FAN6755WMY [ONSEMI]

用于 65 KHz 反激式转换器的绿色模式 PWM 控制器,提供线路过压保护和通电/欠压保护;
FAN6755WMY
型号: FAN6755WMY
厂家: ONSEMI    ONSEMI
描述:

用于 65 KHz 反激式转换器的绿色模式 PWM 控制器,提供线路过压保护和通电/欠压保护

控制器 转换器
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FAN6755W / FAN6755UW  
mWSaverPWM Controller  
Features  
Description  
This highly integrated PWM controller provides several  
features to enhance the performance of flyback  
converters.  
.
mWSaverTechnology Provides Industry’s Best-  
in-Class Standby Power  
<100 mW at 25-mW Load for LCDM Adaptor  
Internal High-Voltage JFET Startup  
To minimize standby power consumption, a proprietary  
adaptive green-mode function reduces switching  
frequency at light-load condition. To avoid acoustic-  
noise problems, the minimum PWM frequency is set  
above 23 kHz. This green-mode function enables the  
power supply to meet international power conservation  
requirements, such as Energy Star®. With the internal  
high-voltage startup circuitry, the power loss caused by  
bleeding resistors is also eliminated. To further reduce  
power consumption, FAN6755W/UW uses the BiCMOS  
process, which allows an operating current of only  
2 mA. The standby power consumption can be under  
100 mW for most of LCD monitor power supply designs.  
Low Operating Current: Under 2 mA  
Adaptively Decrease PWM Frequency to  
23 kHz at Light-Load Condition for Better  
Efficiency  
Feedback Impedance Switching During  
Minimum Load or No Load  
.
.
Proprietary Asynchronous Frequency Hopping  
Technique that Reduces EMI  
Fixed PWM Frequency: 65 kHz (FAN6755W),  
130 kHz (FAN6755UW)  
FAN6755W/UW  
integrates  
a
frequency-hopping  
.
.
.
Internal Leading-Edge Blanking  
function that reduces EMI emission of a power supply  
with minimum line filters. The built-in synchronized  
slope compensation achieves a stable peak-current-  
mode control and improves noise immunity. The  
proprietary line compensation ensures constant output  
power limit over a wide AC input voltage range from  
Built-in Synchronized Slope Compensation  
Auto-Restart Protection: Feedback Open-Loop  
Protection (OLP), VDD Over-Voltage Protection  
(OVP), Over-Temperature Protection (OTP), and  
Line Over-Voltage Protection  
90 VAC to 264 VAC  
.
.
.
.
Soft Gate Drive with Clamped Output Voltage: 18 V  
VDD Under-Voltage Lockout (UVLO)  
FAN6755W/UW provides many protection functions.  
The internal feedback open-loop protection circuit  
protects the power supply from open-feedback-loop  
condition or output-short condition. It also has line  
under-voltage protection (brownout protection) and  
over-voltage protection using an input voltage sensing  
pin (VIN).  
Programmable Constant Power Limit  
(Full AC Input Range)  
.
.
.
Internal OTP Sensor with Hysteresis  
Build-in 5-ms Soft-Start Function  
Input Voltage Sensing (VIN Pin) for Brown-In/Out  
Protection with Hysteresis and Line Over-Voltage  
Protection  
FAN6755W/UW is available in a 7-pin SOP package.  
Applications  
General-purpose switched-mode power supplies and  
flyback power converters, including:  
.
.
LCD Monitor Power Supply  
Open-Frame SMPS  
ENERGY STAR® is a registered trademark of the U.S. Department of Energy and the U.S. Environmental Protection Agency.  
© 2009 Fairchild Semiconductor Corporation  
www.fairchildsemi.com  
FAN6755W / FAN6755UW • Rev. 2, Feb-2020  
Ordering Information  
Operating  
Part Number Temperature  
Range  
PWM  
Frequency  
Packing  
Method  
Package  
7-Lead, Small Outline Integrated Circuit  
(SOIC), Depopulated JEDEC MS-112, .150  
Inch Body  
FAN6755WMY  
-40 to +105°C  
65 kHz  
Reel & Tape  
Reel & Tape  
FAN6755UWMY -40 to +105°C  
130 kHz  
Application Diagram  
N
EMI  
Filter  
Vo+  
Vo-  
+
+
L
1
VIN  
7
2
6
VDD  
HV  
FB  
+
5
GATE  
3
SENSE  
4
FAN6755W  
Figure 1.  
Typical Application  
© 2009 Fairchild Semiconductor Corporation  
FAN6755W / FAN6755UW • Rev. 2, Feb-2020  
www.fairchildsemi.com  
2
Internal Block Diagram  
HV  
7
OTP  
Re-start  
Protection  
OVP  
OLP  
VIN-OVP  
VDD  
Brownout Protection  
Soft  
Driver  
5
GATE  
VPWM  
OSC  
S
R
Q
VDD  
6
Internal  
BIAS  
UVLO  
VRESET  
Soft-Start  
Comparator  
Pattern  
Generator  
Circuit  
Blanking  
SENSE  
Soft-Start  
VLimit  
3
Current Limit  
Comparator  
Green  
Mode  
VRESET  
OVP  
Debounce  
PWM  
VDD-OVP  
Comparator  
5.3V  
Max.  
Duty  
VPWM  
VIN-ON / VIN-OFF  
Slope  
Compensation  
3R  
Brownout Protection  
VLimit  
2
FB  
VIN  
1
High/Low  
Line Compensation  
R
OLP  
Delay  
OLP  
VIN-OVP  
Debounce  
VFB-OLP  
OLP  
Comparator  
VIN-Protect  
4
GND  
Figure 2.  
Internal Block Diagram  
Marking Information  
7
7
Z: Plant Code  
X: 1-Digit Year Code  
Y: 1-Digit Week Code  
TT: 2-Digit Die Run Code  
T: Package Type (M:SOP)  
P: Y=Green Package  
ZXYTT  
6755U  
WTPM  
ZXYTT  
6755  
WTPM  
M: Manufacture Flow Code  
Figure 3. Top Mark  
© 2009 Fairchild Semiconductor Corporation  
FAN6755W / FAN6755UW • Rev. 2, Feb-2020  
www.fairchildsemi.com  
3
Pin Configuration  
SOP-7  
VIN  
FB  
1
2
3
4
7
HV  
SENSE  
6
5
VDD  
GND  
GATE  
Figure 4.  
Pin Configuration (Top View)  
Pin Definitions  
Pin #  
Name  
Description  
Line-voltage detection. The line-voltage detection is used for brownout protection with  
hysteresis. Constant output power limit over universal AC input range is also achieved using this  
VIN pin. It is suggested to add a low-pass filter to filter out line ripple on the bulk capacitor.  
Pulling VIN HIGH also triggers auto-restart protection.  
1
VIN  
The signal from the external compensation circuit is fed into this pin. The PWM duty cycle is  
determined in response to the signal on this pin and the current-sense signal on the SENSE pin.  
2
3
FB  
Current sense. The sensed voltage is used for peak-current-mode control and cycle-by-cycle  
current limiting.  
SENSE  
GND  
4
5
Ground  
GATE The totem-pole output driver. Soft-driving waveform is implemented for improved EMI.  
Power supply. The internal protection circuit disables PWM output as long as VDD exceeds the  
OVP trigger point.  
6
7
VDD  
HV  
For startup, this pin is connected to the line input or bulk capacitor in series with resistors.  
© 2009 Fairchild Semiconductor Corporation  
FAN6755W / FAN6755UW • Rev. 2, Feb-2020  
www.fairchildsemi.com  
4
Absolute Maximum Ratings  
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be  
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.  
In addition, extended exposure to stresses above the recommended operating conditions may affect device  
reliability. The absolute maximum ratings are stress ratings only.  
Symbol  
VVDD  
VFB  
Parameter  
Min.  
Max.  
30  
Unit  
V
DC Supply Voltage(1, 2)  
FB Pin Input Voltage  
-0.3  
-0.3  
-0.3  
7.0  
V
VSENSE  
VVIN  
SENSE Pin Input Voltage  
VIN Pin Input Voltage  
7.0  
V
7.0  
V
VHV  
HV Pin Input Voltage  
700  
400  
V
Power Dissipation (TA50°C)  
PD  
mW  
Thermal Resistance (Junction-to-Air)  
Operating Junction Temperature  
150  
JA  
TJ  
C/W  
C  
-40  
-55  
+125  
+150  
+260  
TSTG  
TL  
Storage Temperature Range  
C  
Lead Temperature (Wave Soldering or IR, 10 Seconds)  
C  
Human Body Model,  
All Pins Except HV Pin  
JEDEC: JESD22-A114  
5.5  
2.0  
ESD  
kV  
Charged Device Model,  
All Pins Except HV Pin  
JEDEC: JESD22-C101  
Notes:  
1. All voltage values, except differential voltages, are given with respect to the network ground terminal.  
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.  
3. ESD with HV pin: CDM=2000 V (FAN6755W) or 1500 V (FAN6755UW), and HBM=3500 V.  
© 2009 Fairchild Semiconductor Corporation  
FAN6755W / FAN6755UW • Rev. 2, Feb-2020  
www.fairchildsemi.com  
5
 
 
Electrical Characteristics  
VDD=15 V, TA=25C, unless otherwise noted.  
Symbol  
Parameter  
Conditions  
Min.  
Typ.  
Max.  
Unit  
VDD Section  
VOP  
Continuously Operating Voltage  
Full Load  
22  
17  
11  
8.8  
30  
2
V
V
VDD-ON Start Threshold Voltage  
VDD-OFF Protection Mode  
15  
9
16  
10  
V
UVLO  
IDD-ST  
Normal Mode  
6.8  
7.8  
V
Startup Current  
VDD-ON – 0.16 V  
µA  
mA  
µA  
IDD-OP  
IDD-OLP  
Operating Supply Current  
Internal Sink Current  
VDD=15 V, GATE Open  
VDD-OLP+0.1 V  
30  
6.5  
25  
75  
60  
7.5  
26  
90  
Threshold Voltage on VDD for HV  
JFET Turn-On  
VDD-OLP  
8.0  
27  
V
V
VDD-OVP VDD Over-Voltage Protection  
VDD Over-Voltage Protection  
tD-VDDOVP  
125  
200  
µs  
Debounce Time  
HV Section  
VDC=120 V, VDD=10 µF,  
VDD=0 V  
IHV  
Supply Current Drawn from HV Pin  
Leakage Current after Startup  
mA  
µA  
2.0  
3.5  
1
5.0  
20  
HV=700 V, VDD=VDD-  
OFF+1 V  
IHV-LC  
VDD  
VDD  
VDD-ON  
VDD-ON  
VDD-OFF  
UVLO  
VDD-OLP  
t
t
Normal Mode  
Protection Mode  
Figure 5.  
VDD Behavior  
Continued on the following page…  
© 2009 Fairchild Semiconductor Corporation  
FAN6755W / FAN6755UW • Rev. 2, Feb-2020  
www.fairchildsemi.com  
6
Electrical Characteristics  
VDD=15 V, TA=25C, unless otherwise noted.  
Symbol  
Parameter  
Conditions  
Min.  
Typ.  
Max.  
Unit  
Oscillator Section  
62  
124  
±4.5  
±9  
65  
130  
±5.2  
±10.4  
23  
68  
136  
±5.9  
±11.8  
26  
FAN6755W  
FAN6755UW  
FAN6755W  
FAN6755UW  
Center  
Frequency  
fOSC  
Frequency in Normal Mode  
kHz  
Hopping  
Range  
fOSC-G  
tHOP  
Green-Mode Frequency  
Hopping Period  
20  
kHz  
ms  
10  
12  
14  
5
Frequency Variation vs. VDD  
Deviation  
fDV  
fDT  
VDD=11 V to 22 V  
%
%
Frequency Variation vs.  
Temperature Deviation  
5
TA=-40 to 85C=TJ  
VIN Section  
PWM Turn-Off (Brown-out)  
0.66  
0.70  
0.74  
VIN-OFF  
VIN-ON  
VIN-Protect  
tVIN-Protect  
V
V
Threshold Voltage  
VIN-OFF  
0.17  
+
VIN-OFF  
0.20  
+
VIN-OFF  
0.23  
+
PWM Turn-On (Brown in)  
Threshold Voltage  
Threshold Voltage of VIN Over-  
Voltage Protection  
5.1  
60  
5.3  
5.5  
V
Debounce Time of VIN Over-  
Voltage Protection  
100  
140  
µs  
Current-Sense Section  
VLIMIT at  
VIN=1 V  
Threshold Voltage for Current Limit VIN=1 V  
Threshold Voltage for Current Limit VIN=3 V  
0.80  
0.67  
0.83  
0.70  
0.86  
0.73  
V
VLIMIT at  
VIN=3 V  
V
tPD  
tLEB  
tSS  
Delay to Output  
100  
150  
290  
5.5  
200  
175  
340  
7.0  
ns  
Soft-Start (FAN6755UW)  
Steady State  
125  
240  
4.0  
Leading-Edge Blanking Time  
Period During Soft-Start Time  
ns  
Startup Time  
ms  
VLimit  
=0.92V  
=5.3V  
VIN-Protect  
VIN-OFF  
VSENSE =0.83V  
VSENSE =0.7V  
VIN  
VIN=1V  
VIN=3V  
Figure 6.  
VIN vs. VSENSE  
Continued on the following page…  
© 2009 Fairchild Semiconductor Corporation  
FAN6755W / FAN6755UW • Rev. 2, Feb-2020  
www.fairchildsemi.com  
7
Electrical Characteristics  
VDD=15 V, TA=25C, unless otherwise noted.  
Symbol  
Parameter  
Conditions  
Min.  
Typ.  
Max.  
Unit  
Feedback Input Section  
AV  
Internal FB Voltage Attenuation  
Input Impedance  
1/4.5  
10  
1/4.0  
15  
1/3.5  
19  
V/V  
kΩ  
V
ZFB  
VFB=4 V  
VFB-OPEN The Maximum Clamp of FB Voltage  
FB Pin Open  
5.1  
5.3  
5.5  
FB Open-Loop Protection Triggering  
VFB-OLP  
Level  
4.4  
4.6  
4.8  
V
Delay Time of FB Pin Open-loop  
Protection  
tD-OLP  
45.0  
2.8  
62.5  
70.0  
3.2  
ms  
VFB-N  
VFB-G  
Green-Mode Entry FB Voltage  
Green-Mode Ending FB Voltage  
3.0  
V
V
VFB-N - 0.6  
FB Threshold Voltage for Zero-Duty  
Recovery  
VFB-ZDCR  
1.6  
1.4  
1.8  
1.6  
2.0  
1.8  
V
V
VFB-ZDC FB Threshold Voltage for Zero-Duty  
VFB-ZDCR -  
ZDC Hysteresis  
VFB-ZDC  
0.12  
0.15  
0.19  
V
Frequency  
+ hopping range  
fOSC  
PWM  
Frequency  
- hopping range  
+1.76KHz  
fOSC-G  
-1.76KHz  
V
FB-ZDCVFB-ZDCRV  
V
FB-N  
VFB  
FB-G  
Figure 7.  
VFB vs. PWM Frequency  
Continued on the following page…  
© 2009 Fairchild Semiconductor Corporation  
FAN6755W / FAN6755UW • Rev. 2, Feb-2020  
www.fairchildsemi.com  
8
Electrical Characteristics  
VDD=15 V, TA=25C, unless otherwise noted.  
Symbol  
Parameter  
Conditions  
Min.  
Typ.  
Max.  
Unit  
GATE Section  
DCYMAX Maximum Duty Cycle  
VGATE-L Gate Low Voltage  
VGATE-H Gate High Voltage  
60  
8
75  
90  
%
V
VDD=15 V, IO=50 mA  
VDD=12 V, IO=50 mA  
VDD=15 V, CL=1 nF  
VDD=15 V, CL=1 nF  
1.5  
V
Gate Rising Time  
Gate Falling Time  
tr  
tf  
ns  
ns  
100  
30  
IGATE-  
SOURCE  
mA  
V
Gate Source Current  
VDD=15 V, GATE=6 V  
VDD=22 V  
700  
VGATE-  
CLAMP  
Gate Output Clamping Voltage  
18  
Over-Temperature Protection Section (OTP)  
TOTP  
TRestart  
Notes:  
Protection Junction Temperature(4,6)  
Restart Junction Temperature(5,6)  
140  
°C  
°C  
TOTP-25  
4. When OTP is activated, the PWM switching is shut down.  
5. When junction temperature is lower than this level, IC resumes PWM switching.  
6. These parameters are guaranteed by design.  
© 2009 Fairchild Semiconductor Corporation  
www.fairchildsemi.com  
FAN6755W / FAN6755UW • Rev. 2, Feb-2020  
9
 
 
 
Typical Performance Characteristics  
Figure 9. Operation Supply Current (IDD-OP  
)
Figure 8. Startup Current (IDD-ST) vs. Temperature  
vs. Temperature  
Figure 10.Start Threshold Voltage (VDD-ON  
)
Figure 11.Minimum Operating Voltage (VDD-OFF  
vs. Temperature  
)
vs. Temperature  
Figure 12.Supply Current Drawn from HV Pin (IHV  
)
Figure 13.HV Pin Leakage Current After Startup  
(IHV-LC) vs. Temperature  
vs. Temperature  
Figure 14.Frequency in Normal Mode (fOSC  
)
Figure 15.Maximum Duty Cycle (DCYMAX  
)
vs. Temperature  
vs. Temperature  
© 2009 Fairchild Semiconductor Corporation  
FAN6755W / FAN6755UW • Rev. 2, Feb-2020  
www.fairchildsemi.com  
10  
Typical Performance Characteristics  
Figure 16.FB Open-Loop Trigger Level (VFB-OLP  
)
Figure 17.Delay Time of FB Pin Open-Loop Protection  
(tD-OLP) vs. Temperature  
vs. Temperature  
Figure 18.PWM Turn-Off Threshold Voltage  
(VIN-OFF & VIN-ON) vs. Temperature  
Figure 19.VDD Over-Voltage Protection (VDD-OVP  
)
vs. Temperature  
Figure 20.VIN vs. VLIMIT  
© 2009 Fairchild Semiconductor Corporation  
FAN6755W / FAN6755UW • Rev. 2, Feb-2020  
www.fairchildsemi.com  
11  
Functional Description  
Startup Current  
Gate Output / Soft Driving  
For startup, the HV pin is connected to the line input or  
bulk capacitor in series with diodes and/or resistors. If HV  
pin is connected to the line input, a 1-kV/ 1-A diode and a  
100 kΩ resistor are recommended. If HV pin is connected  
to the bulk capacitor, only the resistor is required. Startup  
current drawn from pin HV (typically 3.5 mA) charges the  
hold-up capacitor through the diode and resistor. When  
the VDD capacitor level reaches VDD-ON, the startup current  
switches off. At this moment, only the VDD capacitor  
supplies the FAN6755W/UW to maintain VDD before the  
auxiliary winding of the main transformer to provide the  
operating current.  
The BiCMOS output stage is a fast totem-pole gate  
driver. Cross conduction has been avoided to minimize  
heat dissipation, increase efficiency, and enhance  
reliability. The output driver is clamped by an internal  
18 V Zener diode to protect power MOSFET transistors  
against undesirable gate over voltage. A soft-driving  
circuit is implemented to minimize EMI.  
Soft-Start  
For many applications, it is necessary to minimize the  
inrush current at startup. The built-in 5.5 ms soft-start  
circuit significantly reduces the startup current spike  
and output voltage overshoot.  
Operating Current  
Operating current is below 2 mA. The low operating  
current enables better efficiency and reduces the  
requirement of VDD hold-up capacitance.  
Slope Compensation  
The sensed voltage across the current-sense resistor is  
used for peak-current-mode control and pulse-by-pulse  
current limiting. Built-in slope compensation improves  
stability and prevents sub-harmonic oscillation.  
FAN6755W/UW inserts a synchronized positive-going  
ramp at every switching cycle as slope compensation.  
Green-Mode Operation  
The proprietary green-mode function provides an off-  
time modulation to reduce the switching frequency in  
light-load and no-load conditions. The on time is limited  
for better abnormal or brownout protection. VFB, which is  
derived from the voltage feedback loop, is taken as the  
reference. Once VFB is lower than the threshold voltage,  
switching frequency is continuously decreased to the  
minimum green-mode frequency of around 23 kHz.  
Constant Output Power Limit  
For constant output power limit over universal input-  
voltage range, the peak-current threshold is adjusted by  
the voltage of the VIN pin. Since the VIN pin is  
connected to the rectified AC input line voltage through  
the resistive divider, a higher line voltage generates a  
higher VIN voltage. The threshold voltage decreases as  
VIN increases, making the maximum output power at  
high-line input voltage equal to that at low-line input.  
The value of R-C network should not be so large that it  
affects the power limit (shown in Figure 21). R and C  
should be less than 100 and 470 pF, respectively.  
Current Sensing / PWM Current Limiting  
Peak-current-mode control is utilized to regulate output  
voltage and provide pulse-by-pulse current limiting. The  
switching current is detected by the current-sensing  
resistor of SENSE pin. The PWM duty cycle is  
determined by this current sense signal and VFB, the  
feedback voltage. When the voltage on the SENSE pin  
reaches around VCOMP=(VFB–0.6)/4, the PWM switching  
turns off immediately.  
Leading-Edge Blanking (LEB)  
Each time the power MOSFET is switched on, a turn-on  
spike occurs on the sense resistor. To avoid premature  
termination of the switching pulse, a leading-edge  
blanking time is built in. During this blanking period, the  
current-limit comparator is disabled and cannot switch  
off the gate driver.  
FAN6755W  
GATE  
R
Blanking  
SENSE  
Circuit  
C
Under-Voltage Lockout (UVLO)  
The turn-on and turn-off thresholds are fixed internally  
at 16 V and 7.8 V in normal mode. During startup, the  
hold-up capacitor must be charged to 16 V through the  
startup resistor to enable the IC. The hold-up capacitor  
continues to supply VDD before the energy can be  
delivered from auxiliary winding of the main transformer.  
VDD must not drop below 7.8 V during startup. This  
UVLO hysteresis window ensures that the hold-up  
capacitor is adequate to supply VDD during startup.  
Figure 21. Current-Sense R-C Filter  
© 2009 Fairchild Semiconductor Corporation  
FAN6755W / FAN6755UW • Rev. 2, Feb-2020  
www.fairchildsemi.com  
12  
 
RLower  
VDD Over-Voltage Protection  
V
VAC 2,(unit V)  
IN  
(1)  
RLower RUpper  
VDD over-voltage protection prevents damage due to  
abnormal conditions. Once the VDD voltage is over the  
over-voltage protection voltage (VDD-OVP), and lasts for tD-  
VDDOVP, the PWM pulses are disabled. When the VDD  
voltage drops below the UVLO, the internal startup circuit  
turns on, and VDD is charged to VDD-ON to restart IC.  
Thermal Overload Protection  
Thermal overload protection limits total power  
dissipation. When the junction temperature exceeds TJ=  
+140C, the thermal sensor signals the shutdown logic  
and turns off most of the internal circuitry. The thermal  
sensor turns internal circuitry on again after the IC’s  
junction temperature drops by 25C. Thermal overload  
protection is designed to protect the FAN6755W/UW in  
the event of a fault condition. For continual operation,  
the controller should not exceed the absolute maximum  
junction temperature of TJ = +140C.  
Feedback Impedance Switching  
FAN6755W/UW actively varies FB-pin impedance  
(ZFB) to reduce no-load power consumption. This  
technique can further reduce operating current of the  
controller when FB-pin voltage drops below VFB-ZDC  
.
Figure 22 exhibits the range that ZFB changes. When  
VFB is lower than VFB-ZDC, PWM switching is stopped  
and ZFB is switched from 15 kΩ to 90 kΩ. On the other  
hand, ZFB is switched from 90 kΩ to 15 kΩ when VFB is  
Limited Power Control  
higher than VFB-ZDCR  
.
The FB voltage is saturated HIGH when the power  
supply output voltage drops below its nominal value and  
shut regulator (KA431) does not draw current through  
the opto-coupler. This occurs when the output feedback  
loop is open or output is short circuited. If the FB  
voltage is higher than a built-in threshold for longer than  
tD-OLP, PWM output is turned off. As PWM output is  
turned off, VDD begins decreasing since no more energy  
is delivered from the auxiliary winding.  
fosc (kHz)  
Proprietary  
ZFB  
=90k  
ZFB  
=15k  
As the protection is triggered, VDD enters into UVLO  
mode. This protection feature continues as long as the  
over loading condition persists. This prevents the power  
supply from overheating due to overloading conditions.  
VFB(V)  
VFB-ZDC VFB-ZDCR  
Noise Immunity  
Noise on the current sense or control signal may cause  
significant pulse-width jitter, particularly in continuous-  
conduction mode. Slope compensation helps alleviate  
this problem. Good placement and layout practices  
should be followed. Avoiding long PCB traces and  
component leads, locating compensation and filter  
components near the FAN6755W/UW, and increasing  
the gate resistor from GATE pin to MOSFET improve  
performance.  
Figure 22. ZFB-Switching Activating Range  
Brownout Protection  
Since the VIN pin is connected through a resistive  
divider to the rectified AC input line voltage, it can also  
be used for brownout protection. If VIN is less than  
0.7 V, the PWM output is shut off. When VIN reaches  
over 0.9 V, the PWM output is turned on again. The  
hysteresis window for ON/OFF is around 0.2 V. The  
brownout voltage setting is determined by the potential  
divider formed with RUpper and RLower. Equations to  
calculate the resistors are shown below:  
© 2009 Fairchild Semiconductor Corporation  
FAN6755W / FAN6755UW • Rev. 2, Feb-2020  
www.fairchildsemi.com  
13  
 
Typical Application Circuit  
R6  
R7  
12V1  
1
12V  
P1  
C7  
N18  
L2  
2
12V  
C5  
1
3
R8  
C10  
C8  
C9  
+
+
F1  
2
N1  
N1A  
R1  
N2  
BD1  
C1  
C2  
CN1  
TX1  
L
L1  
4
1
N4  
4
12  
11  
N17 D1  
M1  
1
2
3
C3  
N28  
R4  
N21  
ZD1  
VIN  
C4  
R3  
R5  
C6  
AC IN  
R2  
8
N20  
7
5V1  
1
5V  
P2  
L3  
2
5V  
N
N3  
N5 N6  
6
1
C11  
+
1
3
D3  
R14  
2
N7  
10  
9
R17  
2
D4  
C15  
C13  
C14  
+
+
C12  
R13  
D5  
R9  
N8  
P3  
SGND  
Q1  
N30  
R10  
R16  
N10  
D2  
1 N9  
R11  
R12  
N29  
R15  
HV  
VIN  
U1  
VIN  
1
2
3
4
7
HV  
R20  
FB  
VDD  
FB  
5V1  
R22  
R19  
6
5
N12  
N13  
SENSE  
GND  
VDD  
U2  
GATE  
GATE  
12V  
5V  
C16  
C18  
C19  
FAN6755W  
+
R28  
C17  
SENSE  
R23  
R24  
R25  
C20  
R21  
R
N14  
N15  
U3  
N16  
R18  
R26  
R27  
Figure 23. 44 W Flyback 12 V/2 A, 5 V/4 A Application Circuit  
© 2009 Fairchild Semiconductor Corporation  
FAN6755W / FAN6755UW • Rev. 2, Feb-2020  
www.fairchildsemi.com  
14  
Bill of Materials  
Designator  
Part Type  
BD 4 A/600 V  
Designator  
Part Type  
MOS 9 A/600 V  
BD1  
C1  
Q1  
R1  
R2  
R3  
YC 2200 pF/Y1  
YC 2200 pF/Y1  
XC 0.33 µF/300 V  
NC  
R 1.5 M1/4 W  
R 1.5 M1/4 W  
R 10 M1/4 W  
R 47 1/4 W  
NC  
C2  
C3  
C4  
R4, R5, R6, R7  
C5  
R8, R17, R25, R27  
YC 2200 pF/Y1  
CC 2200 pF/100 V  
CC 1000 pF/100 V  
EC 1000 µF/25 V  
EC 470 µF/25 V  
CC 100 pF/50 V  
EC 100 µF/400 V  
C 1 µF/50 V  
C6  
R9  
R 50 K1/4 W  
R 50 K1/4 W  
R 0 1/8 W  
C7  
R10  
R11  
R12  
R13  
R14  
R15  
R16  
R18  
R19  
R20  
R21  
R22  
R23  
R24  
R26  
R28  
TX1  
U1  
C8  
C9  
R 47 1/8 W  
R 100 K1/8 W  
R 0 1/4 W  
C10  
C11  
C12  
C13  
C14  
C15  
C16  
C17  
C18  
C19  
C20  
D1  
R 10 K1/8 W  
R 1 1/8 W  
EC 1000 µF/10 V  
EC 470 µF/10 V  
CC 100 pF/50 V  
C 1 nF/50 V  
R 0 1/8 W  
R 100 1/8 W  
R 1 K1/8 W  
R 4.7 K1/8 W  
R 7.5 K1/8 W  
R 120 K1/8 W  
R 15 K1/8 W  
R 10 K1/8 W  
R 0.43 2 W  
800 µH(ERL-28)  
IC FAN6755W  
IC PC817  
C 470 pF/50 V  
EC 47 µF/50 V  
C 0.01 µF/50 V  
C 0.1 µF/50 V  
FYP1010  
D2  
1N4148  
D3  
FR107  
D4  
FR103  
D5  
U2  
FYP1010  
ZD1  
F1  
P6KE150A  
U3  
IC TL431  
FUSE 4A/250V  
VZ 9G  
M1  
L1  
13 mH  
L2  
Inductor (2 µH)  
Inductor (2 µH)  
L3  
© 2009 Fairchild Semiconductor Corporation  
FAN6755W / FAN6755UW • Rev. 2, Feb-2020  
www.fairchildsemi.com  
15  
Physical Dimensions  
5.00  
4.80  
A
3.81  
0.65TYP  
1.75TYP  
3.81  
6
5
7
7
B
6.20  
5.80  
4.00  
3.80  
3.85 7.35  
3
2
1
4
PIN #1  
1.27  
0.25  
C B A  
(0.33)  
1.27  
TOP VIEW  
LAND PATTERN RECOMMENDATION  
SEE DETAIL A  
0.25  
0.19  
0.25  
0.10  
C
OPTION A - BEVEL EDGE  
1.75 MAX  
0.10 C  
0.51  
0.33  
FRONT VIEW  
OPTION B - NO BEVEL EDGE  
0.50  
0.25  
x 45°  
NOTES:  
R0.10  
R0.10  
GAGE PLANE  
A) THIS PACKAGE DOES NOT FULLY CONFORMS  
TO JEDEC MS-012, VARIATION AA, ISSUE C,  
DATED MAY 1990.  
0.36  
B) ALL DIMENSIONS ARE IN MILLIMETERS.  
8°  
0°  
C) DIMENSIONS DO NOT INCLUDE MOLD  
FLASH OR BURRS.  
SEATING PLANE  
0.90  
(1.04)  
DETAIL A  
0.406  
D) STANDARD LEAD FINISH:  
200 MICROINCHES / 5.08 MICRONS MIN.  
LEAD/TIN (SOLDER) ON COPPER.  
SCALE: 2:1  
E) DRAWING FILENAME : M07Arev3  
Figure 24. 7-Lead, Small Outline Package (SOP)  
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any  
manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative  
to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and  
conditions, specifically the warranty therein, which covers Fairchild products.  
© 2009 Fairchild Semiconductor Corporation  
FAN6755W / FAN6755UW • Rev. 2, Feb-2020  
www.fairchildsemi.com  
16  
ON Semiconductor and  
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.  
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent  
coverage may be accessed at www.onsemi.com/site/pdf/PatentMarking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.  
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