FAN6862TY [ONSEMI]
用于反激转换器的 6 引脚绿色模式 PWM 控制器，65KHz;
| 型号： | FAN6862TY |
| 厂家： | 
ONSEMI |
| 描述： | 用于反激转换器的 6 引脚绿色模式 PWM 控制器，65KHz 控制器 开关 光电二极管 转换器 |
| 文件： | 总18页 (文件大小：1230K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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FAN6862
Highly Integrated Green-Mode PWM Controller
Features
Description
.
.
.
Low Startup Current: 8µA
A highly integrated PWM controller, FAN6862 provides
several features to enhance the performance of flyback
converters. To minimize standby power consumption, a
proprietary green-mode function provides off-time
modulation to continuously decrease the switching
frequency under light-load conditions. Under zero-load
conditions, the power supply enters burst-mode, which
completely shuts off PWM output. Output restarts just
before the supply voltage drops below the UVLO lower
limit. This green-mode function enables power supplies
to meet international power conservation requirements.
Low Operating Current in Green Mode: 3mA
Peak-Current Mode Operation with Cycle-by-Cycle
Current Limiting
.
PWM Frequency Continuously Decreasing with
Burst Mode at Light Loads
.
.
.
.
VDD Over-Voltage Protection (OVP)
Constant Output Power Limit (Full AC Input Range)
Internal Latch Circuit for OVP, OTP
The FAN6862 is designed for SMPS and integrates a
frequency-hopping function that helps reduce EMI
emission of a power supply with minimum line filters.
The built-in synchronized slope compensation is
proprietary sawtooth compensation for constant output
power limit over universal AC input range. The gate
output is clamped at 18V to protect the external
MOSFET from over-voltage damage.
Fixed PWM Frequency (65KHz) with Frequency
Hopping
.
.
.
Feedback Open-Loop Protection with 56ms Delay
Soft Start Time: 4ms
400mA Driving Capability
Other protection functions include VDD over-voltage
protection and over-temperature protection. For over-
temperature protection, an external NTC thermistor can
be applied to sense the ambient temperature. When VDD
OVP or OTP is activated, an internal latch circuit latches
off the controller.
Applications
General-purpose switch-mode power supplies and
flyback power converters, including:
.
.
.
Power Adapters
Open-Frame SMPS
Part Number
FAN6862TY
FAN6862NY
OVP
Latch
Latch
OTP
OLP
SMPS with Surge-Current Output, such as for
Printers, Scanners, and Motor Drivers
Latch Auto Restart
Latch Auto Restart
Ordering Information
Operating Temperature
Part Number
Package
Packing Method
Range
FAN6862TY
FAN6862NY
-40 to +105°C
-40 to +105°C
6-Pin SSOT-6
8-Pin Dual In-Line Package (DIP)
Tape & Reel
Tube
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN6862 • Rev. 2, Feb-2020
Typical Application
Figure 1. Typical Application
Block Diagram
Figure 2. Block Diagram
© 2009 Fairchild Semiconductor Corporation
FAN6862 • Rev. 2, Feb-2020
www.fairchildsemi.com
2
Marking Information
ABx:
TT:
ABD: FAN6862TY
Wafer Lot Code
: Year Code
Week Code
_ _ _:
F – Fairchild Logo
Z – Plant Code
X – 1-Digit Year Code
Y – 1-Digit Week Code
TT – 2-Digit Die Run Code
T – Package Type (N:DIP)
P – Y: Green Package
M – Manufacture Flow Code
Figure 3. Top Mark
Pin Configuration
Figure 4. SSOT-6
Figure 5. DIP-8
Pin Definitions
Pin #
SSOT-6
Pin # DIP8
Name
Description
8
1
GND
Ground.
Feedback. The FB pin provides the output voltage regulation signal. It
provides feedback to the internal PWM comparator, so that the PWM
comparator can control the duty cycle. This pin also provide for OLP: if
VFB is larger than the trigger level and delays for a long time, the
controller stops and restarts.
7
6
5
2
FB
NC
RT
No Connect Pin
Temperature Detection. An external NTC thermistor is connected from
this pin to GND for over-temperature protection. The impedance of the
NTC decreases at high temperatures. Once the voltage of the RT pin
drops below a threshold,
3
4
PWM output is disabled.
Current Sense. This pin senses the voltage across a resistor. When the
voltage reaches the internal threshold, PWM output is disabled. This
activates over-current protection. This pin also provides current
amplitude information for current-mode control.
4
SENSE
3
2
NC
No Connect Pin
Power Supply.
5
6
VDD
Driver Output. The totem-pole output driver for driving the power
MOSFET.
1
GATE
© 2009 Fairchild Semiconductor Corporation
FAN6862 • Rev. 2, Feb-2020
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only. All voltage values, except differential voltages, are given with
respect to GND pin.
Symbol
VDD
Parameter
Min.
Max.
30
Unit
V
Supply Voltage
VL
Input Voltage to FB, SENSE, RT Pin
-0.3
7.0
V
SSOT-6
DIP-8
300
800
115
67
PD
Power Dissipation at TA<50°C
mW
SSOT-6
DIP-8
ΘJC
Thermal Resistance (Junction-to-Case)
°C/W
TJ
TSTG
TL
Operating Junction Temperature
-40
-55
+150
+150
+260
3.00
1.25
°C
°C
°C
Storage Temperature Range
Lead Temperature, Wave Soldering, 10 Seconds
Human Body Model, JESD22-A114
Charge Device Model, JESD22-C101
ESD
kV
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Max.
Unit
TA
Operating Ambient Temperature
-40
+105
°C
© 2009 Fairchild Semiconductor Corporation
FAN6862 • Rev. 2, Feb-2020
www.fairchildsemi.com
4
Electrical Characteristics
VDD = 15V and TA = 25°C unless otherwise noted.
Symbol
Parameter
Test Condition
Min.
Typ. Max. Unit
VDD Section
VDD-OP
VDD-ON
VDD-OFF
VDD-LH
Continuously Operating Voltage
Turn-on Threshold Voltage
Turn-off Voltage
24
17
9.5
5
V
V
15
7.5
3
16
8.5
4
V
Threshold voltage for Latch-Off release
Startup Current
V
IDD-ST
VDD-ON–0.16V
CL=1nF
8
30
4
μA
mA
mA
V
IDD-OP
Normal Operating Supply Current
Green-Mode Operating Supply Current
VDD Over-Voltage Protection
VDD OVP Debounce Time
Latch-Off Holding Current
3
IDD-BM
GATE open, VFB=VFB-G
2.5
26
50
65
VDD-OVP
tD-VDDOVP
IDD-LH
24
25
30
40
μs
μA
VDD=5V
Feedback Input Section
AV
ZFB
Input-Voltage to Current-Sense Attenuation
1/4.0
1/3.5 1/3.0
5.5
V/V
kΩ
V
Input Impedance
VFB-OPEN
FB Pin Open Voltage
5.0
4.3
53
5.2
4.6
56
5.4
4.9
60
Threshold Voltage for Open-Loop
Protection
VFB-OLP
tD-OLP
V
Open-Loop Protection Delay Time
ms
Current Sense Section
tPD
Delay to Output
100
360
250
ns
ns
V
tLEB
Leading-Edge Blanking Time
270
0.47
0.41
VSTHFL
VSTHVA
VSLOPE
Flat Threshold Voltage for Current Limit
Valley Threshold Voltage for Current Limit
Slope Compensation
Duty>51%
Duty=0%
0.50
0.44
0.273
4.00
0.53
0.47
V
Duty=DCYMAX
V
tSOFT-START Period During Startup time
2.50
5.25
ms
Oscillator Section
Center
Frequency
VFB>VFB-N
62
65
68
fOSC
Normal PWM Frequency
kHz
±3.7
±4.2
±4.7
Hopping Range
VFB≥VFB-N
Hopping Range*1 VFB=VFB-G
±2.9
4.4
thop-1
thop-3
Hopping Period 1*1
Hopping Period 3*1
VFB≥VFB-N
ms
ms
VFB=VFB-G
11.5
22.5
fOSC-G
Green Mode Minimum Frequency
18.0
2.0
25.0
2.4
kHz
FB Threshold Voltage For Frequency
Reduction
VFB-N
2.2
V
VFB-G
VFB-ZDC
fDV
FB Voltage at fOSC-G
1.9
2.1
1.7
2.3
V
V
FB Threshold Voltage for Zero Duty
Frequency Variation vs. VDD Deviation
VDD=11.5V to 20V
TA= -40 to +105°C
0
0.02
2.00
2
%
Frequency Variation vs. Temperature
Deviation
fDT
%
Continued on the following page…
© 2009 Fairchild Semiconductor Corporation
FAN6862 • Rev. 2, Feb-2020
www.fairchildsemi.com
5
Electrical Characteristics (Continued)
VDD = 15V and TA = 25°C unless otherwise noted.
Symbol
Parameter
Test Condition
Min.
Typ. Max.
Unit
PWM Output Section
DCYMAX
VOL
Maximum Duty Cycle
Output Voltage Low
65
6
70
75
%
V
VDD=15V, IO=50mA
VDD=8V, IO=50mA
CL=1nF
1.5
VOH
Output Voltage High
Rising Time
V
tR
150
35
200
80
ns
ns
V
tF
Falling Time
CL=1nF
VCLAMP
Gate Output Clamping Voltage
VDD=20V
15.0
16.5
18.0
Over-Temperature Protection (OTP) Section
IRT
Output Current of RT Pin
92
0.95
15
100
108
1.05
19
μA
Threshold Voltage for Over-Temperature
Protection
VOTP
TA=25°C
1.00
V
VFB=VFB-N
17
51
tDOTP
Over-Temperature Debounce Time
ms
(1)
VFB=VFB-G
2nd Threshold Voltage for Over-Temperature
Protection
2nd Over-Temperature Debounce Time
VOTP2
TA=25°C
0.60
80
0.70
100
0.75
190
V
tDOTP2
Note:
μs
1. Guarantee by Design.
© 2009 Fairchild Semiconductor Corporation
FAN6862 • Rev. 2, Feb-2020
www.fairchildsemi.com
6
Typical Performance Characteristics
17
16.6
16.2
15.8
15.4
15
9.5
9.1
8.7
8.3
7.9
7.5
-40
-30
-15
0
25
50
75
85
100
125
125
125
-40
-30
-15
0
25
50
75
85
100
125
Temperature (ºC)
Temperature (ºC)
Figure 6. Turn-on Threshold Voltage (VDD-ON
)
Figure 7. Turn-off Threshold Voltage (VDD-OFF
)
vs. Temperature
vs. Temperature
4.5
4.1
3.7
3.3
2.9
2.5
26
25.6
25.2
24.8
24.4
24
-40
-30
-15
0
25
50
75
85
100
-40
-30
-15
0
25
50
75
85
100
125
Temperature (ºC)
Temperature (ºC)
Figure 8. Operating Current (IDD-OP
vs. Temperature
)
Figure 9. VDD Over-Voltage Protection (VDD-OVP
vs. Temperature
)
68
67
66
65
64
63
62
2.2
2.12
2.04
1.96
1.88
1.8
-40
-30
-15
0
25
50
75
85
100
-40
-30
-15
0
25
50
75
85
100
125
Temperature (ºC)
Temperature (ºC)
Figure 10. Center Frequency (fOSC) vs. Temperature
Figure 11. FB Threshold Voltage for Frequency
Reduction (VFB-N) vs. Temperature
© 2009 Fairchild Semiconductor Corporation
FAN6862 • Rev. 2, Feb-2020
www.fairchildsemi.com
7
Typical Performance Characteristics (Continued)
2.2
2.12
2.04
1.96
1.88
1.8
4.9
4.8
4.7
4.6
4.5
4.4
-40
-30
-15
0
25
50
75
85
100
125
-40
-30
-15
0
25
50
75
85
100
125
Temperature (ºC)
Temperature (ºC)
Figure 12. FB Voltage at fOSC-G (VFB-G
vs. Temperature
)
Figure 13. Threshold Voltage for Open-Loop
Protection (VFB-OLP) vs. Temperature
59
58
57
56
55
54
53
0.6
0.56
0.52
0.48
0.44
0.4
-40
-30
-15
0
25
50
75
85
100
125
-40
-30
-15
0
25
50
75
85
100
125
Temperature (ºC)
Temperature (ºC)
Figure 14. Open-Loop Protection Delay Time (tD-OLP
vs. Temperature
)
Figure 15. Flat Threshold Voltage for Current Limit
(VSTHFL) vs. Temperature
0.55
0.51
0.47
0.43
0.39
0.35
5
4
3
2
1
0
-40
-30
-15
0
25
50
75
85
100
125
-40
-30
-15
0
25
50
75
85
100
125
Temperature (ºC)
Temperature (ºC)
Figure 16. Valley Threshold Voltage for Current Limit
(VSTHVA) vs. Temperature
Figure 17. Period during Startup (tSOFT-START
)
vs. Temperature
© 2009 Fairchild Semiconductor Corporation
FAN6862 • Rev. 2, Feb-2020
www.fairchildsemi.com
8
Typical Performance Characteristics (Continued)
72
71
70
69
68
67
200
180
160
140
120
100
-40
-30
-15
0
25
50
75
85
100
125
-40
-30
-15
0
25
50
75
85
100
125
Temperature (ºC)
Temperature (ºC)
Figure 18. Maximum Duty Cycle (DCYMAX
vs. Temperature
)
Figure 19. Rising Time (tR) vs. Temperature
50
40
30
20
10
0
120
112
104
96
88
80
-40
-30
-15
0
25
50
75
85
100
125
-40
-30
-15
0
25
50
75
85
100
125
Temperature (ºC)
Temperature (ºC)
Figure 20. Falling Time (tF) vs. Temperature
Figure 21. Output Current of RT Pin (IRT
)
vs. Temperature
© 2009 Fairchild Semiconductor Corporation
FAN6862 • Rev. 2, Feb-2020
www.fairchildsemi.com
9
Operation Description
Startup Operation
Figure 22 shows a typical startup circuit and transformer
auxiliary winding for a FAN6862 application. Before
FAN6862 begins switching operation, it consumes only
startup current (typically 8μA) and the current supplied
through the startup resistor charges the VDD capacitor
(CDD). When VDD reaches turn-on voltage of 16V (VDD-
ON), FAN6862 begins switching and the current
consumed increases to 3mA. Then, the power required
is supplied from the transformer auxiliary winding. The
large hysteresis of VDD (8.5V) provides more holdup
time, which allows using a small capacitor for VDD. The
startup resistor is typically connected to AC line for a
fast reset of latch protection.
Figure 23. PWM Frequency
VDL
+
Np
Vo
CDL
-
VFB
CDD
NA
AC line
R START
VFB.ZDC
(1.7V)
FAN6862
6
5
4
GND
1
2
GATE
Ids
FB
RT
VDD
3
SENSE
Switching
Disabled
Switching
Disabled
Figure 22. Startup Circuit
Figure 24. Burst Mode Operation
Frequency Hopping
Green-Mode Operation
EMI reduction is accomplished by frequency hopping,
which spreads the energy over a wider frequency range
than the bandwidth measured by the EMI test
equipment. An internal frequency hopping circuit
changes the switching frequency between 60.8kHz and
69.2kHz with a period of 4.4ms, as shown in Figure 25.
The FAN6862 uses feedback voltage (VFB) as an
indicator of the output load and modulates the PWM
frequency, as shown in Figure 23, such that the
switching frequency decreases as load decreases. In
heavy load conditions, the switching frequency is
65KHz. Once VFB decreases below VFB-N (2.2V), the
PWM frequency starts to linearly decrease from 65KHz
to 22.5kHz to reduce the switching losses. As VFB
decreases below VFB-G (2.1V), the switching frequency
is fixed at 22.5kHz and FAN6862 enters “deep” green
mode, where the operating current decreases to 2.5mA
(maximum), further reducing the standby power
consumption. As VFB decreases below VFB-ZDC (1.7V),
FAN6862 enters burst-mode operation. When VFB drops
below VFB-ZDC, FAN6862 stops switching and the output
voltage starts to drop, which causes the feedback
voltage to rise. Once VFB rises above VFB-ZDC, switching
resumes. Burst mode alternately enables and disables
switching, thereby reducing switching loss in standby
mode, as shown in Figure 24.
fs
69.2kHz
65.0kHz
60.8kHz
t
4.4ms
Figure 25. Frequency Hopping
© 2009 Fairchild Semiconductor Corporation
FAN6862 • Rev. 2, Feb-2020
www.fairchildsemi.com
10
Protections
Self-protective functions include VDD Over-Voltage
Protection (OVP), Open-Loop / Overload Protection
(OLP), Over-Current Protection (OCP), Short-Circuit
Protection, and Over-Temperature Protection (OTP).
OLP, OCP, and SCP are auto-restart mode protections;
while OVP and OTP are latch-mode protections.
Open-Loop / Over-Load Protection (OLP)
When the upper branch of the voltage divider for the
shunt regulator (KA431 shown) is broken, as shown in
Figure 27, no current flows through the opto-coupler
transistor, which pulls up the feedback voltage to 5.2V.
When the feedback voltage is above 4.6V longer than
56ms, OLP is triggered. This protection is also triggered
when the SMPS output drops below the nominal value
longer than 56ms due to the overload condition.
Auto-Restart Mode Protection: Once a fault condition
is detected, switching is terminated and the MOSFET
remains off. This causes VDD to fall because no more
power is delivered from auxiliary winding. When VDD
falls to VDD-OFF (8.5V), the protection is reset and the
operating current reduces to startup current, which
causes VDD to rise. FAN6862 resumes normal operation
when VDD reaches VDD-ON (16V). In this manner, the
auto-restart can alternately enable and disable the
switching of the MOSFET until the fault condition is
eliminated (see Figure 26).
Latch-Mode Protection: Once this protection is
triggered, switching is terminated and the MOSFET
remains off. The latch is reset only when VDD is
discharged below 4V by unplugging AC power line.
VFB
5.2V
VFB-OLP (4.6V)
OLP Triggers
OLP Shutdown Delay Time
Figure 27. OLP Operation
VDD Over-Voltage Protection (OVP)
VDD over-voltage protection prevents IC damage caused
by over voltage on the VDD pin. The OVP is triggered
when VDD reaches 25V. A debounce time (typically
30µs) prevents false triggering by switching noise.
Over-Temperature Protection (OTP)
The OTP circuit is composed of current source and
voltage comparators. Typically, an NTC thermistor is
connected between the RT and GND pins. Once the
voltage of this pin drops below a threshold of 1.0V,
PWM output is disabled after tDOTP debounce time. If this
pin drops below 0.7V, it triggers the latch-off protection
immediately after tDOTP2 debounce time.
Figure 26. Auto Restart Operation
Over-Current Protection (OCP)
FAN6862 has over-current protection thresholds. It is for
pulse-by-pulse current limit, which turns off MOSFET for
the remainder of the switching cycle when the sensing
voltage of MOSFET drain current reaches the threshold.
The other threshold is for the over-current protection,
which shuts down the MOSFET gate when the sensing
voltage of MOSFET drain current is above the threshold
longer than the shutdown delay (56ms).
© 2009 Fairchild Semiconductor Corporation
FAN6862 • Rev. 2, Feb-2020
www.fairchildsemi.com
11
Leading-Edge Blanking (LEB)
Constant Output Power Limit
Each time the power MOSFET is switched on, a turn-on
spike occurs across the sense-resistor caused by
primary-side capacitance and secondary-side rectifier
reverse recovery. To avoid premature termination of the
switching pulse, a leading-edge blanking time is built in.
During this blanking period (360ns), the PWM
comparator is disabled and cannot switch off the gate
driver. Thus, RC filter with a small RC time constant is
enough for current sensing.
FAN6862 has saw-limiter for pulse-by-pulse current
limit, which guarantees almost constant power limit over
different line voltages of universal input range.
The conventional pulse-by-pulse current limiting scheme
has a constant threshold for current limit comparator,
which results in a higher power limit for high line
voltage. FAN6862 has a sawtooth current limit threshold
that increases progressively within a switching cycle,
which provides lower current limit for high line and
makes the actual power limit level almost constant over
different line voltages of universal input range, as shown
in Figure 28.
Figure 29. Current Sense R-C Filter
Soft-Start
The FAN6862 has an internal soft-start circuit that
increases pulse-by-pulse current-limit comparator
inverting input voltage slowly after it starts. The typical
soft-start time is 4ms. The pulsewidth to the power
MOSFET is progressively increased to establish the
correct working conditions for transformers, rectifier
diodes, and capacitors. The voltage on the output
capacitors is progressively increased with the intention
of smoothly establishing the required output voltage. It
also helps prevent transformer saturation and reduces
the stress on the secondary diode during startup.
Figure 28. Sawtooth Current Limiter
© 2009 Fairchild Semiconductor Corporation
FAN6862 • Rev. 2, Feb-2020
www.fairchildsemi.com
12
Applications Information
NTC1
SCK053
F1
3.15A
C1
R3
L1
R1
C 102P/1206
R 47R/1206
BD1
R 1.5M/1206
2
1N5
N4
1
BD2A/600V
M1
MOV
+1
L3
VO
TR1
L1
900uH
L2
TRN-0211
4
1
N1
N2
1
3
6
1
2
VO
C2
10uH
2
C5
R7
R 100K/1206
R 750K/1206
飛ꢀ
LED1
C 472pF/1KV
R4
3
R2
+
R 1.5M/1206
+
D1
+
C4
N3 11
C11
N1
D120A/100V
C82uF/450V
D2
D 1N4007
C6
R10
R 1K/1206
R5
SGN
R 750K/1206
-1
C3
YC470p/400V
10
7
RM8
Q1
飛ꢀ
MOS 6A/600V
D3
D 1N4007
1
R17
R8
R9
R6
R 0R22/1W R 0R/0805
R 100/1206
U1
GND GATE
GND
FB
1
2
6GATE
D4
5
4
VDD
SENSE
1
2
FB
RT
VDD
D 1N4148
RT 3
C7
C 102P/0805
SENSE
+
+
C12
C9
R11 FAN6862
R 5.6K/0805
C/4.7uF/50V
C/10uF/50V
C8
C 471p/0805
NTC2
TTC 100K
R13
R 560/0805
R12
U3
PC817
R/100/1206
R16
R 39K/1206
C10
R14
R 10K/0805
C 0.1uF/0805
U2
TL431
R
R15
R 10K/0805
Figure 30. 36W (12V/3A) Application Circuit
BOM
Designator
BD1
D1
Part Type
Designator
C8
Part Type
2KBP06M 2A/600V
CC 470pF/50V
EC 10µF/50V
CC 0.1µF/50V
EC 4.7µF/50V
Y2010DN 20A/100V
1N4007
C9
D2, D3
D4
C10
1N4148
C12
F1
Fuse 3.15A/250V
NTC Thermistor SCK053
NTC Thermistor TTC 100KΩ
900µH
R1, R2
R3
R 1.5MΩ (option)
R 47Ω
NTC1
NTC2
L1
R4, R5
R6, R12
R7
R 750KΩ (option)
R 100Ω
L2
10mH
R 100KΩ
R 0.22Ω / 1W
R 0Ω
L3
10µH
R8
TR1
M1
RM-8 400µH
VZ 9G
R9
R10
R 1KΩ
LED1
C1
LED
R11
R 5.6KΩ
CC 1nF
R13
R 560Ω
C2
XC 0.33µF/275V
YC 470pF/400V
EC 82µF/400V
CC 4.7nF/1KV
EC 680µF/25V
CC 1nF
R14, R15
R16
R 10KΩ
C3
R 39KΩ
C4
U1
IC FAN6862
TL431
C5
U2
C6, C11
C7
U3
PC-817
Q1
MOSFET 6A/600V
© 2009 Fairchild Semiconductor Corporation
FAN6862 • Rev. 2, Feb-2020
www.fairchildsemi.com
13
Physical Dimensions
Figure 31. 6-Pin, SUPERSOT6 “SSOT-6”, JEDEC MO-193, 1.6mm Wide Package
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
© 2009 Fairchild Semiconductor Corporation
FAN6862 • Rev. 2, Feb-2020
www.fairchildsemi.com
14
Physical Dimensions
0.400 10.160
0.355 9.017
[
]
8
5
PIN 1 INDICATOR
0.280 7.112
0.240 6.096
[
]
1
4
HALF LEAD 4X
0.005 [0.126]
FULL LEAD 4X
0.005 [0.126] MIN
0.325 8.263
0.300 7.628
[
]
0.195 4.965
MAX 0.210 [5.334]
0.115
[
2.933
]
SEATING PLANE
0.150 3.811
0.115
[
2.922
]
C
MIN 0.015 [0.381]
0.100 [2.540]
0.300 [7.618]
0.045 1.144
0.030 0.763
4X
[
]
0.430 [10.922]
MAX
0.022 0.562
0.014
[
0.358
]
0.070 1.778
0.045 1.143
4X
[
]
0.10
C
NOTES:
A) THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BA
B) CONTROLING DIMS ARE IN INCHES
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSIONS AND TOLERANCES PER ASME
Y14.5M -1982
E) DRAWING FILENAME AND REVSION: MKT-N08MREV1.
Figure 32. 8-Pin Dual In-Line Package (DIP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
© 2009 Fairchild Semiconductor Corporation
FAN6862 • Rev. 2, Feb-2020
www.fairchildsemi.com
15
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