FAN73711MX [ONSEMI]
625V，3.3/5V 输入逻辑，可兼容 4/4A 接收/源电流，高压侧门极驱动集成电路;
| 型号： | FAN73711MX |
| 厂家： | 
ONSEMI |
| 描述： | 625V，3.3/5V 输入逻辑，可兼容 4/4A 接收/源电流，高压侧门极驱动集成电路 栅 驱动 高压 光电二极管 接口集成电路 |
| 文件： | 总13页 (文件大小：679K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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2013 年 11 月
FAN73711
大电流高侧栅极驱动 IC
产品特性
浮动通道可实现高达 +600V 的自举运行
4 A / 4 A 的源电流 / 灌电流驱动能力
共模 dv/dt 噪声消除电路
兼容 3.3V 和 5V 逻辑输入电平
输出与输入信号同相
说明
FAN73711 是单片高侧栅极驱动 IC，可以驱动工作电压
最高达 +600V 的高速 MOSFET 和 IGBT。它具有缓冲输
出级，且所有 NMOS 晶体管设计为具有高脉冲电流驱动
能力和最低交叠导通。
VBS 欠压锁定
飞兆的高压工艺和共模噪声消除技术 s 可使高侧驱动器在
高 dv/dt 噪声环境下稳定运行。先进的电平转换电路，能
使高侧栅极驱动器的工作电压在 VBS=15V 时高达 VS=-
9.8 V （典型值）。UVLO 电路可防止 VBS 低于指定阈值
电压时发生故障。
VDD 和 VBS 上的内置分流稳压器
8 引脚小尺寸封装 (SOP)
大电流和低输出压降功能使得此器件适合作为等离子显示
板的维持放电和能量恢复电路开关驱动器、电机驱动逆变
器、开关电源和大功率 DC-DC 转换器应用中的。
应用
高速栅极驱动器
PDP 应用中维持放电开关驱动器
PDP 应用中能量恢复电路开关驱动器
大功率降压转换器
8-SOP
电机驱动逆变器
订购信息
器件编号
工作温度范围
-40°C ~ 125°C
封装
封装方法
FAN73711MX
8-SOP
卷带和卷盘
© 2009 飞兆半导体公司
FAN73711 • Rev. 1.0.1
www.fairchildsemi.com
典型应用电路图
15V
DBOOT3
RBOOT3
VS
15V
FAN73711
VDD
RBOOT1
DBOOT1
VB
1
2
3
4
8
7
6
5
Q3
R3
HO
VS
IN
IN3
D3
D4
FAN73711
CBOOT3
R4
NC
1
2
3
4
VB
HO
VS
VDD
IN
8
7
6
5
L1
GND
NC
IN1
CBOOT1
D1
D2
NC
R1
GND
NC
To Panel
DBOOT2
R2
Q1
FAN73711
FAN73711
VDD
1
2
3
4
VDD
VB
HO
VS
8
7
6
5
8
7
6
5
VB
1
2
3
4
Q2
Q4
R5
CBOOT2
R7
R8
HO
VS
IN
IN
IN2
IN4
R6
NC
NC
C1
C3
GND
NC
NC
GND
C2
Energy Recovery System
Sustain Drive Part
FAN73711 Rev.01
图 1. 浮动双向开关和半桥驱动器：PDP 应用
15V
VIN
RBOOT
DBOOT
FAN73711
VB
VDD
1
2
8
R1
CBOOT
HO
IN
PWM
7
6
L1
R2
NC
GND
VS
3
4
C1
NC
C2
VOUT
5
D1
FAN73711 Rev.01
图 2. 降压式 （Buck） DC-DC 转换器应用
© 2009 飞兆半导体公司
www.fairchildsemi.com
FAN73711 • Rev. 1.0.1
2
内部框图
VDD
VDD
1
4
8
7
6
VB
HO
VS
UVLO
R
GND
R
NOISE
CANCELLER
IN
2
S
Q
110K
Pin 3 and 5 are no connection.
FAN73711 Rev.01
图 3. 功能性框图
引脚布局
VDD
IN
1
2
3
4
8
VB
7
6
5
HO
VS
FAN73711
NC
GND
NC
FAN73711 Rev.01
图 4. 引脚布局 （顶视图）
引脚说明
引脚号
名称
VDD
IN
说明
1
2
3
4
5
6
7
8
电源电压
高侧栅极驱动器输出的逻辑输入
无连接
NC
GND
NC
VS
接地
无连接
高侧浮动电源电压返回
高侧驱动输出
高侧浮动电源
HO
VB
© 2009 飞兆半导体公司
www.fairchildsemi.com
FAN73711 • Rev. 1.0.1
3
绝对最大额定值
应力超过绝对最大额定值，可能会损坏设备。在超出推荐的工作条件的情况下，该器件可能无法正常运行或操作，且不
建议让器件在这些条件下长期工作。此外，长期工作在在高于推荐的工作条件下工作，会影响器件的可靠性。绝对最大
额定值仅是额定应力值。 TA=25°C，除非另有规定。
符号
VS
特性
最小值
VB-VSHUNT
-0.3
最大值
VB+0.3
625.0
VB+0.3
VSHUNT
VDD+0.3
± 50
单位
V
高侧浮动偏 O 置电压 (1)
高侧浮动电源电压
高侧浮动输出电压
低侧和逻辑电源电压 (1)
逻辑输入电压
允许偏置电压变化速率
功耗 (2, 3, 4)
VB
V
VHO
VDD
VIN
VS-0.3
-0.3
V
V
-0.3
V
dVS/dt
PD
V/ns
W
0.625
θJA
200
°C/W
°C
°C
热阻
TJ
-55
-55
+150
结温
TSTG
+150
存储温度
注意：
1.
2.
3.
此IC包含VDD和VBS的电压调节器。此电源引脚不得被大于在“电气特性”部分指定的 VSHUNT的低阻抗电压源驱动。
安装在 76.2 x 114.3 x 1.6mm PCB 板上 (FR-4 环氧玻璃材料 )。
请查阅以下标准：
JESD51-2：集成电路热测试方法环境条件、自然对流和
JESD51-3：含铅表面贴装封装的低有效导热系数测试板。
4.
任何环境下，都请勿超过功耗 (PD)。
推荐工作条件
推荐的工作条件表明确了器件的真实工作条件。指定推荐的工作条件，以确保设备的最佳性能达到数据表中的规格。
飞兆不建议超出额定或依照绝对最大额定值进行设计。
符号
VB
参数
最小值
VS+10
6-VDD
VS
最大值
VS+20
600
单位
V
高侧浮动电源电压
高侧浮动电源偏置电压
高侧输出电压
VS
V
VHO
VIN
VDD
TA
VB
V
GND
10
VDD
V
逻辑输入电压
20
V
电源电压
-40
+125
°C
工作环境温度
© 2009 飞兆半导体公司
www.fairchildsemi.com
FAN73711 • Rev. 1.0.1
4
电气特性
V 偏压 (VDD, VBS) = 15.0V 且 TA = 25°C，除非另有规定。VIN 和 IIN 参数以 GND 为参考点。VO 和 IO 参数是以 VS 为参
考，且适用于输出 HO。
符号
电源部分
IQDD
特性
测试条件
最小值 典型值 最大值 单位
静态 VDD 电源电流
工作 VDD 电源电流
VIN=0 V 或 5 V
fIN=20 kHz，无负载
25
35
70
μA
μA
IPDD
100
自举电源部分
V
V
V
BS 电源欠压正向阈值电压
BS 电源欠压负向阈值电压
BS 电源欠压锁定滞回电压回差
V
V
V
BS 扫描
BS 扫描
BS 扫描
VBSUV+
VBSUV-
VBSHYS
ILK
8.0
7.3
9.0
8.3
0.7
10.0
9.3
V
V
V
VB=VS=625 V
10
μA
μA
μA
偏置电源的漏电流
静态 VBS 电源电流
VIN=0V 或 5 V
IQBS
60
120
CLOAD=1000 pF，fIN=20 kHz，
均方跟值
工作 VBS 电源电流
IPBS
470
800
25
电压调节器部分
DD 和 VBS 电压调节器箝位电压
输入逻辑部分
VDD 扫描或 VBS 扫描
V
VSHUNT
21
23
V
ISHUNT=5 mA
VIH
VIL
IIN+
IIN-
RIN
2.5
V
V
逻辑 “1” 输入电压
逻辑 “0” 输入电压
逻辑输入高偏压电流
逻辑输入低偏压电流
输入下拉电阻
0.8
65
2
VIN=5 V
VIN=0 V
40
μA
μA
KΩ
90
110
栅极驱动器输出部分
高电平输出电压 (VBIAS - VO)
VOH
VOL
IO+
1.2
30
V
mV
A
无负载
低电平输出电压
输出高，短路脉冲电流 t(5)
输出低，短路脉冲电流 t(5)
无负载
VHO=0 V, VIN=5 V, PW ≤10 µs
3
3
4
4
VHO=15 V,VIN=0 V, PW ≤10 µs
IO-
A
IN 信号传播到 HO 时允许的 VS 引脚负电
压
VS
-9.8
-7.0
V
注意：
5.
这些参数由设计保证。
动态电气特性
VDD=VBS=15 V， GND=0 V， CLOAD=1000 pF， TA=25°C，除非另有规定。
符号
tON
tOFF
tr
参数
工作条件
最小值 典型值 最大值 单位
VS=0 V
VS=0 V
150
150
25
210
210
50
ns
ns
ns
ns
导通传播延时
关断传播延时
导通上升时间
关断下降时间
tf
15
40
© 2009 飞兆半导体公司
www.fairchildsemi.com
FAN73711 • Rev. 1.0.1
5
典型特征
200
180
160
140
120
100
200
180
160
140
120
100
-40
-40
-20
0
20
40
60
80
100
120
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
图 5. 导通传播延时
与温度的关系
图 6. 关断传播延时
与温度的关系
50
40
30
20
10
0
50
40
30
20
10
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
图 7. 导通上升时间
与温度的关系
图 8. 关断下降时间
与温度的关系
100
75
50
25
0
100
75
50
25
0
-40
-40
-20
0
20
40
60
80
100
120
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
图 9. 静态 VDD 电源电流
与温度的关系
图 10. 静态 VBS 电源电流
与温度的关系
© 2009 飞兆半导体公司
www.fairchildsemi.com
FAN73711 • Rev. 1.0.1
6
典型特性 （续）
100
80
60
40
20
0
800
600
400
200
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
图 11. 工作 VDD 电源电流
与温度的关系
图 12. 工作 VBS 电源电流
与温度的关系
10.0
9.5
9.0
8.5
8.0
7.5
7.0
9.5
9.0
8.5
8.0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
图 13. VBS UVLO+ 与温度的关系
图 14.VBS UVLO- 与温度的关系
1.2
0.9
0.6
0.3
0.0
30
25
20
15
10
5
0
-40
-40
-20
0
20
40
60
80
100
120
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
图 15. 高电平输出电压
与温度的关系
图 16. 低电平输出电压
与温度的关系
© 2009 飞兆半导体公司
FAN73711 • Rev. 1.0.1
www.fairchildsemi.com
7
典型特性 （续）
2.5
2.0
1.5
1.0
0.5
2.5
2.0
1.5
1.0
0.5
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
图 17. 逻辑高输入电压
与温度的关系
图 18. 逻辑低输入电压与温度的关系
-7
-8
60
50
40
30
20
10
0
-9
-10
-11
-12
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
图 19. 逻辑输入高偏压电流与温度的关系
图 20. 容许的负 VS 电压
与温度的关系
25
24
23
22
21
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
图 21. 电压调节器箝位电压
与温度的关系
© 2009 飞兆半导体公司
www.fairchildsemi.com
FAN73711 • Rev. 1.0.1
8
开关时间定义
时序图
15V
50%
50%
VDD
VB
IN
15V
10nF
10µF
10µF
0.1µF
VS
ton
tr
toff
tf
GND
IN
FAN73711
1000pF
90%
90%
HO
OUT
10%
10%
FAN73711 Rev.01
图 22. 开关时间测试电路和波形定义
© 2009 飞兆半导体公司
www.fairchildsemi.com
FAN73711 • Rev. 1.0.1
9
封装尺寸
5.00
4.80
A
0.65
3.81
8
5
B
1.75
6.20
5.80
4.00
3.80
5.60
1
4
PIN ONE
INDICATOR
1.27
1.27
(0.33)
M
0.25
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
0.25
0.10
0.25
0.19
C
1.75 MAX
0.10
C
0.51
0.33
OPTION A - BEVEL EDGE
0.50
x 45°
GAGE PLANE
0.25
R0.10
R0.10
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERWISE SPECIFIED
8°
0°
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13
SEATING PLANE
0.90
(1.04)
0.406
DETAIL A
SCALE: 2:1
图 23. 8- 引脚小尺寸封装 (SOP)
封装图纸作为一项服务，提供给考虑飞兆半导体元件的客户。具体参数可进行改动，且无需做出相应通知。请注意图纸上的版本和 / 或
日期，并联系飞兆半导体代表核实或获得最新版本。封装规格并不超出飞兆公司全球范围内的条款与条件，尤其指保修，保修涉及飞兆
半导体的全部产品。
请随时访问飞兆半导体的在线封装网页，以获得最新的封装图：
http://www.fairchildsemi.com/packaging/.
© 2009 飞兆半导体公司
www.fairchildsemi.com
FAN73711 • Rev. 1.0.1
10
© 2009 飞兆半导体公司
www.fairchildsemi.com
FAN73711 • Rev. 1.0.1
11
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