FAN7930BMX-G [ONSEMI]
功率因数控制器 (PFC)，CrCM，可编程 OVP;
| 型号： | FAN7930BMX-G |
| 厂家： | 
ONSEMI |
| 描述： | 功率因数控制器 (PFC)，CrCM，可编程 OVP 控制器 功率因数校正 |
| 文件： | 总22页 (文件大小：628K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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Critical Conduction Mode
PFC Controller
SOIC8
CASE 751EB
FAN7930B
Description
The FAN7930B is an active power factor correction (PFC)
controller for boost PFC applications that operate in critical
conduction mode (CRM). It uses a voltage−mode PWM that compares
an internal ramp signal with the error amplifier output to generate a
MOSFET turn−off signal. Because the voltage−mode CRM PFC
controller does not need rectified AC line voltage information, it saves
the power loss of an input voltage sensing network necessary for a
current−mode CRM PFC controller.
MARKING DIAGRAM
7930BG
ALYW
FAN7930B provides over−voltage protection (OVP),
open−feedback protection, over−current protection (OCP),
input−voltage−absent detection, and under−voltage lockout protection
(UVLO). The additional OVP pin can be used to shut down the boost
power stage when output voltage exceeds OVP level due to the
resistors that are connected at INV pin are damaged. The FAN7930B
can be disabled if the INV pin voltage is lower than 0.45 V and the
operating current decreases to a very low level. Using a new variable
on−time control method, total harmonic distortion (THD) is lower
than in conventional CRM boost PFC ICs.
7930BG = Device Code
A
= Assembly Site
L
YW
= Wafer Lot Number
= Assembly Start Week
ORDERING INFORMATION
See detailed ordering and shipping information on page 20 of
this data sheet.
Features
• Additional OVP Detection Pin
Related Resources
https://www.onsemi.com/pub/collateral/an−80
35.pdf
• VIN−Absent Detection
• Maximum Switching Frequency Limitation
• Internal Soft−Start and Startup without Overshoot
• Internal Total Harmonic Distortion (THD) Optimizer
• Precise Adjustable Output Over−Voltage Protection
• Open−Feedback Protection and Disable Function
• Zero Current Detector (ZCD)
• 150 ms Internal Startup Timer
• MOSFET Over−Current Protection (OCP)
• Under−Voltage Lockout with 3.5 V Hysteresis
• Low Startup and Operating Current
• Totem−Pole Output with High State Clamp
• +500/−800 mA Peak Gate Drive Current
• 8−Pin, Small−Outline Package (SOP)
• This is a Pb−Free Device
Applications
• Adapter
• Ballast
• LCD TV, CRT TV
• SMPS
© Semiconductor Components Industries, LLC, 2010
1
Publication Order Number:
February, 2022 − Rev. 3
FAN7930B/D
FAN7930B
APPLICATION DIAGRAM
DC OUTPUT
Vcc
+
FAN7930B
Line Filter
AC INPUT
7
4
1
2
8
5
Out
CS
VCC
+
ZCD
COMP
INV
OVP
3
GND
6
Figure 1. Typical Boost PFC Application
INTERNAL BLOCK DIAGRAM
VCC
H:open
VREF
VBIAS
2.5 VREF
8
VCC
VCC
−
V Z
Internal
Bias
reset
+
VTH(S/S)
8.5 12
5
ZCD
−
V
CC
+
Restart
Tmer
Gate
Driver
VTH(ZCD)
7
OUT
f MAX
Limit
VO(MAX)
THD
S
R
Q
Q
Optimized
Sawtooth
Generator
Control Range
Compensation
+
−
40 kW
Startup without
4
6
+
CS
Overshoot
8 pF
−
1
INV
−
VCS_LIM
VREF
VREF
Stair
Step
GND
+
Clamp
Circuit
reset
VIN Absent
3
2
COMP
disable
disable
Thermal
Shutdown
−
0.35 0.45
VREF
2.675
2.5
+
OVP
INV_open
OVP
V OVP,LH
disable
+
2.5 2.88
−
Figure 2. Functional Block Diagram
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2
FAN7930B
PIN CONFIGURATION
VCC
OUT
GND
ZCD
FAN7930BG
8−SOP
INV
OVP COMP
CS
Figure 3. Pin Configuration (Top View)
PIN DEFINITIONS
Pin No.
Name
Description
1
INV
This pin is the inverting input of the error amplifier. The output voltage of the boost PFC converter should be
resistively divided to 2.5 V.
2
3
OVP
This pin is used to detect PFC output over voltage when INV pin information is not correct.
COMP
This pin is the output of the transconductance error amplifier. Components for the output voltage compensation
should be connected between this pin and GND.
4
This pin is the input of the over−current protection comparator. The MOSFET current is sensed using a sensing
resistor and the resulting voltage is applied to this pin. An internal RC filter is included to filter sw itching noise.
CS
5
6
7
ZCD
This pin is the input of the zero−current detection (ZCD) block. If the voltage of this pin goes higher than 1.5 V,
then goes low er than 1.4 V, the MOSFET is turned on.
GND
This pin is used for the ground potential of all the pins. For proper operation, the signal ground and the power
ground should be separated.
This pin is the gate drive output. The peak sourcing and sinking current levels are +500 mA and −800 mA,
respectively. For proper operation, the stray inductance in the gate driving path must be minimized.
OUT
8
V
CC
This is the IC supply pin. IC current and MOSFET drive current are supplied using this pin.
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3
FAN7930B
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
−
Max
Unit
V
V
CC
Supply Voltage
V
Z
I
, I
Peak Drive Output Current
−800
−10
−10
−0.3
−10.0
−
+500
+10
+10
8.0
mA
mA
mA
V
OH OL
I
Driver Output Clamping Diodes VO > VCC or VO < −0.3 V
Detector Clamping Diodes
CLAMP
I
DET
V
IN
Error Amplifier Input, Output, OVP Input, ZCD Pins (Note 1)
CS Input Voltage (Note 2)
6.0
T
J
Operating Junction Temperature
+150
+125
+150
2.5
°C
°C
°C
kV
T
A
Operating Temperature Range
−40
−65
−
T
Storage Temperature Range
STG
ESD
Electrostatic Discharge Capability
Human Body Model, JESD22−A114
Charged Device Model, JESD22−C101
−
2.0
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. When this pin is supplied by external power sources by accident, its maximum allowable current is 50 mA.
2. In case of DC input, the acceptable input range is −0.3 V~6 V: within 100 ns −10 V~6 V is acceptable, but electrical specifications are not
guaranteed during such a short time.
THERMAL IMPEDANCE
Symbol
Parameter
Min
Max
Unit
Q
JA
Thermal Resistance, Junction−to−Ambient (Note 3)
150
−
°C/W
3. Regarding the test environment and PCB type, please refer to JESD51−2 and JESD51−10.
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Symbol
SECTION
Parameter
Conditions
Min
Typ
Max
Unit
V
CC
V
Start Threshold Voltage
V
V
Increasing
11
7.5
3.0
20
12
8.5
3.5
22
−
13
9.5
4.0
24
V
V
V
V
V
START
CC
V
Stop Threshold Voltage
UVLO Hysteresis
Decreasing
STOP
CC
HY
UVLO
V
Z
Zener Voltage
I
= 20 mA
CC
V
OP
Recommended Operating Range
13
20
SUPPLY CURRENT SECTION
I
Startup Supply Current
V
= V − 0.2 V
START
−
−
120
1.5
190
3.0
mA
mA
mA
mA
START
CC
I
Operating Supply Current
Dynamic Operating Supply Current
Operating Current at Disable
Output Not Switching
50 kHz, C = 1 nF
OP
I
−
2.5
4.0
DOP
OPDIS
I
I
V
INV
= 0 V
90
160
230
ERROR AM PLIFIER SECTION
V
Voltage Feedback Input Threshold1
Line Regulation
T = 25°C
2.465
−
2.500
0.1
20
2.535
10.0
−
V
mV
mV
mA
REF1
A
V
CC
= 14 V~20 V
DVREF1
DVREF2
Temperature Stability of V
Input Bias Current
(Note 4)
−
REF1
I
V
INV
V
INV
V
INV
V
INV
= 1 V~4 V
−0.5
−
−
0.5
−
EA,BS
I
Output Source Current
Output Sink Current
= V
= V
− 0.1 V
−12
12
mA
EAS,SR
REF
REF
I
+ 0.1 V
−
−
mA
EAS,SK
V
Output Upper Clamp Voltage
Zero Duty Cycle Output Voltage
Transconductance (Note 4)
= 1 V, V = 0 V
6.0
0.9
90
6.5
1.0
115
7.0
1.1
140
V
EAH
CS
V
V
EAZ
g
m
mmho
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4
FAN7930B
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted) (continued)
J
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
MAXIMUM ON−TIME SECTION
t
t
Maximum On−Time Programming 1
Maximum On−Time Programming 2
T = 25°C, V = 1 V
ZCD
35.5
11.2
41.5
13.0
47.5
14.8
ms
ms
ON,MAX1
A
T = 25°C, I
= 0.469 mA
ON,MAX2
A
ZCD
CURRENT−SENSE SECTION
V
Current Sense Input Threshold Voltage Limit
Input Bias Current
0.7
−1.0
−
0.8
−0.1
350
0.9
1.0
V
CS
I
V
= 0~1 V
mA
ns
CS,BS
CS
t
Current Sense Delay to Output (Note 4)
dV/dt = 1 V/100 ns, from 0 V to 5 V
500
CS,D
ZERO−CURRENT DETECT SECTION
V
Input Voltage Threshold (Note 4)
Detect Hysteresis (Note 4)
Input High Clamp Voltage
Input Low Clamp Voltage
1.35
0.05
5.5
0
1.50
0.10
6.2
0.65
−0.1
−
1.65
0.15
7.5
V
V
ZCD
HY
ZCD
CLAMPH
V
I
I
= 3 mA
V
DET
V
= −3 mA
1.00
1.0
V
CLAMPL
ZCD,BS
ZCD,SR
DET
I
Input Bias Current
V
= 1 V~5 V
−1.0
−
mA
mA
mA
ns
ZCD
I
Source Current Capability (Note 4)
Sink Current Capability (Note 4)
T = 25°C
−4
A
I
T = 25°C
−
−
10
ZCD,SK
A
t
Maximum Delay From ZCD to Output
Turn−On (Note 4)
dV/dt = −1 V/100 ns, from 5 V to 0 V
100
−
200
ZCD,D
OUTPUT SECTION
V
Output Voltage High
I
I
= −100 mA, T = 25°C
9.2
−
11.0
1.0
50
12.8
2.5
V
V
OH
O
A
V
Output Voltage Low
= 200 mA, T = 25°C
A
OL
O
t
Rising Time (Note 4)
C
= 1 nF
= 1 nF
−
100
100
14.5
1
ns
ns
V
RISE
FALL
IN
t
Falling Time (Note 4)
C
−
50
IN
V
Maximum Output Voltage
Output Voltage with UVLO Activated
V
V
= 20 V, I = 100 mA
11.5
−
13.0
−
O,MAX
CC
CC
O
V
= 5 V, I = 100 mA
V
O,UVLO
O
RESTART / MAXIMUM SWITCHING FREQUENCY LIMIT SECTION
t
Restart Timer Delay
50
150
300
300
350
ms
RST
MAX
f
Maximum Sw itching Frequency (Note 4)
250
kHz
SOFT−START TIMER SECTION
Internal Soft−Soft (Note 4)
PROTECTIONS
t
SS
3
5
7
ms
V
OVP Threshold Voltage at INV Pin
OVP Hysteresis at INV Pin
T = 25°C
2.620
0.120
2.740
−
2.675
0.175
2.845
0.345
0.45
0.10
140
2.730
0.230
2.960
−
V
V
OVP,INV
A
HY
T = 25°C
A
OVP,INV
V
OVP Threshold Voltage at OVP Pin
OVP Hysteresis at OVP Pin
T = 25°C
A
V
OVP,OVP
HY
T = 25°C
A
V
OVP,OVP
V
EN
Enable Threshold Voltage
0.40
0.05
125
−
0.50
0.15
155
−
V
HY
Enable Hysteresis
V
EN
T
SD
Thermal Shutdown Temperature (Note 4)
Hysteresis Temperature of TSD (Note 4)
°C
°C
T
HYS
60
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. These parameters, although guaranteed by design, are not production tested.
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5
FAN7930B
COMPARISON OF FAN7530 AND FAN7930B
Function
FAN7530
FAN7930B
FAN7930B Advantages
OVP Pin
None
Integrated
•
•
No External Circuit for additional OVP
Reduction of Power Loss and BOM Cost Caused by Additional
OVP Circuit
Frequency Limit
None
None
None
None
Integrated
Integrated
Integrated
Integrated
Internal
•
•
Abnormal CCM Operation Prohibited
Abnormal Inductor Current Accumulation Can Be Prohibited
VIN−Absent Detection
•
•
Increase System Reliability by Testing for Input Supply Voltage
Guarantee Stable Operation at Short Electric Power Failure
Soft−Start and Startup
without Overshoot
•
•
Reduce Voltage and Current Stress at Startup
Eliminate Audible Noise Due to Unwanted OVP Triggering
Control Range
Compensation
•
•
Can Avoid Burst Operation at Light Load and High Input Voltage
Reduce Probability of Audible Noise Due to Burst Operation
THD Optimizer
TSD
External
None
•
No External Resistor is Needed
140°C with 60°C
•
•
Stable and Reliable TSD Operation
Converter Temperature Range Limited Range
Hysteresis
COMPARISON OF FAN7930C AND FAN7930B
Function
RDY Pin
OVP Pin
FAN7930C
Integrated
None
FAN7930B
Integrated
None
Remark
•
User Choice for the Use of Number #2 Pin
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6
FAN7930B
TYPICAL PERFORMANCE CHARACTERISTICS
)
Figure 4. Voltage Feedback Input Threshold 1 (V
Figure 5. Start Threshold Voltage (VSTART) vs. TA
REF1
vs. TA
Figure 6. Stop Threshold Voltage (VSTOP) vs. TA
Figure 7. Startup Supply Current (ISTART) vs. TA
Figure 8. Operating Supply Current (IOP) vs. TA
Figure 9. Output Upper Clamp Voltage (VEAH) vs. TA
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FAN7930B
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Figure 10. Zero Duty Cycle Output Voltage (VEAZ
vs. TA
)
Figure 11. Maximum On−Time Program 1 (tON,MAX1)
vs. TA
Figure 12. Maximum On−Time Program 2 (tON,MAX2
)
Figure 13. Current Sense Input Threshold Voltage
Limit (VCS) vs. TA
vs. TA
Figure 14. Input High Clamp Voltage (VCLAMPH) vs. TA
Figure 15. Input Low Clamp Voltage (VCLAMPL) vs. TA
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FAN7930B
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Figure 16. Output Voltage High (VOH) vs. TA
Figure 17. Output Voltage Low (VOL) vs. TA
Figure 18. Restart Timer Delay (tRST) vs. TA
Figure 19. OVP Threshold at OVP Pin (VOVP,OVP
vs. TA
)
Figure 20. Output Saturation Voltage (VRDY,SAT) vs. TA
Figure 21. OVP Threshold Voltage (VOVP) vs. TA
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FAN7930B
APPLICATIONS INFORMATION
PFC
VOUT
Startup
−
2.885 V
nd
Normally, supply voltage (V ) of a PFC block is fed
from the additional power supply, which can be called
standby power. Without this standby power, auxiliary
winding for zero current detection can be used as a supply
source. Once the supply voltage of the PFC block exceeds
12 V, internal operation is enabled until the voltage drops to
2
OVP
CC
high
+
disable
OVP
2.885
2
1
−
2.675 V/2.5 V
OVP
2.5 2.675
0.35 0.45
disable
+
−
INV Open
+
+
0.45 V/0.25 V
2.5 V
8. 5 V. If VCC exceeds V , 20 mA current is sinking from
Z
INV
V
CC
.
−
3
PFC Inductor
Aux. Winding
COMP
PFC
PFC
VIN
VOUT
Figure 23. Circuit Around INV Pin
External V circuit when no
CC
standby power exists.
PFC
390 VDC
V
OUT
413 V
390 V
70 V
VCC
55 V
H:open
VCC
’
2.5 V REF
8
VREF
VBIAS
V
−
INV
2.50 V
VZ
internal
bias
2.65 V
reset
2.50 V
+
2.24 V
1.64 V
VTH(S/S)
20 mA
0.45 V
0.35 V
8.5 12
V
CC
15 V
Figure 22. Startup Circuit
2.0 V
COMP
I
OUT
INV Block
Scaled−down voltage from the output is the input for the
INV pin. Many functions are embedded based on the INV
pin: transconductance amplifier, output OVP comparator,
and disable comparator.
Current Sourcing
Current Sourcing
Disable
OVP
/ sinking
V
< 2 V, internal logic is not alive.
CC
For the output voltage control, a transconductance
amplifier is used instead of the conventional voltage
amplifier. The transconductance amplifier (voltage−
controlled current source) aids the implementation of the
OVP and disable functions. The output current of the
amplifier changes according to the voltage difference of the
inverting and non−inverting input of the amplifier. To
cancel down the line input voltage effect on power factor
correction, the effective control response of the PFC block
should be slower than the line frequency and this conflicts
with the transient response of the controller. Two−pole
one−zero type compensation can meet both requirements.
The OVP comparator shuts down the output drive block
when the voltage of the INV pin is higher than 2.675 V and
there is 0.175 V hysteresis. The disable comparator disables
operation when the voltage of the inverting input is lower
than 0.35 V and there is 100 mV hysteresis. An external
small−signal MOSFET can be used to disable the IC, as
shown in Figure 23. The IC operating current decreases to
reduce power consumption if the IC is disabled. Figure 24
is the timing chart of the internal circuit near the INV pin
when rated PFC output voltage is 390 V and V supply
− Internal signals are unknown.
t
Figure 24. Timing Chart for INV Block
OVP Pin
Over−Voltage Protection (OVP) is embedded by the
information at the INV pin. That information comes from the
output through the voltage dividing resistors. To scale down
from a high voltage to a low one, high resistance is normally
used with low resistance. If the resistor of high resistance gets
damaged and resistance is changed to high, though INV pin
information is normal, output voltage exceeds its rated
output. If this occurs, the output electrolytic capacitor may be
damaged. To prevent such a catastrophe additional OVP pin
is assigned to double−check output voltage. Additional OVP
may be called “second” OVP, while INV pin OVP is called
“first” OVP. Since the two OVP conditions are quite different,
the protection recovering mode is different.
Since the two OVP conditions are quite different,
protection recovering mode is different. Once the first OVP
triggers, switching stops immediately and recovers switching
when the output voltage is decreased with a hysteresis. When
the second OVP triggers, switching can be recovered only
DC
CC
voltage is 15 V.
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10
FAN7930B
when the V supply voltage falls below V
and builds
where V
is the auxiliary winding voltage; T
and
CC
STOP
AUX
IND
up higher than V
again and V
should be lower than
T
AUX
are boost inductor turns and auxiliary winding turns,
START
OVP
hysteresis. If the second OVP is not used, the OVP pin must
be connected to the INV pin or to the ground.
respectively; V is input voltage for PFC converter; and
AC
V
is output voltage from the PFC converter.
OUT_PFC
VCC
PFC Inductor
PFC
PFC
VIN
VOUT
VSTART
Aux. Winding
VSTOP
VCC
RZCD
Error on INV
Resistors
Happens
VINV
INV OVP
Level
Negative Clamp
Circuit
hysteresis
ZCD
5
−
+
CZCD
Restart
Timer
VTH(ZCD)
Though Output−
Voltage Reduced,
no Switching.
VOVP
OVP Level
OVP Level
Positive Clamp
Circuit
Gate
Driver
fMAX
Limit
Optional
S
Q
Q
THD
Optimized
Sawtooth
Generator
R
Switching stop
If error
IMOSFET
Switching stop
only during
OVP
until VCC drops
below VSTOP and
recovers to
still exist,
OVP
Figure 26. Circuit Near ZCD
triggers
again
VSTART
Because auxiliary winding voltage can swing from
negative to positive voltage, the internal block in ZCD pin
has both positive and negative voltage clamping circuits.
When the auxiliary voltage is negative, an internal circuit
clamps the negative voltage at the ZCD pin around 0.65 V
by sourcing current to the serial resistor between the ZCD
pin and the auxiliary winding. When the auxiliary voltage is
higher than 6.5 V, current is sinked through a resistor from
the auxiliary winding to the ZCD pin.
t
Figure 25. Comparison of First and Second OVP
Recovery Modes
Control Range Compensation
On time is controlled by the output voltage compensator
with FA N7930B. Due to this when input voltage is high and
load is light, control range becomes narrow compared to
when input voltage is low. That control range decrease is
inversely proportional to the double square of the input
1
ISW
IDIODE
VACIN
IMOSFET
voltage (controlꢀrangeꢀa
). Thus at high line,
inputꢀvoltage2
unwanted burst operation easily happens at light load and
audible noise may be generated from the boost inductor or
inductor at input filter. Different from the other converters,
burst operation in PFC block is not needed because the PFC
block itself is normally disabled during standby mode. To
reduce unwanted burst operation at light load, an internal
control range compensation function is implemented and
shows no burst operation until 5% load at high line.
VAUX & VZCD
VAUX
VZCD
6.2 V
0.65 V
t
Figure 27. Auxiliary Voltage Depends on MOSFET
Switching
Zero−Current Detection
Zero−current detection (ZCD) generates the turn−on
signal of the MOSFET when the boost inductor current
reaches zero using an auxiliary winding coupled with the
inductor. When the power switch turns on, negative voltage
is induced at the auxiliary winding due to the opposite
winding direction (see Equation 1). Positive voltage is
induced (see Equation 2) when the power switch turns off:
The auxiliary winding voltage is used to check the boost
inductor current zero instance. When boost inductor current
becomes zero, there is a resonance between boost inductor
and all capacitors at the MOSFET drain pin, including C
OSS
of the MOSFET; an external capacitor at the D−S pin to
reduce the voltage rising and falling slope of the MOSFET;
a parasitic capacitor at inductor; and so on to improve
performance. Resonated voltage is reflected to the auxiliary
winding and can be used for detecting zero current of boost
inductor and valley position of MOSFET voltage stress. For
valley detection, a minor delay by the resistor and capacitor
is needed. A capacitor increases the noise immunity at the
TAUX
VAUX + *
VAUX + *
@ VAC
(eq. 1)
(eq. 2)
TIND
TAUX
TIND
@ (VPFCOUT * VAC
)
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11
FAN7930B
ZCD pin. If ZCD voltage is higher than 1.5 V, an internal
next switch on; inductor current builds up at every switching
cycle and can be raised to very high current that exceeds the
current rating of the power switch or diode. This can
seriously damage the power switch. To avoid this, maximum
switching frequency limitation is embedded. If ZCD signal
is applied again within 3.3 ms after the previous rising edge
of gate signal, this signal is ignored internally and
FAN7930B waits for another ZCD signal.
ZCD comparator output becomes HIGH and LOW when the
ZCD goes below 1.4 V. At the falling edge of comparator
output, internal logic turns on the MOSFET.
V
DS
PFC
PFC
V
V
− V
− V
OUT
IN
OUT
IN
V
IN
ZCDafter COMPARATOR
Ignores ZCD Noise
I
INDUCTOR
MOSFET Gate
Max fSW Limit
Error Occurs!
I
I
DIODE
MOSFET
V
ZCD
t
Inhibit Region
1.5 V
1.4 V
Figure 30. Maximum Switching Frequency Limit
Operation
MOSFET gate
ON
150 ns Delay
Control
ON
The scaled output is compared with the internal reference
voltage and sinking or sourcing current is generated from
the COMP pin by the transconductance amplifier. The error
amplifier output is compared with the internal sawtooth
waveform to give proper turn−on time based on the
controller.
t
Figure 28. Auxiliary Voltage Threshold
When no ZCD signal is available, the PFC controller
cannot turn on the MOSFET, so the controller checks every
switching off time and forces MOSFET turn on when the off
time is longer than 150 ms. This restart timer triggers
MOSFET turn−on at startup and may be used at the input
voltage zero cross period.
PFC
VOUT
6.2 V
THD optimized
Sawtooth
Generator
1 V
+
MOSFET Off
Sawtooth
VOUT
−
V
IN
INV
−
1
3
VREF
Stair
Step
+
VCC
Clamp
Circuit
COMP
tRESTART
R1
C1
150ms
C2
MOSFET
ZCD after COMPARATOR
Figure 31. Control Circuit
t
Unlike a conventional voltage−mode PWM controller,
FAN7930B turns on the MOSFET at the falling edge of ZCD
signal. The “ON” instant is determined by the external signal
and the turn−on time lasts until the error amplifier output
Figure 29. Restart Timer at Startup
Because the MOSFET turn−on depends on the ZCD input,
switching frequency may increase to higher than several
megahertz due to the mis−triggering or noise on the nearby
ZCD pin. If the switching frequency is higher than needed
for critical conduction mode (CRM), operation mode shifts
to continuous conduction mode (CCM). In CCM, unlike
CRM where the boost inductor current is reset to zero at the
(V
) and sawtooth waveform meet. When load is heavy,
COMP
output voltage decreases, scaled output decreases, COMP
voltage increases to compensate low output, turn−on time
lengthens to give more inductor turn−on time, and increased
inductor current raises the output voltage. This is how a PFC
negative feedback controller regulates output.
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12
FAN7930B
ICOMP
The maximum of V
is limited to 6.5 V, which
COMP
dictates the maximum turn−on time. Switching stops when
is lower than 1.0 V.
Powering
V
COMP
250 mmho
ZCD after COMPARATOR
VCOMP & Sawtooth
115 mmho
0.155 V / ms
MOSFET Gate
Braking
t
Figure 34. Gain Characteristic
Figure 32. Turn−On Time Determination
Soft−Start
The roles of PFC controller are regulating output voltage
When V reaches V
, the internal reference voltage
CC
START
and input current shaping to increase power factor. Duty
control based on the output voltage should be fast enough to
compensate output voltage dip or overshoot. For the power
factor, however, the control loop must not react to the
fluctuating AC input voltage. These two requirements
conflict; therefore, when designing a feedback loop, the
feedback loop should be least ten times slower than AC line
frequency. That slow response is made by C1 at the
compensator. R1 makes gain boost around operation region
and C2 attenuates gain at higher frequency. Boost gain by R1
helps raise the response time and improves phase margin.
is increased like a stair step for 5 ms. As a result, V
is
COMP
also raised gradually and MOSFET turn−on time increases
smoothly. This reduces voltage and current stress on the
power switch during startup.
V
CC
VSTART = 12 V
SS
VREFEND = 2.5 V
V
REF
5 ms
Gain
Integrator
C1
VINV = 0.4 V
gM
Proportional
Gain
R1
Freq.
COMP
SS
COMP
ISOURCE
(VREF − VINV) x gM = ISOURCE
C2
High−Frequency
Noise Filter
Figure 33. Compensators Gain Curve
ISOURCECOMP x RCOMP = VCOMP
V
COMP
For the transconductance error amplifier side, gain
changes based on differential input. When the error is large,
gain is large to suppress the output dip or peak quickly.
When the error is small, low gain is used to improve power
factor performance.
t
Figure 35. Soft−Start Sequence
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13
FAN7930B
IIN
Startup without Overshoot
Feedback control speed of PFC is quite slow. Due to the
slow response, there is a gap between output voltage and
feedback control. That is why over−voltage protection
(OVP) is critical at the PFC controller and voltage dip caused
by fast load changes from light to heavy is diminished by a
bulk capacitor. OVP can be triggered during startup phase.
Operation on and off by OVP at startup may cause audible
noise and can increase voltage stress at startup, which is
normally higher than in normal operation. This operation is
improved when soft−start time is very long. However, too
much startup time enlarges the output voltage building time
at light load. FAN7930B has overshoot protection at startup.
During startup, the feedback loop is controlled by an internal
proportional gain controller and when the output voltage
reaches the rated value, it switches to an external
compensator after a transition time of 30 ms. This internal
proportional gain controller eliminates overshoot at startup
and an external conventional compensator takes over
successfully afterward.
IINDUCTOR
IDIODE
IMOSFET
VZCD
INEGATIVE
1.5 V
1.4 V
150 ns
MOSFET Gate
ON
ON
t
Figure 37. Input and Output Current Near Input
Voltage Peak
VOUT
IIN
Startup
Overshoot
Conventional Controller
Overshoot−less Startup Control
IINDUCTOR
Control Transition
V
ZCD
INEGATIVE
VCOMP
Depend on Load
1.5 V
1.4 V
Internal Controller
150 ns
MOSFET Gate
t
Figure 36. Startup without Overshoot
ON
ON
ON
ON
THD Optimization
t
Total harmonic distortion (THD) is the factor that dictates
how closely input current shape matches sinusoidal form.
The turn−on time of the PFC controller is almost constant
over one AC line period due to the extremely low feedback
control response. The turn−off time is deter mined by the
current decrease slope of the boost inductor made by the
input voltage and output voltage. Once inductor current
Figure 38. Input and Output Current Near Input
Voltage Peak Zero Cross
To improve this, lengthened turn−on time near the zero
cross region is a well−known technique, though the method
may vary and may be proprietary. FA N7930B optimizes this
by sourcing current through the ZCD pin. Auxiliary winding
voltage becomes negative when the MOSFET turns on and
is proportional to input voltage. The negative clamping
circuit of ZCD outputs the current to maintain the ZCD
voltage at a fixed value. The sourcing current from the ZCD
is directly proportional to the input voltage. Some portion of
this current is applied to the internal sawtooth generator
together with a fixed−current source. Theoretically the
fixed−current source and the capacitor at sawtooth generator
determine the maximum turn−on time when no current is
sourcing at ZCD clamp circuit and available turn−on time
gets shorter proportional to the ZCD sourcing current.
becomes zero, resonance between C
and the boost
OSS
inductor makes oscillating waveforms at the drain pin and
auxiliary winding. By checking the auxiliary winding
voltage through the ZCD pin, the controller can check the
zero current of boost inductor. At the same time, a minor
delay is inserted to determine the valley position of drain
voltage. The input and output voltage difference is at its
maximum at the zero cross point of AC input voltage. The
current decrease slope is steep near the zero cross region and
more negative inductor current flows during a drain voltage
valley detection time. Such a negative inductor current
cancels down the positive current flows and input current
becomes zero, called “zero−cross distortion” in PFC.
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14
FAN7930B
FAN7930B checks if the input AC voltage exists. If input
does not exist, soft−start is reset and waits until AC input is
live again. Soft−start manages the turn−on time for smooth
operation when it detects AC input is applied again and
applies less voltage and current stress on startup.
VAUX
RZCD
VCC
THD Optimizer
VOUT
VIN
N
1
ZCD
Though VIN is eliminated,
operation of controller is
normal due to the large
bypass capacitor.
5
Zero Current
Detect
VAUX
VREF
IMOT
CMOT
Sawtooth Generator
reset
DMAX
MOSFET Gate
VCOMP
fMIN
Figure 39. Circuit of THD Optimizer
tON is typically constant over 1 AC line frequency
but tON
V
ZCD
tON
IDS
High Drain
Current!
t
t
Figure 41. Without VIN−Absent Circuit
tON not shortter
tON get shortter
VOUT
VIN
VZCD at FET on
Figure 40. Effect of THD Optimizer
Though VIN is eliminated,
operation of controller is
normal due to the large
bypass capacitor.
By THD optimizer, turn−on time over one AC line period
is proportionally changed, depending on input voltage. Near
zero cross, lengthened turn−on time improves THD
performance.
VAUX
VIN−Absent Detection
To reduce power loss caused by input voltage sensing
resistors and to optimize THD, the FAN7930B omits AC
input voltage detection. Therefore, no information about AC
input is available from the internal controller. In many cases,
DMAX
fMIN
DMIN
MOSFET Gate
New VCOMP
fMIN
the V of PFC controller is supplied by an independent
CC
power source like standby power. In this scheme, some
mismatch may exist. For example, when the electric power
is suddenly interrupted during two or three AC line periods;
Input Voltage Absent Detected
V
is still live during that time, but output voltage drops
CC
because there is no input power source. Consequently, the
control loop tries to compensate for the output voltage drop
IDS
Smooth Soft−Start
and V
reaches its maximum. This lasts until AC input
COMP
voltage is live again. When AC input voltage is live again,
high V allows high switching current and more stress
is put on the MOSFET and diode. To protect against this,
t
COMP
Figure 42. With VIN−Absent Circuit
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15
FAN7930B
Current Sense
Gate Driver Output
The MOSFET current is sensed using an external sensing
resistor for over−current protection. If the CS pin voltage is
higher than 0.8 V, the over−current protection comparator
generates a protection signal. An internal RC filter of 40 kW
and 8 pF is included to filter switching noise.
FAN7930B contains a single totem−pole output stage
designed for a direct drive of the power MOSFET. The drive
output is capable of up to +500 / −800 mA peak current with
a typical rise and fall time of 50 ns with 1 nF load. The output
voltage is clamped to 13 V to protect the MOSFET gate even
if the V voltage is higher than 13 V.
CC
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16
FAN7930B
PCB LAYOUT GUIDE
PFC block normally handles high switching current and
components may be needed to reduce the noise level
applied to the CS pin.
the voltage low−energy signal path can be affected by the
high−energy path. Cautious PCB layout is mandatory for
stable operation.
• The gate drive path should be as short as possible. The
closed−loop that starts from the gate driver, MOSFET
gate, and MOSFET source to ground of PFC controller
should be as close as possible. This is also crossing point
between power ground and signal ground. Power ground
path from the bridge diode to the output bulk capacitor
should be short and wide. The sharing position between
power ground and signal ground should be only at one
position to avoid ground loop noise. Signal path of the
PFC controller should be short and wide for external
components to contact.
• The PFC output voltage sensing resistor is normally high
to reduce current consumption. This path can be affected
by external noise. To reduce noise potential at the INV
pin, a shorter path for output sensing is recommended. If
a shorter path is not possible, place some dividing
resistors between PFC output and the INV pin — closer to
the INV pin is better. Relative high voltage close to the
INV pin can be helpful.
• The ZCD path is recommended close to auxiliary winding
from boost inductor and to the ZCD pin. If that is difficult,
place a small capacitor (below 50 pF) to reduce noise.
Figure 43. Recommended PCB Layout
• The switching current sense path should not share with
another path to avoid interference. Some additional
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17
FAN7930B
TYPICAL APPLICATION CIRCUIT
TYPICAL APPLICATION CIRCUIT
Output Voltage
(Maximum Current)
Application
Device
FAN7930B
Input Voltage Range
90−265 V
Rated Output Power
195 W
LCD TV Power Supply
390 V (0.5 A)
AC
Features
• Because the input bias current of INV pin is almost zero,
output voltage sensing resistors (R112~R115) should be
as high as possible. However, too−high resistance makes
the node susceptible to noise. Resistor values need to
strike a balance between power consumption and noise
immunity.
• Quick charge diode (D106) can be eliminated if output
diode inrush current capability is sufficient. Even without
D106, system operation is normal due to the controller’s
highly reliable protection features.
• Average efficiency of 25%, 50%, 75%, and 100% load
conditions is higher than 95% at universal input.
• Power factor at rated load is higher than 0.98 at universal
input.
• Total Harmonic Distortion (THD) at rated load is lower
than 15% at universal input.
Key Design Notes
• When auxiliary VCC supply is not available, VCC power
can be supplied through Zero Current Detect (ZCD)
winding. The power consumption of R103 is quite high,
so its power rating needs checking.
Schematic
Optional
D106
600V 3A
D105
600V 8A
194mH, 39:5
DC OUTPUT
LP101,EER3019N
BD101,
600V,15A
VAUX
R103,
10k,1W
C104,
12nF
R109
47
Q101
FCPF
20N60
D102,
UF4004
FAN7930B
R108
4.7
D103,1N4148
8
7
4
1
VCC
Out
C102,
680nF
5
3
2
ZCD
Comp
OVP
CS
INV
GND
6
C114, C115,
2.2nF 2.2nF
C101,
220nF
R101,1M−J
ZNR101,
10D471
Circuit for VCC. If external VCC is used, this circuit is not needed.
Figure 44. Demonstration Circuit
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18
FAN7930B
Transformer
EER3019N
9, 10
1, 2
Naux 9, 10
1, 2
6, 7
Naux
NP
Np
3, 4
6, 7
3, 4
Figure 45. Transformer Schematic Diagram
Winding Specification
WINDING SPECIFICATION
Position
N
Pin (S " F)
3, 4 → 1, 2
Wire
Turns
Winding Method
o
Bottom
N
39
Solenoid Winding
0.1 φ x 50
p
Insulation: Polyester Tape t = 0.05 mm, 3 Layers
9, 10 → 6, 7
Top
N
5
Solenoid Winding
0.3 φ
AUX
Insulation: Polyester Tape t = 0.05 mm, 4 Layers
Electrical Characteristics
ELECTRICAL CHARACTERISTICS
Pin
3, 4 → 1, 2
Specification
Remark
Inductance
194 mH 5%
100 kHz, 1 V
Core & Bobbin
Core: EER3019, Samhwa (PL−7) (Ae = 137.0 mm )
2
Bobbin: EER3019
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19
FAN7930B
BILL OF MATERIALS
Part #
Value
Note
Part #
Value
Note
Resistor
Switch
®
R101
R102
R103
R104
1 MW
330 kW
10 kW
30 kW
1W
1/2W
1W
Q101
FCPF20N60
20 A, 600 V, SUPERFET
Diode
D101
D102
1N4746
UF4004
1 W, 18 V, Zener Diode
1/4W
1 A, 400 V Glass Passivated
High−Efficiency Rectifier
R107
R108
R109
10 kW
4.7 kW
47 kW
1/4W
1/4W
1/4W
D103
D104
D105
1N4148
1N4148
1 A, 100 V Small−Signal Diode
1 A, 100 V Small−Signal Diode
8 A, 600 V,
General−Purpose Rectifier
R110
10 kW
1/4W
D106
3 A, 600 V,
General−Purpose Rectifier
R111
0.80 kW
3.9 kW
5W
R112, R113,
R114, R116,
R117, R118
1/4W
IC101
FAN7930B
CRM PFC Controller
R115, R119
75 kW
1/4W
Capacitor
Fuse
NTC
C101
C102
220 nF / 275 VAC
680 nF / 275 VAC
0.68 mF / 630 V
12 nF / 50 V
Box Capacitor
Box Capacitor
FS101
TH101
BD101
LF101
T1
5 A / 250 V
C103
Box Capacitor
5D−15
C104
Ceramic Capacitor
SMD (1206)
Bridge Diode
C105
100 nF / 50 V
33 mF / 50 V
15 A, 600 V
C107
Electrolytic Capacitor
Ceramic Capacitor
Ceramic Capacitor
Ceramic Capacitor
Ceramic Capacitor
Electrolytic Capacitor
Box Capacitor
Line Filter
C108
220 nF / 50 V
47 nF / 50 V
23 mH
C109
Transformer
2
C110, C116
C112
1 nF / 50 V
EER3019
10D471
Ae = 137.0 mm
47 nF / 50 V
ZNR
C111
220 mF / 450 V
2.2 nF / 450 V
2.2 nF / 450 V
ZNR101
C114
C115
Box Capacitor
ORDERING INFORMATION
Operating
Temperature Range
†
Part Number
Top Mark
Package Type
Shipping
FAN7930BMX−G
−40 to + 125°C
FAN7930BG
8−Lead, Small−Outline Package (SOP)
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
SUPERFET is registered trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States
and/or other countries.
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20
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC8
CASE 751EB
ISSUE A
DATE 24 AUG 2017
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DOCUMENT NUMBER:
DESCRIPTION:
98AON13735G
SOIC8
PAGE 1 OF 1
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相关型号：
FAN7930C
The FAN7930C is an active power factor correction(PFC) controller for boost PFC applications that operate in critical conduction mode(CRM).
FAIRCHILD
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