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February 2013

FAN9612

Interleaved Dual BCM PFC Controllers

The FAN9612 interleaved dual Boundary-Conduction-

Mode (BCM) Power-Factor-Correction (PFC) controller

operates two parallel-connected boost power trains 180°

out of phase. Interleaving extends the maximum practical

power level of the control technique from about 300 W to

greater than 800 W. Unlike the continuous conduction

mode (CCM) technique often used at higher power

levels, BCM offers inherent zero-current switching of the

boost diodes, which permits the use of less expensive

diodes without sacrificing efficiency. Furthermore, the

input and output filters can be smaller due to ripple

current cancellation and effective doubling of the

switching frequency.

Features

.

Sync-Lock™ Interleaving Technology for 180°

Out-of-Phase Synchronization Under All Conditions

.

Automatic Phase Disable at Light Load

Dead-Phase Detect Protection

2.0 A Sink, 1.0 A Source, High-Current Gate Drivers

High Power Factor, Low Total Harmonic Distortion

Voltage-Mode Control with (V_IN)²Feedforward

Closed-Loop Soft-Start with User-Programmable

Soft-Start Time for Reduced Overshoot

.

Minimum Restart Frequency to Avoid Audible Noise

Maximum Switching Frequency Clamp

The converter operates with variable frequency, which is

a function of the load and the instantaneous input /

output voltages. The switching frequency is limited

between 16.5 kHz and 525 kHz. The Pulse Width

Modulators (PWM) implement voltage-mode control with

input voltage feedforward. When configured for PFC

applications, the slow voltage regulation loop results in

constant on-time operation within a line cycle. This PWM

method, combined with the BCM operation of the boost

converters, provides automatic power factor correction.

Brownout Protection with Soft Recovery

Non-Latching OVP on FB Pin and Latching Second-

Level Protection on OVP Pin

.

Open-Feedback Protection

Power-Limit and Current Protection for Each Phase

Low Startup Current of 80 µA Typical

Works with DC and 50 Hz to 400 Hz AC Inputs

The controller offers bias UVLO of 12.5 V / 7.5 V, input

brownout, over-current, open-feedback, output over-

voltage, and redundant latching over-voltage protections.

Furthermore, the converters’ output power is limited

independently of the input RMS voltage. Synchronization

between the power stages is maintained under all

operating conditions.

Applications

.

100-1000 W AC-DC Power Supplies

Large Screen LCD-TV, PDP-TV, RP-TV Power

High-Efficiency Desktop and Server Power Supplies

Networking and Telecom Power Supplies

Solar Micro Inverters

Description

Figure 1. Simplified Application Diagram

FAN9612 • Rev. 1.1.7

www.fairchildsemi.com

Ordering Information

Packing

Quantity

Part Number

Package

Packing Method

FAN9612MX

16-Lead, Small Outline Integrated Circuit (SOIC)

Tape and Reel

2,500

This device passed wave soldering test by JESD22A-111.

Package Outlines

Figure 2. SOIC-16 (Top View)

Thermal Resistance Table

Thermal Resistance

Package

Suffix

(1)

(2)

Θ_JL

Θ_JA

16-Lead SOIC

M

35°C/W

50 – 120°C/W⁽³⁾

Notes:

1. Typical Θ_JLis specified from semiconductor junction to lead.

2. Typical Θ_JAis dependent on the PCB design and operating conditions, such as air flow. The range of values

covers a variety of operating conditions utilizing natural convection with no heatsink on the package.

3. This typical range is an estimate; actual values depend on the application.

FAN9612 • Rev. 1.1.7

www.fairchildsemi.com

2

Typical Application Diagram

V

IN

L2a

D2

D1

V

OUT

V

LINE

L2b

L1a

R

ZCD2

ZCD1

R

IN1

C

IN

L1b

C

OUT

AC IN

R

FB1

FB2

EMI Filter

1

2

3

4

ZCD1

ZCD2

5VB

CS1 16

CS2 15

R

IN2

C

R

5VB

V_BIAS

14

13

VDD

Q1

MOT

AGND

SS

DRV1

R

MOT

INHYST

R_G1

R_G2

Q2

5

6

7

8

DRV2 12

C

SS

R

OV1

OV2

PGND 11

VIN 10

R

C

COMP

FB

C

COMP,LF

R_CS1

R_CS2

9

OVP

COMP,HF

C

VDD2

VDD1

C

INF

Figure 3. Typical Application Diagram

Block Diagram

Figure 4. Block Diagram

FAN9612 • Rev. 1.1.7

www.fairchildsemi.com

3

Pin Configuration

Figure 5. Pin Layout (Top-View)

Pin Definitions

Pin #

1

Name

ZCD1

ZCD2

5VB

Description

Zero Current Detector for Phase 1 of the interleaved boost power stage.

Zero Current Detector for Phase 2 of the interleaved boost power stage.

5V Bias. Bypass pin for the internal supply, which powers all control circuitry on the IC.

Maximum On-Time adjust for the individual power stages.

2

3

4

MOT

AGND

SS

5

Analog Ground. Reference potential for all setup signals.

6

Soft-Start Capacitor. Connected to the non-inverting input of the error amplifier.

Compensation Network connection to the output of the g_Merror amplifier

Feedback pin to sense the converter’s output voltage; inverting input of the error amplifier.

Output Voltage monitor for the independent, second-level, latched OVP protection.

Input Voltage monitor for brownout protection and input-voltage feedforward.

Power Ground connection.

7

COMP

FB

8

9

OVP

VIN

10

11

12

13

14

15

16

PGND

DRV2

DRV1

VDD

CS2

Gate Drive Output for Phase 2 of the interleaved boost power stage.

Gate Drive Output for Phase 1 of the interleaved boost power stage.

External Bias Supply for the IC.

Current Sense Input for Phase 2 of the interleaved boost power stage.

Current Sense Input for Phase 1 of the interleaved boost power stage.

CS1

FAN9612 • Rev. 1.1.7

www.fairchildsemi.com

4

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Symbol

V_DD

Parameter

Min.

-0.3

Max.

20.0

Unit

V

Supply Voltage to AGND & PGND

V_BIAS

5VB Voltage to AGND & PGND

5.5

V

Voltage On Input Pins to AGND (Except FB Pin)

Voltage On FB Pin (Current Limited)

V_BIAS+ 0.3

V_DD+ 0.8

V_DD+ 0.3

2.5

V

Voltage On Output Pins to PGND (DRV1, DRV2)

V

I_OH,I_OLGate Drive Peak Output Current (Transient)

Gate Drive Output Current (DC)

A

0.05

A

T_L

T_J

Lead Soldering Temperature (10 Seconds)

Junction Temperature

+260

ºC

-40

-65

+150

T_STG

Storage Temperature

+150

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol

V_DD

Parameter

Min.

9

Typ.

Max.

18

Unit

V

Supply Voltage Range

Signal Input Voltage

12

V_INS

0

5

V

I_SNK

Output Current Sinking (DRV1, DRV2)

Output Current Sourcing (DRV1, DRV2)

1.5

0.8

2.0

1.0

A

I_SRC

A

L_MISMATCHBoost Inductor Mismatch⁽⁴⁾

±5%

±10%

+125

T_A

Operating Ambient Temperature

-40

ºC

Note:

4. While the recommended maximum inductor mismatch is ±10% for optimal current sharing and ripple-current

cancellation, there is no absolute maximum limit. If the mismatch is greater than ±10%, current sharing is

proportionately worse, requiring over-design of the power supply. However, the accurate 180° out-of-phase

synchronization is still maintained, providing current cancellation, although its effectiveness is reduced.

FAN9612 • Rev. 1.1.7

www.fairchildsemi.com

5

Electrical Characteristics

Unless otherwise noted, V_DD= 12 V, T_J= -40°C to +125°C. Currents are defined as positive into the device and

negative out of the device.

Symbol

Supply

Parameter

Conditions

Min.

Typ.

Max. Unit

I_STARTUPStartup Supply Current

I_DDOperating Current

I_{DD_DYM}Dynamic Operating Current⁽⁵⁾

V_DD= V_ON– 0.2 V

80

3.7

4

110

5.2

6

µA

mA

V

Output Not Switching

f_SW= 50 kHz; C_LOAD= 2 nF

V_ON

V_OFF

V_HYS

UVLO Start Threshold

UVLO Stop Threshold Voltage

UVLO Hysteresis

12.0

7.0

12.5

7.5

5.0

13.0

8.0

V_DDDecreasing

V

Bias Regulator (C_5VB= 0.1 µF)

T_A= 25°C; I_LOAD= 1 mA

5.0

V_5VB

5VB Output Voltage

V

Total Variation Over Line,

Load, and Temperature

4.8

5.0

5.2

I_{OUT_MAX}Maximum Output Current

mA

Error Amplifier

T_A= 25°C

2.95

2.91

3.00

3.05

V_EA

Voltage Reference

V

Total Variation Over Line,

Load, and Temperature

3.075

V_FB= 1 V to 3 V;

|V_SS– V_FB| ≤ 0.1V

I_BIAS

Input Bias Current

-0.2

0.2

µA

I_{OUT_SRC}Output Source Current

I_{OUT_SINK}Output Sink Current

V_SS= 3 V; V_FB= 2.9 V

V_SS= 3 V; V_FB= 3.1 V

-13.7

4

-8

8

-4

12

µA

V_OH

V_OL

g_M

Output High Voltage

Output Low Voltage

Transconductance

4.5

0.0

50

4.7

0.1

78

V5VB

0.2

V

I_SINK< 100 µA

V

115

µmho

PWM

V_RAMP,OFSTPWM Ramp Offset

t_ON,MINMinimum On-Time

Maximum On-Time

T_A= 25°C

V_FB> V_SS

120

195

270

0

mV

µs

V_MOT

Maximum On-Time Voltage

Maximum On-Time

1.16

3.4

1.25

5.0

1.30

6.6

V

R = 125 kΩ

R = 125 kΩ; V_VIN= 2.5 V;

t_ON,MAX

µs

V_COMP> 4.5 V; T_A= 25°C

Restart Timer (Each Channel)

f_SW,MIN

Minimum Switching Frequency

V_FB> V_{PWM_OFFSET}

12.5

400

16.5

525

20.0

630

kHz

Frequency Clamp (Each Channel)

f_SW,MAX

Maximum Switching Frequency⁽⁵⁾

Continued on the following page…

FAN9612 • Rev. 1.1.7

www.fairchildsemi.com

6

Electrical Characteristics (Continued)

Unless otherwise noted, V_DD= 12 V, T_J= -40°C to +125°C. Currents are defined as positive into the device and

negative out of the device.

Symbol

Parameter

Conditions

Min. Typ.

Max.

Unit

Current Sense

V_CS

I_CS

CS Input Threshold Voltage Limit

CS Input Current

0.19

-0.2

0.21

85

0.23

0.2

V

V_CSX= 0 V to 1 V

µA

ns

t_{CS_DELAY}CS to Output Delay

CS Stepped from 0 V to 5 V

100

Zero Current Detection

Input Voltage Threshold⁽⁵⁾

Input High Clamp Voltage

Input Low Clamp Voltage

V_ZCDis Falling

I_ZCD= 0.5 mA

I_ZCD= –0.5 mA

0

0.1

1.2

-0.3

1

V

-0.1

0.8

V_{ZCD_IN}

V_{ZCD_H}

V_{ZCD_L}

1.0

-0.5

-0.7

V

I_{ZCD_SRC}Source Current Capability⁽⁵⁾

I_{ZCD_SNK}Sink Current Capability⁽⁵⁾

t_{ZCD_DLY}Turn-On Delay⁽⁵⁾

Output

mA

ns

10

ZCDx to OUTx

180

I_SINK

I_SOURCE

t_RISE

OUTx Sink Current ⁽⁵⁾

OUTx Source Current ⁽⁵⁾

Rise Time

V_OUTx= V_DD/2; C_LOAD= 0.1 µF

C_LOAD= 1 nF, 10% to 90%

C_LOAD= 1 nF, 90% to 10%

V_DD= 5 V; I_OUT= 100 µA

2.0

1.0

10

5

A

25

20

1

ns

V

t_FALL

Fall Time

V_{O_UVLO}Output Voltage During UVLO

I_RVS

Reverse Current Withstand ⁽⁵⁾

Soft-Start (C_SS= 0.1 µF)

I_{SS_MAX}Maximum Soft-Start Current

I_{SS_MIN}

Minimum Soft-Start Current⁽⁵⁾

Input Brownout Protection

V_{IN_BO}Input Brownout Threshold

500

mA

-7

-5

-3

V_COMP< 3.0 V

V_COMP> 4.5 V

µA

-0.40

-0.25

-0.10

0.76

-0.2

1.4

0.925

2

1.10

0.2

V

V_VIN> 1.1 V

µA

I_VINSNK

V_INSink Current

V_VIN< 0.8 V

2.5

Input-Voltage Feedforward Range

V_{FF_UL}

V_INFeedforward Upper Limit ⁽⁵⁾

3.1

3.6

3.7

4.0

4.3

V

(5)

V_{FF_RATIO}V_{FF_UL}/ V_{IN_BO}

Phase Management

V

_COMPDecreasing, Transition

V_PH,DROPPhase Dropping Threshold

V_PH,ADDPhase Adding Threshold

0.66

0.86

0.73

0.93

0.80

1.00

V

from 2 to 1 Phase, T_A= 25°C

V_COMPIncreasing, Transition

from 1 to 2 Phase, T_A= 25°C

Over-Voltage Protection Using FB Pin – Cycle-by-Cycle (Input)

Non-Latching OVP Threshold

(+8% above V_{OUT_NOMINAL}

T_A= 25°C

DRV1=DRV2=0 V

V_OVPNL

3.15

3.36

3.25

0.24

3.35

3.65

V

)

V_{OVPNL_HYS}OVP Hysteresis

FB Decreasing

Over-Voltage Protection Using OVP Pin – Latching (Input)

V_OVPLCHLatching OVP Threshold (+15%) DRV1=DRV2=0 V

Note:

3.50

V

5. Not tested in production.

FAN9612 • Rev. 1.1.7

www.fairchildsemi.com

7

Theory of Operation

There are many fundamental differences in CCM and

BCM operations and the respective designs of the boost

converter.

1. Boundary Conduction Mode

The boost converter is the most popular topology for

power factor correction in AC-to-DC power supplies.

This popularity can be attributed to the continuous input

current waveform provided by the boost inductor and to

the fact that the boost converter’s input voltage range

includes 0 V. These fundamental properties make close

to unity power factor easier to achieve.

The FAN9612 utilizes the boundary conduction mode

control algorithm. The fundamental concept of this

operating mode is that the inductor current starts from

zero in each switching period, as shown in the lower

waveform in Figure 7. When the power transistor of the

boost converter is turned on for a fixed amount of time,

the peak inductor current is proportional to the input

voltage. Since the current waveform is triangular, the

average value in each switching period is also

proportional to the input voltage. In the case of a

sinusoidal input voltage waveform, the input current of

the converter follows the input voltage waveform with

very high accuracy and draws a sinusoidal input current

from the source. This behavior makes the boost

converter in BCM operation an ideal candidate for

power factor correction.

L

This mode of control of the boost converter results in a

variable switching frequency. The frequency depends

primarily on the selected output voltage, the

instantaneous value of the input voltage, the boost

inductor value, and the output power delivered to the

load. The operating frequency changes as the input

voltage follows the sinusoidal input voltage waveform.

The lowest frequency operation corresponds to the peak

of the sine waveform at the input of the boost converter.

Even larger frequency variation can be observed as the

output power of the converter changes, with maximum

output power resulting in the lowest operating

frequency. Theoretically, under zero-load condition, the

operating frequency of the boost converter would

approach infinity. In practice, there are natural limits to

the highest switching frequency. One such limiting factor

is the resonance between the boost inductor and the

parasitic capacitances of the MOSFET, the diode, and

the winding of the choke, in every switching cycle.

Figure 6. Basic PFC Boost Converter

The boost converter can operate in continuous

conduction mode (CCM) or in boundary conduction

mode (BCM). These two descriptive names refer to the

current flowing in the energy storage inductor of the

boost power stage.

Another important characteristic of the BCM boost

converter is the high ripple current of the boost inductor,

which goes from zero to a controlled peak value in every

switching period. Accordingly, the power switch is

stressed with high peak current. In addition, the high

ripple current must be filtered by an EMI filter to meet

high-frequency

noise

regulations

enforced

for

equipment connecting to the mains. The effects usually

limit the practical output power level of the converter.

Figure 7. CCM vs. BCM Control

As the names indicate, the current in Continuous

Conduction Mode (CCM) is continuous in the inductor;

while in Boundary Conduction Mode (BCM), the new

switching period is initiated when the inductor current

returns to zero.

FAN9612 • Rev. 1.1.7

www.fairchildsemi.com

8

a sine square function. Eliminating the line frequency

component from the feedback system is imperative to

maintain low total harmonic distortion (THD) in the input

current waveform.

2. Interleaving

The FAN9612 control IC is configured to control two

boost converters connected in parallel, both operated in

boundary conduction mode. In this arrangement, the

input and output voltages of the two parallel converters

are the same and each converter is designed to process

approximately half the total output power.

The pulse width modulator implements voltage mode

control. This control method compares an artificial ramp

to the output of the error amplifier to determine the

desired on-time of the converter’s power transistor to

achieve output voltage regulation.

Figure 9. PWM Operation

Figure 8. Interleaved PFC Boost Operation

In FAN9612, there are two PWM sections

corresponding to the two parallel power stages. For

proper interleaved operation, two independent 180-

degree out-of-phase ramps are needed; which

necessitates the two pulse width modulators. To ensure

that the two converters process the same amount of

power, the artificial ramps have the same slope and use

the same control signal generated by the error amplifier.

Parallel power processing is penalized by the increased

number of power components, but offers significant

benefits to keep current and thermal stresses under

control and to increase the power handling capability of

the otherwise limited BCM PFC control solution.

Furthermore, the switches of the two boost converters

can be operated 180 degrees out of phase from each

other. The control of parallel converters operating 180

degrees out of phase is called interleaving. Interleaving

provides considerable ripple current reduction at the

input and output terminals of the power supply, which

favorably affects the input EMI filter requirements and

reduces the high-frequency RMS current of the power

supply output capacitor.

4. Input-Voltage Feedforward

Basic voltage-mode control, as described in the

previous section, provides satisfactory regulation

performance

in most cases. One important

characteristic of the technique is that input voltage

variation to the converter requires a corrective action

from the error amplifier to maintain the output at the

desired voltage. When the error amplifier has adequate

bandwidth, as in most DC-DC applications, it is able to

maintain regulation within a tolerable output voltage

range during input voltage changes.

There is an obvious difficulty in interleaving two BCM

boost converters. Since the converter’s operating

frequency is influenced by component tolerances in the

power stage and in the controller, the two converters

operate at different frequencies. Therefore special

attention must be paid to ensure that the two converters

are locked to 180-degree out-of-phase operation.

Consequently, synchronization is a critical function of an

interleaved boundary conduction mode PFC controller.

It is implemented in the FAN9612 using proprietary and

dedicated circuitry called Sync-Lock™ interleaving

technology.

On the other hand, when voltage-mode control is used

in power factor corrector applications; the error amplifier

bandwidth, and its capability to quickly react to input

voltage changes, is severely limited. In these cases, the

input voltage variation can cause excessive overshoot

or droop at the converter output as the input voltage

goes up or down.

To overcome this shortcoming of the voltage-mode

PWM circuit in PFC applications, input-voltage

feedforward is often employed. It can be shown

mathematically that a PWM ramp proportional to the

square of the input voltage rejects the effect of input

voltage variations on the output voltage and eliminates

the need of any correction by the error amplifier.

3. Voltage Regulation, Voltage Mode Control

The power supply’s output voltage is regulated by a

negative feedback loop and a pulse width modulator.

The negative feedback is provided by an error amplifier

that compares the feedback signal at the inverting input

to a reference voltage connected to the non-inverting

input of the amplifier. Similar to other PFC applications,

the error amplifier is compensated with high DC gain for

accurate voltage regulation, but very low bandwidth to

suppress line frequency ripple present across the output

capacitor of the converter. The line frequency ripple is

the result of the constant output power of the converter

and the fact that the input power is the product of a

sinusoidal current and a sinusoidal voltage thus follows

FAN9612 • Rev. 1.1.7

www.fairchildsemi.com

9

mean that the converter stops operating. To overcome

these situations, a restart timer is employed to kick start

the controller and provide the first turn-on command, as

shown in Figure 12.

Figure 12. PWM Cycle Start

Figure 10. Input-Voltage Feedforward

6. Terminating the Conduction Interval

When the PWM ramp is made proportional to the input

voltage squared, the system offers other noteworthy

benefits. The first is the input voltage-independent small

signal gain of the closed loop power supply, which

makes compensation of the voltage regulation loop

much easier. The second side benefit is that the output

of the error amplifier becomes directly proportional to

the input power of the converter. This phenomenon is

Terminating the conduction period of the boost

transistor in boundary conduction mode controllers is

similar to any other pulse width modulator. During

normal operation, the PWM comparator turns off the

power transistor when the ramp waveform exceeds the

control voltage provided by the error amplifier. In the

FAN9612 and in similar voltage-mode PWMs, the ramp

is a linearly rising waveform at one input of the

comparator circuit.

very significant and it is re-visited in Section

describing light-load operation.

9

5. Starting a PWM Cycle

The principle of boundary conduction mode calls for a

pulse width modulator able to operate with variable

frequency and initiate a switching period whenever the

current in the boost inductor reaches zero. Therefore,

BCM controllers cannot utilize

a fixed frequency

oscillator circuit to control the operating frequency.

Instead, a zero current detector is used to sense the

inductor current and turn on the power switch once the

current in the boost inductor reaches zero. This process

is facilitated by an auxiliary winding on the boost

inductor. The voltage waveform of the auxiliary winding

can be used for indirect detection of the zero inductor

current condition of the boost inductor. Therefore it

should be connected to the zero current detect input, as

shown in Figure 11.

Figure 13. Conduction Interval Termination

In addition to the PWM comparator, the current limit

circuit and a timer circuit limiting the maximum on-time

of the boost transistor can also terminate the gate drive

pulse of the controller. These functions provide

protection for the power switch against excessive

current stress.

7. Protecting the Power Components

In general, power converters are designed with

adequate margin for reliable operation under all

operating conditions. However, it might be difficult to

predict dangerous conditions under transient or certain

fault situations. Therefore, the FAN9612 contains

dedicated protection circuits to monitor the individual

peak currents in the boost inductors and in the power

transistors. Furthermore, the boost output voltage is

sensed by two independent mechanisms to provide

over-voltage protection for the power transistors,

rectifier diodes, and the output energy storage capacitor

of the converter.

Figure 11. Simple Zero-Current Detection Method

The auxiliary winding can also be used to generate bias

for the PFC controller when an independent bias power

supply is not present in the system.

At startup condition and in the unlikely case of missing

zero current detection, the lack of an oscillator would

FAN9612 • Rev. 1.1.7

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10

8. Power Limit

The architecture and operating principle of FAN9612

also provides inherent input power limiting capability.

Figure 15. Automatic Phase-Control Operation

10. Brownout Protection with Soft Recovery

An additional protection function usually offered by PFC

ICs is input brownout protection to prevent the converter

from operating below a user-defined minimum input

voltage level. For this function to work, the input voltage

of the converter is monitored. When the voltage falls

below the brownout protection threshold, the converter

stops working. The output voltage of the boost converter

falls until the load stops drawing current from the output

capacitor or until the input voltage gets back to its

nominal range and operation resumes.

Figure 14. On-Time vs. V_{IN_RMS}

When the slope of the PWM ramp is made proportional

to the square of the input RMS voltage, the maximum

on-time of the boost power switch becomes inversely

proportional to the square of V_IN,RMS, as represented in

Figure 14. In boundary-conduction mode, the peak

current of the boost transistor is proportional to its on

time. Therefore, controlling the maximum pulse width of

the gate drive signal according to the curve shown is an

effective method to implement an input-voltage

independent power limit for the boost PFC.

As the output falls, the voltage at the feedback pin falls

proportionally, according to the feedback divider ratio.

To facilitate soft recovery after a brownout condition, the

soft-start capacitor – which is also the reference voltage

of the error amplifier – is pulled lower by the feedback

network. This effectively pre-conditions the error

amplifier to provide closed-loop, soft-start-like behavior

9. Light-Load Operation (Phase Management)

One of the parameters determining the operating

frequency of a boundary conduction mode converter is

the output power. As the load decreases, lower peak

currents are commanded by the pulse width modulator

to maintain the output voltage at the desired set point.

Lower peak current means shorter on-time for the power

transistor and shorter time interval to ramp the inductor

current back to zero at any given input voltage. As a

result, the operating frequency of the converter

increases under light load condition.

during the converter’s recovery from

a brownout

situation. Once the input voltage goes above the

brownout protection threshold, the converter resumes

normal operation. The output voltage rises back to the

nominal regulation level following the slowly rising

voltage across the soft-start capacitor.

11. Soft Starting the Converter

As the operating frequency and corresponding switching

losses increase, conduction losses diminish at the same

time. Therefore, the power losses of the converter are

dominated by switching losses at light load. This

phenomenon is especially evident in a BCM converter.

During startup, the boost converter peak charges its

output capacitor to the peak value of the input voltage

waveform. The final voltage level, where the output is

regulated during normal operation, is reached after the

converter starts switching. There are two fundamentally

different approaches used in PWM controllers to control

the startup characteristics of a switched-mode power

supply. Both methods use some kind of soft-start

mechanism to reduce the potential overshoot of the

converter’s output after the desired output voltage level

is reached.

To improve light-load efficiency, FAN9612 disables one

of the two interleaved boost converters automatically

when the output power falls below approximately 13% of

the maximum power limit level. By managing the

number of phases used at light load, the FAN9612 can

maintain high efficiency for a wider load range of the

power supply.

The first method is called open-loop soft-start and relies

on gradually increasing the current or power limit of the

converter during startup. In this case, the voltage error

amplifier is typically saturated, commanding maximum

current until the output voltage reaches its final value. At

that time, the voltage between the error amplifier inputs

changes polarity and the amplifier slowly comes out of

saturation. While the error amplifier recovers and before

it starts controlling the output voltage, the converter

operates with full power. Thus, output voltage overshoot

is unavoidable in converters utilizing the open-loop soft-

start scheme.

Normal interleaved operation of the two boost

converters resumes automatically once the output

power exceeds approximately 18% of the maximum

power limit level of the converter.

By adjusting maximum on-time (using R_MOT), the phase

management thresholds can be adjusted upward,

described in the “Adjusting the Phase-Management

Thresholds” section of this datasheet.

FAN9612 • Rev. 1.1.7

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11

This method is especially dangerous in power-factor-

corrector applications because the error amplifier’s

bandwidth is typically limited to a very low crossover

frequency. The slow response of the amplifier can

cause considerable overshoot at the output.

FAN9612 employs closed-loop soft-start where the

reference voltage of the error amplifier is slowly

increased to its final value. When the current and power

limits of the converter are properly taken into

consideration, the output voltage of the converter

follows the reference voltage. This ensures that the

error amplifier stays in regulation during soft start and

the output voltage overshoot can be eliminated.

Functional Description

used as an indication that the chip is running.

Potentially, this behavior can be utilized to control the

inrush current limiting circuit.

1. Detecting Zero Inductor Current

(ZCD1, ZCD2)

Each ZCD pin is internally clamped close to 0 V (GND).

Any capacitance on the pin is ineffective in providing

any delay in ZCD triggering. The internal sense circuit is

a true differentiator to catch the valley of the drain

waveforms. The resistor between the auxiliary winding

of the boost inductor and the ZCD pin is only used for

current limiting. The maximum source current during

zero current detection must be limited to 0.5 mA. If the

sourcing current is larger than 0.5 mA, the internal

detection circuit is saturated and the ZCD circuit can be

prematurely triggered before reaching the actual ZCD

valley threshold. Source and sink capability of the pin

are about 1 mA and 10 mA, respectively. The stronger

sinking current capability provides sufficient margin for

the higher sinking current required during the

conduction time of the rectifier diode.

Figure 17. 5 V Bias

External

Components

Internal

Circuits

To arm ZCD

detector

PWM

signal

3. Maximum On-Time Control (MOT)

Maximum on-time, MOT, (of the boost MOSFET) is set

by a resistor to analog ground (AGND). The FAN9612

implements input-voltage feedforward. The maximum

on-time is a function of the RMS input voltage. The

voltage on the MOT pin is 1.25 V during operation

(constant DC voltage). The maximum on-time of the

power MOSFETs can be approximated by:

.

0.3/0.0V

R

ZCD

ARM

(ready)

INHIBIT

1(2)

ZCD

ZCD Valley

To ZCD

winding

Detector

ZCD

signal

(true differentiator)

2.4

1

t_ON,MAX= R_MOT⋅120⋅10⁻¹²

⋅

Positive Negative

Clamp Clamp

(2)

V_I²_NSNS,PK

1.25

Figure 16. Zero-Current Detect Circuit

The R_ZCDresistor value can be approximated by:

where V_INSNS,PKis the peak of the AC input voltage as

measured at the VIN pin (must be divided down, see

the VIN pin description).

V_O

N _AUX

1

R_ZCD

=

⋅

(1)

0.5mA

2

N _BOOST

2. 5 V Bias Rail (5VB)

This is the bypass capacitor pin for the internal 5 V bias

rail powering the control circuitry. The recommended

capacitor value is 220 nF. At least a 100 nF, good-

quality, high-frequency, ceramic capacitor should be

placed in close proximity to the pin.

The 5 V rail is a switched rail. It is actively held LOW

when the FAN9612is in under-voltage lockout. Once the

UVLO turn-on threshold is exceeded at the VDD pin, the

5 V rail is turned on, providing a sharp edge that can be

Figure 18. Maximum On-Time Control (MOT)

FAN9612 • Rev. 1.1.7

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12

the output voltage can not be raised. Therefore the FB

voltage stays flat or even decays while the SS voltage

keeps rising. This is a problem if closed-loop soft-start

should be maintained. By clamping the SS voltage to

the FB pin, this problem can be mitigated.

4. Analog Ground (AGND) and Power Ground

(PGND)

Analog ground connection (AGND) is the GND for all

control logic biased from the 5 V rail. Internally, the

AGND and PGND pins are tied together by two anti-

parallel diodes to limit ground bounce difference due to

bond wire inductances during the switching actions of

the high-current gate drive circuits. It is recommended to

connect AGND and PGND pins together with a short,

low-impedance trace on the PCB (right under the IC).

Furthermore, during brownout condition, the output

voltage of the converter might fall, which is reflected at

the FB pin. When FB voltage goes 0.5 V below the

voltage on the SS pin, it starts discharging the soft-start

capacitor. The soft-start capacitor remains 0.5 V above

the FB voltage. When the brownout condition is over,

the converter returns to normal operation gracefully,

following the slow ramp up of the soft-start capacitor at

the non-inverting input of the error amplifier.

PGND is the reference potential (0 V) for the high-

current gate-drive circuit. Two bypass capacitors should

be connected between the VDD pin and the PGND pin.

One is the V_DDenergy storage capacitor, which provides

bias power during startup until the bootstrap power

supply comes up. The other capacitor shall be a good-

quality ceramic bypass capacitor, as close as possible

to PGND and VDD pins to filter the high peak currents

of the gate driver circuits. The value of the ceramic

bypass capacitor is a strong function of the gate charge

requirement of the power MOSFETs and its

recommended value is between 1 µF and 4.7 µF to

ensure proper operation.

5. Soft-Start (SS)

Soft-start is programmed with a capacitor between the

SS pin and AGND. This is the non-inverting input of the

transconductance (g_M) error amplifier.

At startup, the soft-start capacitor is quickly pre-charged

to a voltage approximately 0.5 V below the voltage on

the feedback pin (FB) to minimize startup delay. Then a

5 µA current source takes over and charges the soft-

start capacitor slowly, ramping up the voltage reference

of the error amplifier. By ramping up the reference

slowly, the voltage regulation loop can stay closed,

actively controlling the output voltage during startup.

While the SS capacitor is charging, the output of the

error amplifier is monitored. In case the error voltage

(COMP) ever exceeds 3.5 V, indicating that the voltage

loop is close to saturation, the 5 µA soft-start current is

reduced. Therefore, the soft start is automatically

extended to reduce the current needed to charge the

output capacitor, reducing the output power during

startup. This mechanism is integrated to prevent the

voltage loop from saturation. The charge current of the

soft-start capacitor can be reduced from the initial 5 µA

to as low as 0.5 µA minimum.

Figure 19. Soft-Start Programming

6. Error Amplifier Compensation (COMP)

COMP pin is the output of the error amplifier. The

voltage loop is compensated by a combination of R_S

and C_Sto AGND at this pin. The control range of the

error amplifier is between 0.195 V and 4.3 V. When the

COMP voltage is below about 0.195 V, the PWM circuit

skips pulses. Above 4.3 V, the maximum on-time limit

terminates the conduction of the boost switches.

Due to the input-voltage feedforward, the output of the

error amplifier is proportional to the input power of the

converter, independent of the input voltage. In addition,

also due to the input-voltage feedforward, the maximum

power capability of the converter and the loop gain is

independent of the input voltage. The controller’s phase-

management circuit monitors the error amplifier output

and switches to single-phase operation when the COMP

voltage falls below 0.73 V and returns to two-phase

operation when the error voltage exceeds 0.93 V. These

thresholds correspond to about 13% and 18% of the

maximum power capability of the design.

In addition to modulating the soft-start current into the

SS capacitor, the SS pin is clamped 0.2 V above the FB

pin. This is useful in preventing the SS capacitor from

running away from the FB pin and defeating the closed-

loop soft-start. During the zero crossing of the input

source waveform, the input power is almost zero and

FAN9612 • Rev. 1.1.7

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13

Figure 20. Error Amplifier Compensation Circuitry

7. Output Voltage Feedback (FB)

8. Secondary Output Voltage Sense (OVP)

The feedback pin receives the divided-down output

voltage of the converter. In regulation, the FB pin should

be 3 V, which is the reference used at the non-inverting

input of the error amplifier. Due to the g_Mtype error

amplifier, the FB pin is always proportional to the output

voltage and can be used for over-voltage protection as

A second-level latching over-voltage protection can be

implemented using the OVP pin of the controller. The

threshold of this circuit is set to 3.5 V. There are two

ways to program the secondary OVP.

Option 1, as shown in Figure 22, is to connect the OVP

pin to the FB pin. In addition to the standard non-

latching OVP (set at ~8%), this configuration provides a

second OVP protection (set at ~15%), which is latched.

well.

A non-latching over-voltage detection circuit

monitors the FB pin and prevents the boost MOSFETs

from turning on when the FB voltage exceeds 3.25 V.

Operation resumes automatically when the FB voltage

returns to its nominal 3 V level.

In the case where redundant over-voltage protection is

preferred (also called double-OVP protection), a second

separate divider from the output voltage can be used, as

shown by Option 2 in Figure 22. In this case, the

latching OVP protection level can be independently

established below or above the non-latching OVP

threshold, which is based on the feedback voltage (at

the FB pin).

The open feedback detection circuit is also connected to

the FB pin. Since the output of the boost converter is

charged to the peak of the input AC voltage when power

is applied to the power supply, the detection circuit

monitors the presence of this voltage. If the FB pin is

below 0.5 V, which would indicate a missing feedback

divider (or wrong value causing dangerously-high

regulation voltage), the FAN9612 does not send out

gate drive signals to the boost transistors.

If latching OVP protection is not desired at all, the OVP

pin should be grounded (Option 3).

Figure 22. Secondary Over-Voltage Protection

Circuit

Figure 21. Output-Voltage Feedback Circuit

FAN9612 • Rev. 1.1.7

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14

the integrator while the peak detector works properly

during light-load operation.

9. Input Voltage Sensing (V_IN)

The input AC voltage is sensed at the VIN pin. The input

voltage is used in two functions: input under-voltage

lockout (brownout protection), and input voltage

feedforward in the PWM control circuit. All the functions

require the RMS value of the input voltage waveform.

Since the RMS value of the AC input voltage is directly

proportional to its peak, it is sufficient to find the peak

instead of the more complicated and slower method of

integrating the input voltage over a half line cycle. The

internal circuit of the VIN pin works with peak detection

of the input AC waveforms. One of the important

benefits of this approach is that the peak indicates the

correct RMS value even at no load when the HF filter

capacitor at the input side of the boost converter is not

discharged around the zero crossing of the line

waveform. Another notable benefit is that during line

transients, when the peak exceeds the previously

measured value, the input-voltage feedforward circuit

can react immediately, without waiting for a valid

integral value at the end of the half line period.

Furthermore, lack of zero crossing detection could fool

The valid range for the peak of the AC input is between

approximately 0.925 V and 3.7 V. This range is

optimized for universal input voltage range of operation.

If the peak of the sense voltage remains below the

0.925 V threshold, input under-voltage or brownout

condition is declared and the FAN9612 stops operating.

When the V_INvoltage exceeds 3.7 V, the FAN9612 input

voltage sense circuit saturates and the feedforward

circuit is not able to follow the input any higher.

Consequently, the slope of the PWM ramp remains

constant corresponding to the V_IN

= 3.7 V level

amplitude for any V_INvoltage above 3.7 V.

The input voltage is measured by a tracking analog-to-

digital converter, which keeps the highest value (peak

voltage) of the input voltage waveform. Once

a

measurement is taken, the converter tracks the input for

at least 12 ms before a new value is taken. This delay

ensures at least one new peak value is captured before

the new value is used.

Figure 23. Input Voltage Sensing Circuit

The measured peak value is then used in the following

half-line cycle while a new measurement is executed to

be used in the next half line cycle. This operation is

synchronized to the zero crossing of the line waveform.

Since the input voltage measurement is held steady

during the line half periods, this technique does not feed

any AC ripple into the control loop. If line zero crossing

detection is missing, the FAN9612 measures the input

voltage in every 32 ms; it can operate from a DC input

as well. The following figures provide detail about the

input voltage sensing method of the controller.

As shown in the waveforms, input voltage feedforward is

instantaneous when the line voltage increases and has

a half line cycle delay when the input voltage decreases.

Any increase in input voltage would cause output over

voltage due to the slow nature of the voltage regulation

loop. This is successfully mitigated by the immediate

action of the input-voltage feedforward circuit.

FAN9612 • Rev. 1.1.7

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15

Figure 24. Input Voltage Sensing Waveforms

The purpose of the MillerDrive™ architecture is to

10. Gate Drive Outputs (DRV1; DRV2)

speed switching by providing high current during the

Miller plateau region when the gate-drain capacitance of

the MOSFET is being charged or discharged as part of

the turn-on / turn-off process.

High-current driver outputs DRV1 and DRV2 have the

capability to sink a minimum of 2 A and source 1 A. Due

to the low impedance of these drivers, the 1 A source

current must be actively limited by an external gate

resistor. The minimum external gate resistance is:

The output pin slew rate is determined by V_DDvoltage

and the load on the output. It is not user adjustable, but

if a slower rise or fall time at the MOSFET gate is

needed, a series resistor can be added.

V_DD

R_GATE

=

(3)

1A

To take advantage of the higher sink current capability

of the drivers, the gate resistor can be bypassed by a

small diode to facilitate faster turn-off of the power

MOSFETs. Traditional fast turn-off circuit using a PNP

transistor instead of a simple bypass diode can be

considered as well.

It is also imperative that the inductance of the gate drive

loop is minimized to avoid excessive ringing. If optimum

layout is not possible or the controller is placed on a

daughter card, it is recommended to use an external

driver circuit located near the gate and source terminals

of the boost MOSFET transistors. Small gate charge

power MOSFETs can be driven by a single 1A gate

driver, such as the FAN3111C; while higher gate charge

devices might require higher gate drive current capable

devices, such as the single-2 A FAN3100C or the dual-

2 A FAN3227C family of drivers.

11. MillerDrive™ Gate Drive Technology

Figure 25. Current-Sense Protection Circuits

FAN9612 output stage incorporates the MillerDrive™

architecture shown in Figure 25. It is a combination of

bipolar and MOS devices which are capable of providing

large currents over a wide range of supply voltage and

temperature variations. The bipolar devices carry the

bulk of the current as OUT swings between 1/3 to 2/3

V_DDand the MOS devices pull the output to the high

or low rail.

FAN9612 • Rev. 1.1.7

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16

12. Bias Supply (V_DD)

This is the main bias source for the FAN9612. The

operating voltage range is between 8 V and 18 V. The

V_DDvoltage is monitored by the under-voltage lockout

(UVLO) circuit. At power-up, the V_DDvoltage must

exceed 12.5 V (±0.5 V) to enable operation. The

FAN9612 stops operating when the V_DDvoltage falls

below 7.5 V (±0.5 V). See PGND pin description for

important bypass information.

13. Current-Sense Protection (CS1, CS2)

The FAN9612 uses independent over-current protection

for each of the power MOSFETs. The current-sense

thresholds at the CS1 and CS2 pins are approximately

0.2 V. The current measurements are strictly for

protection purposes and are not part of the control

algorithm. The pins can be directly connected to the

non-grounded end of the current-sense resistors

because the usual R-C filters of the leading-edge

current spike are integrated in the IC.

Figure 26. Current-Sense Protection Circuits

The time constant of the internal filter is approximately:

τ = 27kΩ⋅5pF = 130ns

or

(4)

1

ω_P

=

= 1.2MHz

2 ⋅π ⋅ 27kΩ ⋅ 5pF

FAN9612 • Rev. 1.1.7

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17

Application Information

2. Startup with 12 V Bias (Less than UVLO)

1. Synchronization and Timing Functions

The FAN9612 is designed so that the controller can

start even if the auxiliary bias voltage is less than the

controller’s under-voltage lockout start threshold. This is

useful if the auxiliary power is 12 V or below. This

configuration also allows bias power designs using a

bootstrap winding to start the FAN9612 without a

dedicated startup resistor.

The FAN9612 employs a sophisticated synchronization

sub-system. At the heart of the system is a dual-channel

switching-frequency detector that measures the

switching period of each channel in every switching

cycle and locks their operating phase 180 degrees out

of phase from each other. The slower operating

frequency channel is dominant, but there is no master-

slave arrangement. Moreover, as the frequency

constantly changes due to the varying input voltage,

either channel can be the slower dominant channel.

In the boost PFC topology, the output voltage is pre-

charged to the peak line voltage by the boost diode. As

soon as voltage is present at the output of the boost

converter, current starts to flow through the feedback

resistors from the boost output to GND. Using an

external low-voltage MOSFET in series with the lower

resistor in the feedback divider, as shown in Figure 27;

this current can be diverted to charge the V_DDbypass

capacitor of the controller. The upper resistor becomes

a current source to charge the capacitor. To accomplish

this, a small external diode should be connected

between the VDD and FB pins.

As opposed to the most common technique, where the

phase relationship between the channels is provided by

changing the on-time of one of the MOSFETs, the

FAN9612 controls the phase relationship by inserting a

turn-on delay before the next switching period starts for

the faster running phase. As shown in the literature^[1],

the on-time modulation technique is not stable under all

operating conditions, while the off-time modulation (or

delaying the turn-on) is unconditionally stable under all

operating conditions.

As V_DDrises past the under-voltage lockout threshold of

the IC, the 5 V reference is turned on, which turns on

the external MOSFET and connects the resistor of the

feedback divider to ground. The IC checks if the FB

voltage is below 3.22 V, ensuring that the FB pin is in its

normal operating voltage range, before enabling the rest

of the IC operation. The diode between the FB pin and

the VDD pin is reverse biased and the FB pin reverts to

its normal role of output voltage sensing. A simplified

circuit implementation for this proprietary startup method

is shown in Figure 27.

a. Restart Timer and Dead-Phase Detect

Protection

The restart timer is an integral part of the Sync-Lock™

synchronizing circuit. It ensures exact 180-degree out-

of-phase operation in restart timer operation. This is an

important safety feature. In the case of a non-operating

phase due to no ZCD detection, missing gate drive

connection (for example no gate resistor), one of the

power components failing in an open circuit, or similar

errors, the other phase is locked into restart timer

operation, preventing it from trying to deliver full power

to the load. This is called the dead-phase detect

protection.

If, for whatever reason, the bias to the IC drops below

the under-voltage lockout level, the startup process is

repeated.

The restart timer is set to approximately 16.5 kHz, just

above the audible frequency range, to avoid any

acoustic noise generation.

b. Frequency Clamp

Just as the restart timer, the frequency clamp is

integrated into the synchronization and ensures exact

180-degree out-of-phase operation when the operating

frequency is limited. This might occur at very light-load

operation or near the zero crossing region of the line

voltage waveform. Limiting the switching frequency at

light load can improve efficiency, but has a negative

effect on power factor since the converter also enters

true DCM operation. The frequency clamp is set to

approximately 525 kHz.

Figure 27. Simplified FAN9612 Startup Circuit Using

the Output Feedback Resistors to Provide a

Charging Current

FAN9612 • Rev. 1.1.7

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18

The default thresholds can be adjusted upward based

on the application requirement; for example, to meet the

Energy STAR 5.0 or the Climate Savers Computing

efficiency requirements at 20% of the load. The phase

drop threshold can be adjusted upward (for example to

25%) by adjusting the maximum on time.

3. Adjusting the Output Voltage with Load

In some applications, the output voltage of the PFC

boost converter is decreased at low power levels to

boost the light load efficiency of the power supply.

Implementing this function with a circuit external to the

FAN9612 is straightforward because the error amplifier

reference (the positive input) is available on the soft-

start (SS) pin, as shown in Figure 28. In the FAN9612

architecture, the power of the converter is proportional

to the voltage on the COMP pin, minus a small offset.

The voltage on the COMP pin is monitored to determine

the operating power of the supply. Therefore the voltage

on the SS pin can be adjusted lower to achieve the

desired lower output voltage.

Several possible implementations to adjust the output

voltage of the boost stage at light load are described in

the application note AN-8021. It includes the universal

output voltage adjust implementation which is

modulated by input voltage to avoid the boost converter

becoming a peak rectifier at high line and light load.

Figure 29. Adjusting Phase Management Thresholds

Since the phase management threshold is fixed at 13%

and 18% of the maximum power limit level, the actual

power management threshold as a percentage of

nominal output power can be adjusted by the ratio

between nominal power and maximum power limit level

as shown in Figure 29. The second plot shows an

example where the maximum power limit level is 1.4

times of nominal output power. By adjusting the

maximum on-time (using R_MOT), the phase management

thresholds can be adjusted upward.

Phase management is implemented such that the

output of the error amplifier (V_COMP) does not have to

change when the system toggles between single-phase

and two-phase operations, as shown in Figure 30. The

output of the error amplifier is proportional to the output

power of the converter independently, whether one or

both phases are operating in the power supply.

Furthermore, because the maximum on-time limit is

applied independently to each pulse-width modulator,

the power handling capability of the converter with only

one phase running is approximately half of the total

output power that can be delivered when both phases

are utilized.

Figure 28. Error Amplifier Configuration

4. Adjusting the Output Voltage with Input

Voltage

In some applications, the output voltage of the PFC

boost converter is adjusted based on the input voltage

only. This boost follower implementations increases the

efficiency of the downstream DC-DC converter and

therefore of the overall power supply.

Implementations for both the two-level boost and the

linear boost follower (or tracking boost) are described in

application note AN-8021.

Additional details on adjusting phase management are

provided in the application note AN-6086.

5. Adjusting the Phase-Management

Thresholds

In any power converter, the switching losses become

dominant at light load. For an interleaved converter

where there are two or more phases, light-load

efficiency can be improved by shutting down one of the

phases at light load (also known as phase-shedding or

phase-dropping operating).

The initial phase-management thresholds are fixed at

approximately 13% and 18% of the maximum load

power level. This means when the output power

reaches 13%, the FAN9612 automatically goes from a

two-phase to a single-phase operation (phase shed or

phase drop). When the output power comes back up to

18%, the FAN9612 automatically goes from the single-

phase to the two-phase operation (phase-add).

MAX

Figure 30. V_COMPvs. t_ON

FAN9612 • Rev. 1.1.7

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19

6. Disabling the FAN9612

d. Pull the VIN Pin to GND. Since the VIN sense

circuit is configured to ride through a single line

cycle dropout test without shutting down the power

supply, this method results in a delayed shutdown

of the converter. The FAN9612 stops operation

approximately 20 ms to 32 ms after the VIN pin is

pulled LOW. The delay depends on the phase of

the line cycle at which the pull-down occurs. This

method triggers the input brownout protection (input

under-voltage lockout), which gradually discharges

the compensation capacitor. As the output voltage

decreases, the FB pin falls, pulling LOW the SS

capacitor voltage. Similarly to the shutdown, once

the VIN pin is released, operation resumes after

several milliseconds of delay needed to determine

that the input voltage is above the turn-on

threshold. At least one line cycle peak must be

detected above the turn-on threshold before

operation can resume at the following line voltage

zero-crossing. The converter starts following normal

soft-start procedure.

There are four ways to disable the FAN9612. It is

important to understand how the part reacts for the

various shutdown procedures.

a. Pull the SS Pin to GND. This method uses the error

amplifier to stop the operation of the power supply.

By pulling the SS pin to GND, the error amplifier’s

non-inverting input is pulled to GND. The amplifier

senses that the inverting input (FB pin) is higher

than the reference voltage and tries to adjust its

output (COMP pin) to make the FB pin equal to the

reference at the SS pin. Due to the slow speed of

the voltage loop in PFC applications, this might take

several line cycles. Thus, it is important to consider

that by pulling the SS pin to GND, the power supply

is not shut down immediately. Recovery from a shut

down follows normal soft-start procedure when the

SS pin is released.

b. Pull the FB Pin to GND. By pulling the FB pin below

the open feedback protection threshold of

approximately 0.5 V, the power supply can be shut

down immediately. It is imperative that the FB is

pulled below the threshold very quickly since the

power supply keeps switching until this threshold is

crossed. If the feedback is pulled LOW softly and

does not cross the threshold, the power supply tries

to deliver maximum power because the FB pin is

forced below the reference voltage of the error

amplifier on the SS pin. Eventually, as FB is pulled

to GND, the SS capacitor is pulled LOW by the

internal clamp between the FB and SS pins. The

SS pin stays approximately 0.5 V higher than the

FB pin itself. Therefore, recovery from a shut down

state follows normal soft-start procedure when the

FB pin is released as the voltage across the SS

capacitor starts ramping from a low value.

7. Layout and Connection Guidelines

For high-power applications, two or more PCB layers

are recommended to effectively use the ground pattern

to minimize the switching noise interference.

The FAN9612 incorporates fast-reacting input circuits,

short propagation delays, and strong output stages

capable of delivering current peaks over 1.5 A to

facilitate fast voltage transition times. Many high-speed

power circuits can be susceptible to noise injected from

their own output or external sources, possibly causing

output re-triggering. These effects can be especially

obvious if the circuit is tested in breadboard or non-

optimal circuit layouts with long input or output leads.

The following guidelines are recommended for all layout

designs, but especially strongly for the single-layer PCB

designs. (For example of a 1-layer PCB design, see the

Application Note AN-6086.)

c. Pulling the COMP Pin to GND. When the COMP

pin is pulled below the PWM ramp offset,

approximately 0.195 V, the FAN9612 stops sending

gate drive pulses to the power MOSFETs. This

condition is similar to pulse skipping under no-load

condition. If any load is still present at the output of

the boost PFC stage, the output voltage decreases.

Consequently, the FB pin decreases and the SS

capacitor voltage is pulled LOW by the internal

clamp between the FB and SS pins. At that point,

the operation and eventual recovery to normal

operation is similar to the mechanism described

above. If the COMP pin is held LOW for long

enough to pull the SS pin LOW, the recovery

follows normal soft-start procedure when the COMP

pin is released. If the SS capacitor is not pulled

LOW as a result of a momentary pull-down of the

COMP pin, the recovery is still soft due to the fact

that a limited current source is charging the

compensation capacitors at the output of the error

amplifier. Nevertheless, in this case, output voltage

overshoot can occur before the voltage loop enters

closed-loop operation and resumes controlling the

output voltage again.

General

.

Keep high-current output and power ground paths

separate from analog input signals and signal

ground paths.

.

For best results, make connections to all pins as

short and direct as possible.

Power Ground and Analog Ground

.

Power ground (PGND) and analog ground (AGND)

should meet at one point only.

All the control components should be connected to

AGND without sharing the trace with PGND.

The return path for the gate drive current and V_DD

capacitor should be connected to the PGND pin.

Minimize the ground loops between the driver

outputs (DRV1, DRV2), MOSFETs, and PGND.

Adding the by-pass capacitor for noise on the VDD

pin is recommended. It should be connected as

close to the pin as possible.

FAN9612 • Rev. 1.1.7

www.fairchildsemi.com

20

Gate Drive

.

To minimize switching noise, current sensing

should not make a loop.

.

The gate drive pattern should be wide enough to

handle 1 A peak current.

Input Voltage Sensing (V_IN)

.

Keep the controller as close to the MOSFETs as

possible. This minimizes the length and the loop

area (series inductance) of the high-current gate

drive traces. The gate drive pattern should be as

short as possible to minimize interference.

.

Since the impedance of voltage divider is large and

FAN9612 detects the peak of the line voltage, the

VIN pin can be sensitive to the switching noise. The

trace connected to this pin should not cross traces

with high di/dt to minimize the interference.

Current Sensing

.

The noise bypass capacitor for V_INshould be

connected as close to the pin as possible.

.

Current sensing should be as short as possible.

FAN9612 • Rev. 1.1.7

www.fairchildsemi.com

21

Quick Setup Guide

The FAN9612 can be configured following the next

steps outlined in this section. This Quick Setup Guide

refers to the schematic diagram and component

references of Figure 33. It uses the equations derived

and explained in Application Note AN-6086.

Input Voltage Sense Divider

Brownout Hysteresis Set

Gate Drive Resistor

R_IN2

R_INHYST

R_G1, R_G2

D_G1, D_G2

C_VDD1

Gate Drive Speed-Up Diode

Bypass Capacitor for VDD_HF

Startup Energy Storage for V_DD

Current Sense Resistor

2.2μ

47μ

In preparation to calculate the setup component values,

the power supply specification must be known.

Furthermore, a few power stage components must be

pre-calculated before the controller design begins as

their values determine the component selections. An

Excel design tool is also available to ease calculations.

C_VDD2

R_CS1, R_CS2

Step 1: Input Voltage Range

Description

From Power Supply Specification:

Minimum AC RMS Input (Turn-On)

Minimum AC RMS Input (Turn-Off)

Minimum Line Frequency

Name Value

FAN9612 utilizes a single pin (VIN) for input voltage

sensing. The VIN pin must be above 0.925 V (V_{IN_BO}) to

enable operation. The converter turns on at a higher

VIN voltage (V_{IN_ON}) set independently by the designer.

The input voltage information is used for feedforward in

the control algorithm as well. The input-voltage

feedforward operates over a four-to-one range from

0.925 V (V_{IN_BO}) to 3.7 V (V_{FF_UL}), as measured at the

VIN pin.

V_LINE.ON

V_LINE.OFF

f_LINE,MIN

V_OUT

Nominal DC Output

Output Voltage Ripple (2 · f_LINE

)

V_OUT,RIPPLE

V_OUT,LATCH

P_OUT

Latching Output OVP

Nominal Output Power (to Load)

Desired Hold-Up Time

t_HOLD

Minimum DC Output (End of t_HOLD

Minimum Switching Frequency

Maximum DC Bias

)

V_OUT,MIN

f_SW,MIN

V_DDMAX

Pre-Calculated Power Stage Parameters:

Estimated Conversion Efficiency

Maximum Output Power per Channel

Output Capacitance

η

P_MAX,CH

C_OUT

L

0.95

Figure 31. VIN Turn-on and Turn-off Thresholds

At V_INvoltages above the 3.7 V upper limit (V_{FF_UL}),

input voltage feedforward is not possible. The input

voltage-sense circuitry saturates at this point and the

PWM ramp is modulated any longer. Above V_{FF_UL}, the

converter’s output power becomes a function of the

input voltage as shown in Figure 32. It can also be

expressed analytically as:

Boost Inductance per Channel

Maximum On-Time per Channel

t_ON,MAX

N

Other Variables Used During the Calculations:

Turns Ratio (N_BOOST/ N_AUX

)

10

Peak Inductor Current

I_L,PK

2

VIN

3.7









Maximum DC Output Current (to Load)

Calculated Component Values:

I_O,MAX

(5)

P_{OUT_NO_FF}= P_MAX

•





R_ZCD1

R_ZCD2

,

where VIN is the voltage at the VIN pin and P_MAXis the

desired maximum output power of the converter which

will be maintained constant while the input voltage

feedforward circuit is operational.

Zero Current Detect Resistor

Bypass Capacitor for 5 V Bias

Maximum On-Time Set

Soft-Start Capacitor

C_5VB

R_MOT

C_SS

0.15μ

Compensation Capacitor

Compensation Resistor

Compensation Capacitor

Feedback Divider

C_COMP,LF

R_COMP

C_COMP,HF

R_FB1

Feedback Divider

R_FB2

Figure 32. VIN Feedforward Range

Over Voltage Sense Divider

Input Voltage Sense Divider

R_OV1

R_OV2

As can be seen, the converter’s output power capability

R_IN1

will follow a square function above V_{FF_UL}

.

FAN9612 • Rev. 1.1.7

www.fairchildsemi.com

22

Figure 33. Interleaved BCM PFC Schematic Using FAN9612

Step 2: Estimated Conversion Efficiency

Step 3: Maximum Output Power per

Channel

Use the estimated full-load power conversion efficiency.

Typical value for an interleaved BCP PFC converter is in

the 0.92 to 0.98 range. The efficiency is in the lower half

of the range for low-power applications. Using state-of-

the-art semiconductors, good quality ferrite inductors

and selecting lower limit for minimum switching

frequency positively impacts the efficiency of the

system. In general, the value of 0.95 can be used

unless a more accurate power budget is available.

P_OUT

2

P_MAX,CH= 1.2 ⋅

(6)

A margin of 20% has been added to the nominal output

power to cover reference inaccuracy, internal

component tolerances, inductance mismatch, and

current-sense resistor variation to the per-channel

power rating.

FAN9612 • Rev. 1.1.7

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23

Step 4: Output Capacitance

Step 9: Zero Current Detect Resistors

P_OUT

C_OUT(RIPPLE)

=

(7)

(8)

0.5 ⋅ V_OUT

N⋅0.5mA

4⋅ f_LINE,MIN⋅ V_OUT⋅ V_OUT,RIPPLE

R_ZCD1= R_ZCD2

=

(14)

2⋅P_OUT⋅ t_HOLD

C_OUT(HOLD)

=



²

where 0.5·V_OUTis the maximum amplitude of the

resonant waveform across the boost inductor during

zero current detection; N is the turns ratio of the boost

inductor and the auxiliary winding utilized for the zero

current detection; and 0.5 mA is the maximum current

of the ZCD pin during the zero current detection period.

V_OUT,RIPPLE

V_OUT

−

− V_O²_UT,MIN







2



The output capacitance must be calculated by two

different methods. The first equation determines the

capacitor value based on the allowable ripple voltage at

the minimum line frequency. It is important to remember

that the scaled version of this ripple is present at the FB

pin. The feedback voltage is continuously monitored by

the non-latching over voltage protection circuit. Its

threshold is about 8% higher the nominal output voltage.

To avoid triggering the OVP protection during normal

operation, V_OUT,RIPPLEshould be limited to less 12% of

Step 10: Maximum On-Time Setting

Resistor

R_MOT= 4340⋅10⁶⋅ t_ON,MAX

(15)

where R_MOTshould be between 40 kΩ and 130 kΩ.

the nominal output voltage, V_OUT

.

Step 11: Output Voltage Setting Resistors

(Feedback)

The second expression yields the minimum output

capacitance based on the required hold-up time based

on the power supply specification. Ultimately, the larger

of the two values satisfies both design requirements and

3V ⋅ V_OUT

3V

I_FB

R_FB2

=

(16)

P_FB

has to be selected for C_OUT

.

where 3 V is the reference voltage of the error amplifier

at its non-inverting input and P_FBor I_FBare selected by

the designer. If the power loss associated to the

feedback divider is critical to meet stand-by power

consumption regulations, it might be beneficial to start

the calculation by choosing P_FB. Otherwise, the current

of feedback divider, I_FBshould be set to approximately

0.4 mA at the desired output voltage set point. This

value ensures that parasitic circuit board and pin

capacitances do not introduce unwanted filtering effect

in the feedback path.

Step 5: Boost Inductance per Channel

η ⋅ V_L²_INE,OFF

⋅

(

V_OUT

−

2 ⋅ V_LINE,OFF

)

L_LINE,OFF

=

(9)

2⋅ f_SW,MIN⋅ V_OUT⋅P_MAX,CH

η⋅ V_L²_INE,MAX

⋅

(

V_OUT

−

2 ⋅ V_LINE,MAX

)

L_LINE,MAX

(10)

2⋅ f_SW,MIN⋅ V_OUT⋅P_MAX,CH

The minimum switching frequency can occur either at

the lowest or at the highest input line voltage.

Accordingly, two boost inductor values are calculated

and the lower of the two inductances must be selected.

This L value keeps the minimum operating frequency

above f_SW,MINunder all operating conditions.

If the feedback divider is used to provide startup power

for the FAN9612 (see AN-6086 for implementation

details), the following equation is used to calculate R_FB2

:

3V ⋅

[

2 ⋅ V_LINE,ON

−

(

12.5V + 3⋅0.7V

)

]

(17)

R_FB2

=

Step 6: Maximum On-Time per Channel

0.12mA ⋅ V_OUT

2⋅L ⋅P_MAX,CH

η⋅ V_L²_INE,OFF

t_ON,MAX

=

where 3 V is the reference voltage of the error amplifier

at its non-inverting input; 12.5 V is the controller’s

UVLO turn-on threshold; 0.12 mA is the worst-case

startup current required to start operation; and 3·0.7 V

accounts for the forward voltage drop of three diodes in

series of the startup current. Once the value of R_FB2is

determined, R_FB1is given by the following formula:

(11)

Step 7: Peak Inductor Current per Channel

2 ⋅ V_LINE,OFF

(12)

I_L,PK

=

⋅ t_ON,MAX

L

V





OUT

R_FB1= 

−1⋅R_FB2

(18)





3V





Step 8: Maximum DC Output Current

2 ⋅P_MAX,CH

R_FB1can be implemented as a series combination of two

or three resistors; depending on safety regulations,

maximum voltage, and or power rating of the selected

resistor type.

I_OUT,MAX

=

(13)

V_OUT

FAN9612 • Rev. 1.1.7

www.fairchildsemi.com

24

Step 12: Soft-Start Capacitor

The recommended f_HFPfrequency is around 120 Hz in

PFC applications.

5μA ⋅ C_OUT

⋅

(

R_FB1+ R_FB2

)

C_SS

=

(19)

0.3 ⋅I_OUT,MAX⋅ R_FB2

Step 14: Over-Voltage Protection Setting

(OVP)

where 5 μA is the charge current of the soft-start

capacitor and 0.3·I_OUT,MAXis the maximum output

current charging the output capacitor of the converter

during the soft-start process. It is imperative to limit the

charge current of the output capacitor to be able to

maintain closed-loop soft-start of the converter. The

0.3 factor used in the C_SSequation can prevent output

over voltage at the end of the soft-start period and

provides sufficient margin to supply current to the load

while the output capacitor is charging.

3.5V ⋅ V_OUT,LATCH

R_OV2

=

(24)

P_OVP

where 3.5 V is the threshold voltage of the OVP

comparator and P_OVPis the total dissipation of the

resistive divider network. Typical P_OVPpower loss is in

the 50 mW to 100 mW range.

V













OUT,LATCH

Step 13: Compensation Components



R_OV1

=

−1 ⋅R_OV2

(25)

3.5V

g_M⋅I_OUT,MAX

4.1V⋅C_OUT2⋅π ⋅f₀

R_FB2

C_COMP,LF

=

⋅

(20)

2

R_FB1+R_FB2

⋅

(

)

R_OV1can be implemented as a series combination of

two or three resistors; depending on safety regulations,

maximum voltage, and or power rating of the selected

resistor type.

where 4.1 V is the control range of the error amplifier

and f₀is the desired voltage loop crossover frequency.

It is important to consider that the lowest output ripple

frequency limits the voltage loop crossover frequency.

In PFC applications, that frequency is two times the AC

line frequency. Therefore, the voltage loop bandwidth

(f₀), is typically in the 5 Hz to 15 Hz range.

Step 15: Input Line Voltage Sense

Resistors

0.925V • V ²

LINE,MAX

R_IN2

=

(26)

2 • V_LINE,MIN• P

INSNS

To guarantee closed-loop soft-start operation under all

conditions, it is recommended that:

where 0.925 V is the brownout protection threshold at

the VIN pin. V_LINE,MINis the minimum input RMS

operating voltage. Its divided down level at the VIN pin

corresponds to the 0.925 V brownout protection

threshold. V_LINE,MAXis the maximum input RMS voltage

anticipated in the design and P_INSNSis the total power

dissipation of the R_IN1- R_IN2divider when the input

voltage equals V_LINE,MAX. Typical P_INSNSpower loss is in

the 50 mW to 100 mW range.

C_COMP,HF< 4⋅C_SS

(21)

This relationship is determined by the ratio between the

maximum output current of the g_Merror amplifier to the

maximum charge current of the soft-start capacitor.

Observing this correlation between the two capacitor

values ensures that the compensation capacitor voltage

can be adjusted faster than any voltage change taking

place across the soft-start capacitor. Therefore, during

startup the voltage regulation loop’s response to the

increasing soft-start voltage is not limited by the finite

current capability of the error amplifier.











2 ⋅ V_LINE,MIN

0.925V



R_IN1

=

−1 ⋅R_IN2

(27)





R_IN1can be implemented as a series combination of two

or three resistors; depending on safety regulations,

maximum voltage, and or power rating of the selected

resistor type.

1

R_COMP

=

(22)

(23)

2⋅ π ⋅ f₀⋅C_COMP,LF













2 ⋅ V_LINE,ON⋅R_IN2

R_IN1+R_IN2

1

− 0.925V

C_COMP,HF

=

(28)

2⋅ π ⋅ f_HFP⋅R_COMP

R_INHYST

=

2μA

where f_HFPis the frequency of a pole implemented in

the error amplifier compensation network against high-

frequency noise in the feedback loop. The pole should

be placed at least a decade higher than f₀to ensure

that it does not interfere with the phase margin of the

voltage regulation loop at its crossover frequency. It

should also be sufficiently lower then the switching

frequency of the converter so noise can be effectively

attenuated.

where 0.925 V is the threshold voltage of the line

under-voltage lockout comparator and 2 μA is the sink

current provided at the VIN pin during line under-

voltage (brownout) condition. The sink current,

together with the terminating impedance of the VIN pin

determines the hysteresis between the turn-on and

turn-off thresholds.

FAN9612 • Rev. 1.1.7

www.fairchildsemi.com

25

The FAN9612 sources high peak current to the

MOSFET gate through R_Gand D_ON, where R_Gis used to

control the turn-on transition time. When the MOSFET is

commanded to turn off, Q_OFFconducts, shorting the gate

to the source, where the turn-off speed can be

controlled by the value of R_OFF. Where maximum turn-

off time is desired, the value of R_OFFcan be 0 Ω. D_ON

serves the dual purpose of protecting the Q_OFFbase-

emitter junction and blocking the MOSFET discharge

current from sinking back through the FAN9612.

Step 16: Gate Resistors

It is recommended to place at least a 15 Ω resistor

between each of the gate drive outputs (DRV1, DRV2)

and their corresponding power devices. The gate drive

resistors have a beneficial effect to limit the current

drawn from the V_DDbypass capacitor during the turn-on

of the power MOSFETs and to attenuate any potential

oscillation in the gate drive circuits.

VDD_MAX

In addition to the high-speed turn-off, another advantage

of this circuit is that the FAN9612 does not have to sink

the high peak discharge current from the MOSFET,

reducing the internal power dissipation in the gate drive

circuitry by a factor of two. Instead, the current is

discharged locally in a tighter, more controlled loop,

minimizing parasitic trace inductance while protecting the

FAN9612 from injected disturbances associated with

ground bounce and ringing due to high-speed turn-off.

R_G1= R_G2

=

(29)

1.0A

where 1.0 A is the recommended peak value of the

gate drive current.

Step 17: Current-Sense Resistors

0.18V

R_CS1= R_CS2

=

(30)

I_L,PK

Figure 34. Recommended Gate Drive Schematic

where 0.18 V is the worst-case threshold of the current

limit comparator. The size and type of current sense

resistors depends on their power dissipation and

manufacturing considerations.

A speed-up discharge diode that feeds switching current

back into the IC is not recommended.









4⋅ 2 ⋅ V_LINE,OFF

9⋅ π ⋅ V_OUT

1

6

P_RCS1= 1.5⋅I_L²_,PK⋅R_CS1

⋅

−

(31)









where the 1.5 factor is used for the worst-case effect of

the current-limit threshold variation. When the current-

sense resistor is determined, the minimum current-

sense threshold must be used to avoid activating over-

current protection too early as the power supply

approaches full-load condition. The worst-case power

dissipation of the current sense resistor occurs when

the current-sense threshold is at its maximum value

defined in the datasheet. The ratio between the

minimum and maximum thresholds squared (since the

square of the current determines power dissipation)

yields exactly the 1.5 factor used in the calculation.

Figure 35. Discharge Diode is Not Recommended

In cases where it is desirable to control the MOSFET

turn-on and turn-off transition times independently, the

circuit of Figure 36 can be used.

Figure 36. Gate Drive Schematic with Independent

Turn-On and Turn-Off

FAN9612 • Rev. 1.1.7

www.fairchildsemi.com

26

Typical Performance Characteristics — Supply

Typical characteristics are provided at T_A= 25°C and V_DD= 12 V unless otherwise noted.

Figure 37. I_STARTUPvs. Temperature

Figure 38. Operating Current vs. Temperature

Figure 39. UVLO Thresholds vs. Temperature

Figure 40. UVLO Hysteresis vs. Temperature

FAN9612 • Rev. 1.1.7

www.fairchildsemi.com

27

Typical Performance Characteristics — Control

Typical characteristics are provided at T_A= 25°C and V_DD= 12 V unless otherwise noted.

Figure 41. Transfer Function

(Maximum On Time vs. V_IN)

Figure 42. Maximum On Time vs. Temperature

Figure 43. EA Transconductance (g_M) vs.

Temperature

Figure 44. EA Reference vs. Temperature

Figure 45. 5V Reference vs. Temperature

Figure 46. Soft-Start Current vs. Temperature

FAN9612 • Rev. 1.1.7

www.fairchildsemi.com

28

Typical Performance Characteristics — Control

Typical characteristics are provided at T_A= 25°C and V_DD= 12 V unless otherwise noted.

Figure 47. Phase-Control Thresholds vs. Temperature

Gate Drive 1

Gate Drive 2

Gate Drive 1

Gate Drive 2

Inductor Current 1

Inductor Current 2

Inductor Current 1

Inductor Current 2

Figure 48. Phase-Dropping Operation

Figure 49. Phase-Adding Operation

FAN9612 • Rev. 1.1.7

www.fairchildsemi.com

29

Typical Performance Characteristics — Protection

Typical characteristics are provided at T_A= 25°C and V_DD= 12 V unless otherwise noted.

Figure 50. CS Threshold vs. Temperature

Figure 52. Restart Timer Frequency vs. Temperature

Figure 54. Brownout Threshold vs. Temperature

Figure 51. CS to OUT Delay vs. Temperature

Figure 53. Maximum Frequency Clamp

vs. Temperature

FAN9612 • Rev. 1.1.7

www.fairchildsemi.com

30

Typical Performance Characteristics — Protection

Typical characteristics are provided at T_A= 25°C and V_DD= 12 V unless otherwise noted.

Figure 55. Non-Latching OVP vs. Temperature

Figure 56. Latching OVP vs. Temperature

Figure 57. OVP Hysteresis vs. Temperature

FAN9612 • Rev. 1.1.7

www.fairchildsemi.com

31

Typical Performance Characteristics — Operation

Typical characteristics are provided at T_A= 25°C and V_DD= 12 V unless otherwise noted.

I_L1

I_L2

I

_L1+ I_L2

I_L1+ I_L2

Figure 58. Ripple-Current Cancellation (110 V_AC

)

Figure 59. Ripple-Current Cancellation (110 V_AC)

V_GATE

V_OUT

Line Current

Line

Current

Figure 60. No-Load Startup at 115 V_AC

Figure 61. Full-Load Startup at 115 V_AC

Line

Vol

110V_AC

220V_AC

V_OUT

COMP

Line

Current

Figure 62. Input Voltage Feedforward

Note:

6. For full performance operational characteristics at both low line (110 V_AC) and high line (220 V_AC), as well as at

no-load and full-load, refer to FEB388 Evaluation Board User Guide: 400 W Evaluation Board using

FAN9611/12.

FAN9612 • Rev. 1.1.7

www.fairchildsemi.com

32

Evaluation Board

FEB388: 400-W Evaluation Board Using FAN9611/12

FEB388 is one of the evaluation boards for an interleaved

dual boundary-conduction-mode PFC converter. It is

rated at 400 W (400 V/1 A) power. With phase

management, efficiency is maintained above 96% even

down at 10% of the rated output power. The efficiencies

for full-load condition exceed 96% as shown below.

Figure 63 and Figure 64 show the phase management

with the default minimum threshold values of the IC.

They can be adjusted upwards to achieve a different

efficiency profile (Figure 65 and Figure 66) where phase

management thresholds are adjusted to 30% / 44% of

the full load. For full specification, design schematic, bill

of materials and test results; see FEB388 — FAN9611/12

400W Evaluation Board User Guide (AN-9717).

Input Voltage

Rated Output Power

Output Voltage (Rated Current)

V_INNominal: 85 V~264 V_AC

V_DDSupply: 13 V~18 V_DC

400 W

400 V (1 A)

Figure 63. Measured Efficiency at 115 V_AC

(Default Thresholds)

Figure 64. Measured Efficiency at 230 V_AC

(Default Thresholds)

FAN9612 Efficiency vs. Load

(230 V_ACInput, 400 V_DCOutput, 400W)

(115 V_ACInput, 400 V_DCOutput, 400W)

100

95

With Phase Management

90

Without Phase Management

85

0

10

20

30

40

50

60

70

80

90

100

0

10

20

30

40

50

60

70

80

90

100

Output Power (%)

Figure 65. Measured Efficiency at 115 V_AC

(Adjusted Thresholds)

Figure 66. Measured Efficiency at 230 V_AC

(Adjusted Thresholds)

FAN9612 • Rev. 1.1.7

www.fairchildsemi.com

33

Table 1. Related Products

Part

Number

of Pins

Description

PFC Control

Comments

Number

Industry Standard Pin-Out with

Green Mode Functions

FAN6961 Green Mode PFC

Single BCM (CRM)

8

FAN7527B Boundary Mode PFC Control IC

Industry Standard Pin-Out

Dual Output Critical Conduction

FAN7528

Low THD for Boost-Follower

Implementation

Mode PFC Controller

Critical Conduction Mode PFC

FAN7529

Controller

Single BCM (CRM)

8

Low THD

Critical Conduction Mode PFC

Low THD, Alternate Pin-Out of

FAN7529 (Pins 2 and 3 Reversed)

FAN7530

Controller

PFC Ready pin, Frequency Limit,

AC-Line-Absent Detection, Soft-

Start to Minimize Overshoot,

Critical Conduction Mode PFC

FAN7930

Controller

Single BCM (CRM)

8

Integrated THD Optimizer, TSD

Interleaved Dual BCM PFC

Dual BCM (CRM), 180°

Out-of-Phase, 10.0V UVLO

FAN9611

Controller

Dual BCM (CRM)

16

Interleaved Dual BCM PFC

Controller

Dual BCM (CRM), 180°

Out-of-Phase, 12.5V UVLO

FAN9612

Dual BCM (CRM)

16

Related Resources

.

AN-6086: Design Consideration for Interleaved Boundary Conduction Mode (BCM) PFC Using FAN9612

AN-9717: Fairchild Evaluation Board User Guide FEB388: 400W Evaluation Board using FAN9611/12

AN-8021: Building Variable Output Voltage Boost PFC Converters Using FAN9612

References

1. L. Huber, B. Irving, C. Adragna and M. Jovanovich, “Implementation of Open-Loop Control for Interleaved

DCM/BCM Boundary Boost PFC Converters”, Proceedings of APEC ’08, pp. 1010-1016.

2. C. Bridge and L. Balogh, “Understanding Interleaved Boundary Conduction Mode PFC Converters”,

Fairchild Power Seminars, 2008-2009.

FAN9612 • Rev. 1.1.7

www.fairchildsemi.com

34

Physical Dimensions

10.00

9.80

A

8.89

16

9

B

1.75

4.00

3.80

6.00

5.6

1

8

PIN ONE

INDICATOR

0.51

0.35

1.27

(0.30)

1.27

0.65

M

0.25

C B A

LAND PATTERN RECOMMENDATION

1.75 MAX

SEE DETAIL A

1.50

1.25

0.25

0.19

0.25

0.10

C

0.10 C

0.50

0.25

X 45°

NOTES: UNLESS OTHERWISE SPECIFIED

(R0.10)

A) THIS PACKAGE CONFORMS TO JEDEC

MS-012, VARIATION AC, ISSUE C.

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD

FLASH AND TIE BAR PROTRUSIONS

GAGE PLANE

0.36

8°

0°

D) CONFORMS TO ASME Y14.5M-1994

E) LANDPATTERN STANDARD: SOIC127P600X175-16AM

F) DRAWING FILE NAME: M16AREV12.

SEATING PLANE

0.90

0.50

(1.04)

DETAIL A

SCALE: 2:1

Figure 67. 16-Lead SOIC Package

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the

warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

FAN9612 • Rev. 1.1.7

www.fairchildsemi.com

35

FAN9612 • Rev. 1.1.7

www.fairchildsemi.com

36

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1


型号：	FAN9612MX
厂家：	ONSEMI
描述：	交错双 CrCM PFC 控制器控制器功率因数校正光电二极管
文件：	总38页 (文件大小：1705K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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