FCH072N60F-F085 [ONSEMI]
N 沟道，SuperFET II™ FRFET MOSFET 600V，52A，62mΩ;
| 型号： | FCH072N60F-F085 |
| 厂家： | 
ONSEMI |
| 描述： | N 沟道，SuperFET II™ FRFET MOSFET 600V，52A，62mΩ 局域网 开关 晶体管 |
| 文件： | 总10页 (文件大小：408K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MOSFET – N-Channel,
SUPERFET II, FRFET
600 V, 52 A, 72 mW
FCH072N60F-F085
Description
®
SUPERFET II MOSFET is ON Semiconductor’s brand−new high
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voltage super−junction (SJ) MOSFET family that is utilizing charge
balance technology for outstanding low on−resistance and lower gate
charge performance. This technology is tailored to minimize
conduction loss, provide superior switching performance, dv/dt rate
and higher avalanche energy. Consequently SUPERFETII is very well
suited for the Soft switching and Hard Switching topologies like High
Voltage Full Bridge and Half Bridge DC−DC, Interleaved Boost PFC,
V
R
MAX
I MAX
D
DSS
DS(ON)
600 V
72 mW
52 A
D
®
Boost PFC for HEV−EV automotive. SUPERFET II FRFET
MOSFET’s optimized body diode reverse recovery performance can
remove additional component and improve system reliability.
Features
G
• Typical R
• Typical Q
= 62 mW at V = 10 V, I = 26 A
GS D
DS(on)
= 160 nC at V = 10 V, I = 26 A
g(tot)
GS
D
S
• UIS Capability
N-Channel MOSFET
• Qualified to AEC Q101 and PPAP Capable
• This Device is Pb−Free and is RoHS Compliant
Applications
• Automotive On Board Charger
• Automotive DC/DC Converter for HEV
G
D
S
TO−247
CASE 340CK
MARKING DIAGRAM
$Y&Z&3&K
FCH
072N60F
$Y
&Z
&3
&K
= ON Semiconductor Logo
= Assembly Plant Code
= Data Code (Year & Week)
= Lot Code
FCH072N60F = Specific Device Code
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
November, 2020 − Rev. 3
FCH072N60F−F085/D
FCH072N60F−F085
MAXIMUM RATINGS (T = 25°C, unless otherwise specified)
C
Symbol
Parameter
Ratings
600
Unit
V
V
DSS
Drain to Source Voltage
Gate to Source Voltage
V
GS
20
V
I
D
Drain Current − Continuous (V = 10) (Note 1)
T
T
= 25°C
= 100°C
52
33
A
GS
C
C
Pulsed Drain Current
See Fig. 4
1128
E
AS
Single Pulsed Avalanche Rating (Note 2)
MOSFET dv/dt
mJ
dv/dt
100
V/ns
Peak Diode Recovery dv/dt (Note 3)
Power Dissipation
50
P
481
W
W/°C
°C
D
Derate Above 25°C
3.85
T , T
Operating and Storage Temperature (Note 4)
−55 to +150
J
STG
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Current is limited by bondwire configuration.
2. Starting T = 25°C, L = 25 mH, I = 9.5 A, V = 100 V during inductor charging and V = 0 V during time in avalanche.
J
AS
DD
DD
3. I ≤ 26 A, di/dt ≤ 200 A/ms, V ≤ 380 V, starting T = 25°C.
SD
DD
J
4. R
is the sum of the junction−to−case and case−to−ambient thermal resistance, where the case thermal reference is defined as the solder
q
JA
mounting surface of the drain pins. R
is guaranteed by design, while R
is determined by the board design. The maximum rating
q
q
JC
JA
2
presented here is based on mounting on a 1 in pad of 2oz copper.
THERMAL CHARACTERISTICS
Symbol
Parameter
Ratings
0.26
Unit
R
Thermal Resistance, Junction to Case, Max.
_C/W
q
JC
R
Thermal Resistance, Junction to Ambient, Max. (Note 4)
40
q
JA
PACKAGE MARKING AND ORDERING INFORMATION
Part Number
Top Marking
Package
Reel Size
Tape Width
Quantity
30
FCH072N60F−F085
FCH072N60F
TO−247−3LD
−
−
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2
FCH072N60F−F085
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
C
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
OFF CHARACTERISTICS
BV
I
Drain to Source Breakdown Voltage
Drain to Source Leakage Current
V
V
V
= 0 V, I = 250 mA
600
−
−
−
−
−
10
1
V
DSS
GS
DS
DS
D
= 600 V, V = 0 V, T = 25_C
mA
mA
DSS
GS
J
= 600 V, V = 0 V, T = 150_C
−
GS
J
(Note 5)
I
Gate to Source Leakage Current
V
GS
=
20 V
−
−
100
nA
GSS
ON CHARACTERISTICS
V
r
Gate to Source Threshold Voltage
Drain to Source On Resistance
V
V
V
= V , I = 250 mA
3.0
−
4.0
62
5.0
72
V
GS(th)
GS
GS
GS
DS
D
= 10 V, I = 26 A, T = 25_C
mW
mW
DS(on)
D
J
= 10 V, I = 26 A, T = 150_C
−
154
195
D
J
(Note 5)
DYNAMIC CHARACTERISTICS
C
Input Capacitance
V
= 100 V, V = 0 V, f = 1 MHz
−
−
−
−
−
−
−
−
6330
199
1.25
0.46
160
11
−
−
pF
pF
pF
W
iss
DS
GS
C
Output Capacitance
oss
C
Reverse Transfer Capacitance
Gate Resistance
−
rss
R
f = 1 MHz
−
g
Q
Total Gate Charge
V
DD
= 380 V, I = 26 A, V = 10 V
210
16
−
nC
nC
nC
nC
g(TOT)
D
GS
Q
Threshold Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
g(th)
Q
34
gs
Q
67
−
gd
SWITCHING CHARACTERISTICS
t
Turn-On Time
Turn-On Delay Time
Rise Time
V
DD
V
GS
= 380 V, I = 26 A,
−
−
−
−
−
−
75
44
100
−
ns
ns
ns
ns
ns
ns
on
D
= 10 V, R = 4.7 W
G
t
d(on)
t
r
31
−
t
Turn-Off Delay Time
Fall Time
128
22
−
d(off)
t
f
−
t
Turn-Off Time
150
200
off
DRAIN−SOURCE DIODE CHARACTERISTICS
V
Source to Drain Diode Voltage
Reverse Recovery Time
I
= 26 A, V = 0 V
−
−
−
−
1.2
−
V
SD
SD
GS
T
I = 26 A, dI /dt = 100 A/ms
185
1515
ns
nC
rr
F
SD
V
= 480 V
DD
Q
Reverse Recovery Charge
−
rr
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. The maximum value is specified by design at T = 150°C. Product is not tested to this condition in production.
J
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3
FCH072N60F−F085
TYPICAL CHARACTERISTICS
1.2
1.0
0.8
0.6
0.4
0.2
0.0
60
50
40
30
20
10
0
V
GS
= 10 V
25
50
75
100
125
150
0
25
50
75
100
125
150
T , CASE TEMPERATURE (°C)
C
T , CASE TEMPERATURE (°C)
C
Figure 1. Normalized Power Dissipation vs. Case
Temperature
Figure 2. Maximum Continuous Drain Current
vs. Case Temperature
2
DUTY CYCLE − DESCENDING ORDER
1
D = 0.50
0.20
P
0.10
DM
0.05
0.02
0.01
t
1
0.1
t
2
NOTES:
DUTY FACTOR: D = t /t
1
2
SINGLE PULSE
PEAK T = P x Z
x R
+ T
qJC C
J
DM
qJC
0.01
−5
−4
−3
−2
−1
0
1
10
10
10
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
1000
o
VGS = 10 V
T
= 25
C
C
FOR TEMPERATURES
o
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
150 * T
I = I
2
C
Ǹ
ƪ ƫ
125
100
10
SINGLE PULSE
−5
−4
−3
−2
−1
10
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
Figure 4. Peak Current Capability
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4
FCH072N60F−F085
TYPICAL CHARACTERISTICS (continued)
150
1000
100
10
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
VDS = 20V
120
90
10 ms
100 ms
T
J = 150oC
OPERATION IN THIS
AREA MAY BE
60
30
0
T
J = 25oC
LIMITED BY R
DS(on)
1 ms
10 ms
100 ms
1
SINGLE PULSE
TJ = MAX RATED
TC = 25oC
o
TJ = −55 C
0.1
1
10
100
1000
5
6
7
8
9
3
4
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
V
GS
, GATE TO SOURCE VOLTAGE(V)
Figure 5. Forward Bias Safe Operating Area
Figure 6. Transfer Characteristics
150
200
80 ms PULSE WIDTH
VGS = 0 V
TJ = 25oC
100
10
1
VGS
15 V Top
10 V
8 V
120
90
60
30
0
7 V
6 V
TJ = 150 o
TJ = 25 o
C
5.5V
5 V
TJ = −55oC
Bottom
C
5V
0.1
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0
4
8
12
16
20
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 8. Saturation Characteristics
Figure 7. Forward Diode Characteristics
100
300
250
200
150
100
80 ms PULSE WIDTH
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
ID = 26 A
TJ = 150oC
VGS
15 V Top
10 V
8 V
80
60
40
20
0
TJ = 150oC
7 V
6 V
5.5V
5 V
Bottom
50
0
TJ = 25oC
5 V
4
5
6
7
8
9
10
0
4
8
12
16
20
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 10. RDSON vs. Gate Voltage
Figure 9. Saturation Characteristics
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5
FCH072N60F−F085
TYPICAL CHARACTERISTICS (continued)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.2
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
VGS = V
DS
I
D
= 250 mA
1.1
1.0
0.9
0.8
0.7
ID = 26 A
VGS = 10 V
0.6
0.5
−80 −40
0
40
80
120 160 200
−80 −40
0
40
80
120
160
200
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 12. Normalized Gate Threshold Voltage
vs. Temperature
Figure 11. Normalized RDSON vs. Junction
Temperature
100000
1.2
ID = 10 mA
Ciss
10000
1000
100
10
1.1
1.0
0.9
0.8
Coss
f = 1MHz
GS = 0 V
V
Crss
1
0.1
1
10
100
1000
−80 −40
0
40
80
120 160
200
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
T , JUNCTION TEMPERATURE (°C)
J
Figure 14. Capacitance vs. Drain to Source
Voltage
Figure 13. Normalized Drain to Source
Breakdown Voltage vs. Junction Temperature
28
10
ID = 26 A
VDS = 240 V
21
14
7
8
= 300 V
VDS
VDS = 360 V
6
4
2
0
0
0
100
V DRAIN TO SOURCE VOLTAGE (V)
DS,
200 300
400
500
600
0
30
60
90
120
150
180
Q
GATE CHARGE (nC)
g,
Figure 15. Gate Charge vs. Gate to Source
Voltage
Figure 16. Eoss vs. Drain to Source Voltage
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6
FCH072N60F−F085
V
GS
R
Q
g
L
V
DS
Q
Q
gs
gd
V
GS
DUT
I
G
= Const.
Charge
Figure 17. Gate Charge Test Circuit & Waveform
R
L
V
DS
GS
90%
90%
10%
90%
V
DS
V
DD
V
GS
R
G
10%
V
DUT
V
GS
t
r
t
f
t
t
d(off)
d(on)
t
on
t
off
Figure 18. Resistive Switching Test Circuit & Waveforms
L
2
1
2
EAS
+
LIAS
V
DS
BV
DSS
I
D
I
AS
R
G
V
DD
I (t)
D
DUT
V
DD
V
GS
V
DS
(t)
t
p
Time
t
p
Figure 19. Unclamped Inductive Switching Test Circuit & Waveforms
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7
FCH072N60F−F085
+
DUT
V
DS
−
I
SD
L
Driver
R
G
Same Type
as DUT
V
DD
V
GS
− dv/dt controlled by R
G
− I controlled by pulse period
SD
Gate Pulse Width
D +
Gate Pulse Period
V
GS
10 V
(Driver)
I
, Body Diode Forward Current
FM
I
di/dt
SD
(DUT)
I
RM
Body Diode Reverse Current
Body Diode Recovery dv/dt
V
DS
V
DD
V
SD
(DUT)
Body Diode
Forward Voltage Drop
Figure 20. Peak Diode Recovery dv/dt Test Circuit & Waveforms
SUPERFET is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or
other countries.
FRFET is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other
countries.
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8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−247−3LD SHORT LEAD
CASE 340CK
ISSUE A
DATE 31 JAN 2019
P1
D2
A
E
P
A
A2
Q
E2
S
D1
D
E1
B
2
2
1
3
L1
A1
b4
L
c
(3X) b
(2X) b2
M
M
B A
0.25
MILLIMETERS
MIN NOM MAX
4.58 4.70 4.82
2.20 2.40 2.60
1.40 1.50 1.60
1.17 1.26 1.35
1.53 1.65 1.77
2.42 2.54 2.66
0.51 0.61 0.71
20.32 20.57 20.82
(2X) e
DIM
A
A1
A2
b
b2
b4
c
GENERIC
D
MARKING DIAGRAM*
D1 13.08
~
~
D2
E
0.51 0.93 1.35
15.37 15.62 15.87
AYWWZZ
XXXXXXX
XXXXXXX
E1 12.81
~
~
E2
e
L
4.96 5.08 5.20
5.56
15.75 16.00 16.25
3.69 3.81 3.93
3.51 3.58 3.65
XXXX = Specific Device Code
~
~
A
Y
= Assembly Location
= Year
WW = Work Week
ZZ = Assembly Lot Code
L1
P
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
P1 6.60 6.80 7.00
Q
S
5.34 5.46 5.58
5.34 5.46 5.58
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13851G
TO−247−3LD SHORT LEAD
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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