FDB1D7N10CL7 [ONSEMI]

功率 MOSFET,N 沟道,Standard Gate,100 V,268 A,1.7 mΩ;
FDB1D7N10CL7
型号: FDB1D7N10CL7
厂家: ONSEMI    ONSEMI
描述:

功率 MOSFET,N 沟道,Standard Gate,100 V,268 A,1.7 mΩ

文件: 总8页 (文件大小:356K)
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FDB1D7N10CL7  
N-Channel Shielded Gate  
POWERTRENCH) MOSFET  
100 V, 268 A, 1.7 mW  
Description  
www.onsemi.com  
This NChannel MOSFET is produced using ON Semiconductor’s  
advanced POWERTRENCH process that incorporates Shielded Gate  
technology. This process has been optimized to minimize onstate  
resistance and yet maintain superior switching performance with best  
in class soft body diode.  
V
I
D
MAX  
r
MAX  
DS(on)  
DS  
100 V  
268 A  
1.7 mΩ  
Features  
D (Pin4, tab)  
Max R  
Max R  
Max R  
Max R  
= 1.75 mΩ at V = 10 V, I = 100 A  
DS(on)  
DS(on)  
DS(on)  
DS(on)  
GS  
D
= 1.7 mΩ at V  
= 12 V, I = 100 A  
GS  
D
= 1.65 mΩ at V  
= 4.4 mΩ at V  
= 15 V, I = 100 A  
GS  
D
= 6 V, I = 63 A  
GS  
D
G (Pin1)  
50% Lower Qrr than Other MOSFET Suppliers  
Lowers Switching Noise/EMI  
MSL1 Robust Package Design  
100% UIL Tested  
S (Pin2, 3, 5, 6, 7)  
NChannel MOSFET  
Applications  
Industrial Motor Drive  
Industrial Power Supply  
Industrial Automation  
Battery Operated Tools  
Battery Protection  
Solar Inverters  
1. Gate  
4
2. Source  
3. Source  
4. Drain  
5. Source  
6. Source  
7. Source  
1
2
3
5
6
7
D2PAK7 (TO263 7 LD)  
UPS and Energy Inverters  
Energy Storage  
CASE 418AY  
Load Switch  
MARKING DIAGRAM  
MAXIMUM RATINGS (T = 25°C, Unless otherwise specified)  
C
Symbol  
Parameter  
Drain to Source Voltage  
Gate to Source Voltage  
Drain Current  
Ratings  
100  
Unit  
V
$Y&Z&3&K  
FDB  
1D7N10CL7  
V
DS  
V
GS  
20  
V
I
D
268  
A
Continuous (T = 25°C) (Note 5)  
C
190  
Continuous (T = 100°C) (Note 5)  
C
$Y  
= ON Semiconductor Logo  
= Assembly Plant Code  
= Numeric Date Code  
= Lot Code  
1390  
595  
Pulsed (Note 4)  
&Z  
&3  
&K  
E
AS  
Single Pulsed Avalanche Energy  
(Note 3)  
mJ  
W
FDB1D7N10CL7 = Specific Device Code  
P
D
Power Dissipation  
250  
3.8  
T
C
= 25°C  
T = 25°C (Note 1a)  
A
ORDERING INFORMATION  
See detailed ordering and shipping information on page 3 of  
this data sheet.  
T , T  
Operating and Storage Temperature 55 to +175  
Range  
°C  
J
STG  
Stresses exceeding those listed in the Maximum Ratings table may damage the  
device. If any of these limits are exceeded, device functionality should not be  
assumed, damage may occur and reliability may be affected.  
© Semiconductor Components Industries, LLC, 2017  
1
Publication Order Number:  
April, 2018 Rev. 2  
FDB1D7N10CL7/D  
FDB1D7N10CL7  
THERMAL CHARACTERISTICS  
Symbol  
Parameter  
Ratings  
0.6  
Unit  
R
Thermal Resistance, Junction to Case (Note 1)  
_C/W  
q
JC  
JA  
R
Thermal Resistance, Junction to Ambient (Note 1a)  
40  
q
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)  
J
Symbol  
Parameter  
Test Conditions  
Min  
Typ  
Max  
Unit  
OFF CHARACTERISTICS  
BV  
Drain to Source Breakdown Voltage  
ID = 250 μA, VGS = 0 V  
100  
V
DSS  
DBV  
/DT  
Breakdown Voltage Temperature  
Coefficient  
ID = 250 μA, referenced to 25°C  
57  
mV/_C  
DSS  
J
I
Zero Gate Voltage Drain Current Zero  
VDS = 80 V, VGS = 0 V  
VGS = 20 V, VDS = 0 V  
1
mA  
DSS  
Gate Voltage Drain Current  
I
Gate to Source Leakage Current  
100  
nA  
GSS  
ON CHARACTERISTICS  
V
GS(th)  
Gate to Source Threshold Voltage  
VGS = VDS, ID = 700 μA  
2.0  
3.1  
4.0  
V
V
GS(th)  
/DT  
Gate to Source Threshold Voltage  
Temperature Coefficient  
ID = 700 μA, referenced to 25°C  
9  
mV/_C  
J
R
Static Drain to Source On Resistance  
VGS = 10 V, ID = 100 A  
VGS = 12 V, ID = 100 A  
VGS = 15 V, ID = 100 A  
VGS = 6 V, ID = 63 A  
1.5  
1.4  
1.75  
1.7  
1.65  
4.4  
3.1  
mW  
DS(on)  
1.33  
2.2  
VGS = 10 V, ID = 100 A, TJ= 150°C  
VDS = 5 V, ID = 100 A  
2.65  
237  
g
FS  
Forward Transconductance  
S
DYNAMIC CHARACTERISTICS  
C
Input Capacitance  
VDS = 50 V, VGS = 0 V, f = 1 MHz  
8285  
5025  
50  
11600  
7035  
80  
pF  
pF  
pF  
Ω
iss  
C
Output Capacitance  
Reverse Transfer Capacitance  
Gate Resistance  
oss  
C
rss  
R
0.1  
0.8  
1.6  
g
SWITCHING CHARACTERISTICS  
t
TurnOn Delay Time  
Rise Time  
V
V
= 50 V, I = 100 A,  
39  
33  
63  
53  
136  
58  
163  
104  
ns  
ns  
d(on)  
DD  
GS  
D
= 10 V, R  
= 6 Ω  
GEN  
t
r
t
TurnOff Delay Time  
Fall Time  
85  
ns  
d(off)  
t
f
36  
ns  
Q
Q
Total Gate Charge  
Total Gate Charge  
Gate to Source Gate Charge  
Gate to Drain “Miller” Charge  
Output Charge  
V
V
= 0 V to 10 V  
= 0 V to 6 V  
116  
74  
nC  
nC  
nC  
nC  
nC  
g
g
GS  
VDD = 50 V,  
ID = 100 A  
GS  
Q
37  
gs  
gd  
Q
24  
Q
VDD = 50 V, VGS = 0 V  
333  
oss  
SOURCE-DRAIN DIODE CHARACTERISTICS  
Continuous Drain to Source Diode Forward Current  
Pulsed Drain to Source Diode Forward Current  
I
268  
1390  
1.2  
A
A
V
S
I
SM  
V
SD  
Source to Drain Diode Forward  
Voltage  
VGS = 0 V, IS = 100 A (Note 2)  
0.9  
www.onsemi.com  
2
FDB1D7N10CL7  
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)  
J
Symbol  
Parameter  
Test Conditions  
IF = 50 A, di/dt = 300 A/μs  
IF = 50 A, di/dt = 1000 A/μs  
Min  
Typ  
Max  
Unit  
SOURCE-DRAIN DIODE CHARACTERISTICS  
t
rr  
Reverse Recovery Time  
Reverse Recovery Charge  
Reverse Recovery Time  
Reverse Recovery Charge  
63  
186  
82  
101  
298  
ns  
nC  
ns  
Q
rr  
t
rr  
132  
Q
869  
1390  
nC  
rr  
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product  
performance may not be indicated by the Electrical Characteristics if operated under different conditions.  
1. R  
is the sum of the junctiontocase and casetoambient thermal resistance where the case thermal reference is defined as the solder  
θ
JA  
mounting surface of the drain pins. R  
is guaranteed by design while R  
is determined by the user’s board design.  
θ
θ
JC  
CA  
a) 40°C/W when mounted on a 1 in2 pad of 2 oz copper.  
b) 62.5°C/W when mounted on a minimum pad of 2 oz copper.  
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0 %.  
3. E of 595 mJ is based on starting T = 25 °C, L = 0.3 mH, I = 63 A, V = 90 V, V = 10 V. 100% test at L = 0.1 mH, I = 91 A.  
AS  
J
AS  
DD  
GS  
AS  
4. Pulsed Id please refer to Figure “Forward Bias Safe Operating Area” for more details.  
5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal &  
electromechanical application board design.  
PACKAGE MARKING AND ORDERING INFORMATION  
Device Marking  
Device  
Package  
Reel Size  
Tape Width  
Quantity  
FDB1D7N10CL7  
FDB1D7N10CL7  
D2PAK7L  
330 mm  
24 mm  
800 Units  
www.onsemi.com  
3
FDB1D7N10CL7  
TYPICAL CHARACTERISTICS  
(T = 25°C unless otherwise noted)  
J
320  
280  
240  
200  
160  
120  
80  
9
8
7
PULSE DURATION = 80 ms  
DUTY CYCLE = 0.5% MAX  
VGS = 10 V  
VGS = 6.5 V  
VGS = 6 V  
V
GS = 5 V  
6
5
4
3
2
1
0
VGS = 5.5 V  
PULSE DURATION = 80 ms  
DUTY CYCLE = 0.5% MAX  
VGS = 6 V  
VGS = 5.5 V  
40  
V
GS = 5 V  
VGS = 10 V  
120 160 200 240 280 320  
VGS = 6.5 V  
0
0
1
2
3
4
5
0
40  
80  
V , Drain-Source Voltage (V)  
DS  
I , Drain Current (A)  
D
Figure 1. On-Region Characteristics  
Figure 2. Normalized OnResistance vs. Drain  
Current and Gate Voltage  
2.2  
2.0  
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
10  
PULSE DURATION = 80 ms  
DUTY CYCLE = 0.5% MAX  
ID = 100 A  
VGS = 10 V  
8
ID = 100 A  
6
4
TJ = 150 o  
C
2
0
TJ = 25 o  
C
3
6
9
12  
15  
75 50 25  
0
25 50 75 100 125 150 175  
T , Junction Temperature (5C)  
J
V , Gate to Source Voltage (V)  
GS  
Figure 3. Normalized OnResistance  
Figure 4. OnResistance vs. Gate to Source Voltage  
vs. Junction Temperature  
320  
320  
PULSE DURATION = 80 ms  
DUTY CYCLE = 0.5% MAX  
VDS = 5 V  
VGS = 0 V  
100  
280  
240  
200  
160  
120  
80  
10  
TJ = 175 o  
C
TJ = 175 o  
C
1
TJ = 25 o  
C
TJ = 25 o  
C
0.1  
TJ = 55oC  
TJ = 55 oC  
0.01  
40  
0.001  
0
2
3
4
5
6
7
0.0  
0.2  
0.4  
0.6  
0.8  
1.0  
1.2  
V , Gate to Source Voltage (V)  
GS  
V
SD  
, Body Diode Forward Voltage (V)  
Figure 5. Transfer Characteristics  
Figure 6. Source to Drain Diode  
Forward Voltage vs. Source Current  
www.onsemi.com  
4
FDB1D7N10CL7  
TYPICAL CHARACTERISTICS (Continued)  
(T = 25°C unless otherwise noted)  
J
100000  
10000  
1000  
10  
8
ID = 100 A  
VDD = 50 V  
Ciss  
Coss  
VDD = 25 V  
6
VDD = 75 V  
100  
10  
1
4
Crss  
2
f = 1 MHz  
GS = 0 V  
V
0
0.1  
1
10  
, Drain to Source Voltage (V)  
DS  
100  
0
30  
60  
90  
120  
Q , Gate Characteristics  
V
g
Figure 7. Gate Charge Characteristics  
Figure 8. Capacitance vs. Drain  
to Source Voltage  
200  
100  
300  
250  
200  
150  
100  
50  
R
qJC = 0.6 oC/W  
VGS = 10 V  
TJ = 25 o  
C
10  
VGS = 6 V  
TJ = 150 o  
C
1
0
0.001 0.01  
0.1  
1
10  
100  
1000  
25  
50  
75  
100  
125  
150  
175  
t , Time in Avalanche (ms)  
AV  
T , Case Temperature (5C)  
C
Figure 9. Unclamped Inductive Switching Capability  
Figure 10. Maximum Continuous Drain Current  
vs. Case Temperature  
20000  
10000  
100000  
SINGLE PULSE  
qJC = 0.6 oC/W  
TC = 25 oC  
R
1 ms  
1000  
100  
10  
5 ms  
10 ms  
10000  
1000  
100  
THIS AREA IS  
LIMITED BY rDS(on)  
100 ms  
SINGLE PULSE  
1 ms  
TJ = MAX RATED  
10 ms  
100 ms  
1
R
qJC = 0.6 oC/W  
CURVE BENT TO  
MEASURED DATA  
TC = 25 oC  
0.1  
105  
104  
103  
t, Pulse Width (sec)  
102  
101  
0.1  
1
10  
100  
400  
1
V , Drain to Source Voltage [V]  
DS  
Figure 11. Forward Bias Safe Operating Area  
Figure 12. Single Pulse Maximum Power Dissipation  
www.onsemi.com  
5
FDB1D7N10CL7  
TYPICAL CHARACTERISTICS (Continued)  
(T = 25°C unless otherwise noted)  
J
2
1
DUTY CYCLEDESCENDING ORDER  
D = 0.5  
0.2  
P
DM  
0.1  
0.05  
0.02  
0.01  
0.1  
t
1
t
2
Notes:  
SINGLE PULSE  
Z
R
(t) = r(t) × R  
q
JC  
0.01  
q
JC  
= 0.6°C/W  
q
JC  
Peak T = P  
× Z (t) + T
JC  
q
J
DM  
C
Duty Cycle, D = t / t  
1
2
0.001  
5  
4  
3  
2  
1  
0
10  
10  
10  
10  
10  
10  
t, Rectangular Pulse Duration (s)  
Figure 13. Normalized Max Junction to Case Transient Thermal Response Curve  
POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States  
and/or other countries.  
www.onsemi.com  
6
MECHANICAL CASE OUTLINE  
PACKAGE DIMENSIONS  
D2PAK7 (TO263 7 LD)  
CASE 418AY  
ISSUE C  
DATE 15 JUL 2019  
GENERIC  
MARKING DIAGRAM*  
XXXXXXXXX  
AYWWG  
XXXX = Specific Device Code  
A
Y
= Assembly Location  
= Year  
WW = Work Week  
G
= PbFree Package  
*This information is generic. Please refer to  
device data sheet for actual part marking.  
PbFree indicator, “G” or microdot “G”, may  
or may not be present. Some products may  
not follow the Generic Marking.  
Electronic versions are uncontrolled except when accessed directly from the Document Repository.  
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.  
DOCUMENT NUMBER:  
DESCRIPTION:  
98AON13798G  
D2PAK7 (TO263 7 LD)  
PAGE 1 OF 1  
ON Semiconductor and  
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.  
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding  
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically  
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the  
rights of others.  
© Semiconductor Components Industries, LLC, 2018  
www.onsemi.com  
onsemi,  
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates  
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.  
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/PatentMarking.pdf. onsemi reserves the right to make changes at any time to any  
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