FDB2532-F085 [ONSEMI]

N 沟道,PowerTrench® MOSFET,150V,79A,16mΩ;
FDB2532-F085
型号: FDB2532-F085
厂家: ONSEMI    ONSEMI
描述:

N 沟道,PowerTrench® MOSFET,150V,79A,16mΩ

开关 晶体管
文件: 总15页 (文件大小:1016K)
中文:  中文翻译
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DATA SHEET  
www.onsemi.com  
D
MOSFET – N-Channel,  
POWERTRENCH)  
G
150 V, 79 A, 16 mW  
S
FDB2532-F085  
Features  
DRAIN  
(FLANGE)  
R  
= 14 mW (Typ.), V = 10 V, I = 33 A  
GS D  
DS(ON)  
Q (tot) = 82 nC (Typ.), V = 10 V  
g
GS  
Low Miller Charge  
Low Q Body Diode  
GATE  
SOURCE  
RR  
UIS Capability (Single Pulse and Repetitive Pulse)  
AEC−Q101 Qualified and PPAP Capable  
D2PAK−3  
CASE 418AJ  
These Devices are Pb−Free and are RoHS Compliant  
Applications  
MARKING DIAGRAM  
DC/DC converters and Off−Line UPS  
Distributed Power Architectures and VRMs  
Primary Switch for 24 V and 48 V Systems  
High Voltage Synchronous Rectifier  
Direct Injection / Diesel Injection Systems  
42 V Automotive Load Control  
Electronic Valve Train Systems  
Synchronous Rectification  
&Z&3&K  
FDB2532  
&Z  
= Assembly Plant Code  
&3  
&K  
= Data Code (Year & Week)  
= Lot  
FDB2532  
= Specific Device Code  
ORDERING INFORMATION  
See detailed ordering and shipping information on page 2 of  
this data sheet.  
© Semiconductor Components Industries, LLC, 2010  
1
Publication Order Number:  
April, 2023 − Rev. 3  
FDB2532−F085/D  
FDB2532−F085  
MOSFET MAXIMUM RATINGS (T = 25°C, Unless otherwise noted)  
C
Symbol  
Parameter  
Value  
150  
20  
Unit  
V
V
DSS  
Drain to Source Voltage  
Gate to Source Voltage  
Drain Current  
V
GS  
V
I
D
− Continuous (T = 25°C, V = 10 V)  
79  
A
C
GS  
− Continuous (T = 100°C, V = 10 V)  
56  
C
GS  
− Continuous (T  
= 25°C, V = 10 V,  
8
A
amb  
GS  
R
q
= 43°C/W)  
JA  
I
Drain Current  
− Pulsed  
Figure 4  
400  
A
mJ  
W
D
E
AS  
Single Pulse Avalanche Energy (Note 1)  
Power Dissipation  
(T = 25°C)  
P
310  
D
C
− Derate Above 25°C  
Operating and Storage Temperature  
2.07  
W/°C  
°C  
T , T  
−55 to +175  
J
STG  
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality  
should not be assumed, damage may occur and reliability may be affected.  
1. Starting T = 25°C, L = 0.5 mH, I = 40 A  
J
AS  
THERMAL CHARACTERISTICS  
Symbol  
Parameter  
Value  
0.48  
43  
Unit  
R
Thermal Resistance Junction to Case  
Thermal Resistance Junction to Ambient, 1in Copper Pad Area  
_C/W  
_C/W  
q
JC  
JA  
2
R
q
PACKAGE MARKING AND ORDERING INFORMATION  
Device Marking  
Device  
Package  
Reel Size  
Tape Width  
24 mm  
Quantity  
800 Units  
2
FDB2532  
FDB2532−F085  
TO−263 (D −PAK−3)  
330 mm  
www.onsemi.com  
2
 
FDB2532−F085  
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)  
C
Symbol  
Parameter  
Test Conditions  
Min.  
Typ.  
Max.  
Unit  
OFF CHARACTERISTICS  
B
Drain to Source Breakdown Voltage  
Zero Gate Voltage Drain Current  
I
= 250 mA, V = 0 V  
150  
V
VDSS  
D
GS  
I
V
V
V
= 120 V, V = 0 V  
1
mA  
DSS  
DS  
DS  
GS  
GS  
= 120 V, V = 0 V, T = 150_C  
250  
100  
GS  
C
I
Gate to Source Leakage Current  
=
20 V  
nA  
GSS  
ON CHARACTERISTICS  
V
GS(TH)  
R
DS(ON)  
Gate to Source Threshold Voltage  
Drain to Source On Resistance  
V
= V , I = 250 mA  
2.0  
4.0  
V
GS  
DS  
D
I
D
I
D
I
D
= 33 A, V = 10 V  
0.014  
0.016  
0.040  
0.016  
0.024  
0.048  
W
GS  
= 16 A, V = 6 V  
GS  
= 33 A, V = 10 V, T = 175 °C  
GS  
C
DYNAMIC CHARACTERISTICS  
C
Input Capacitance  
V
= 25 V, V = 0 V, f = 1 MHz  
5870  
615  
135  
82  
pF  
pF  
pF  
nC  
iss  
DS  
GS  
C
Output Capacitance  
oss  
C
Reverse Transfer Capacitance  
Total Gate Charge at 10 V  
rss  
Q
V
GS  
V
DD  
= 0 V to 10 V,  
107  
14  
g(tot)  
= 75 V, I = 33 A, I = 1.0 mA  
D
g
Q
Threshold Gate Charge  
V
GS  
V
DD  
= 0 V to 2 V,  
11  
nC  
g(th)  
= 75 V, I = 33 A, I = 1.0 mA  
D
g
Q
Gate to Source Gate Charge  
Gate Charge Threshold to Plateau  
Gate to Drain “Miller” Charge  
V
DD  
= 75 V, I = 33 A, I = 1.0 mA  
23  
13  
19  
nC  
nC  
nC  
gs  
D
g
Q
gs2  
Q
gd  
RESISTIVE SWITCHING CHARACTERISTICS (V = 10 V)  
GS  
t
Turn-On Time  
Turn-On Delay Time  
Rise Time  
V
DD  
V
GS  
= 75 V, I = 33 A,  
69  
84  
ns  
ns  
ns  
ns  
ns  
ns  
ON  
D
= 10 V, R = 3.6 W  
GS  
t
16  
30  
39  
17  
d(ON)  
t
r
t
Turn-Off Delay Time  
Fall Time  
d(OFF)  
t
f
t
Turn-Off Time  
OFF  
DRAIN−SOURCE DIODE CHARACTERISTICS  
V
Source to Drain Diode Voltage  
I
I
I
I
= 33 A  
= 16 A  
1.25  
1
V
V
SD  
SD  
SD  
SD  
SD  
t
Reverse Recovery Time  
= 33 A, dl /dt = 100 A/ms  
105  
327  
ns  
nC  
rr  
SD  
Q
Reverse Recovery Charge  
= 33 A, dl /dt = 100 A/ms  
SD  
RR  
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product  
performance may not be indicated by the Electrical Characteristics if operated under different conditions.  
1. Pulse Width = 100 s  
www.onsemi.com  
3
FDB2532−F085  
TYPICAL CHARACTERISTICS  
T
C
= 25°C UNLESS OTHERWISE NOTED  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0
125  
V
= 10V  
GS  
100  
75  
50  
25  
0
150  
0
25  
50  
75  
100  
175  
125  
o
25  
50  
75  
T , CASE TEMPERATURE ( C)  
C
100  
125  
150  
175  
o
T
, CASE TEMPERATURE ( C)  
C
Figure 1. Normalized Power  
Figure 2. Maximum Continuous  
Dissipation vs. Ambient Temperature  
Drain Current vs Case Temperature  
2.0  
DUTY CYCLE − DESCENDING ORDER  
0.5  
0.2  
0.1  
1.0  
0.05  
0.02  
0.01  
P
DM  
0.1  
t
1
t
2
NOTES:  
DUTY FACTOR : D = t /t  
SINGLE PULSE  
1
2
PEAK T = P  
x Z  
Q
x R  
Q
+ T  
JC C  
J
DM  
JC  
0.01  
−5  
−4  
−3  
−2  
0
1
10  
10  
10  
10  
10−1  
10  
10  
t, RECTANGULAR PULSE DURATION (s)  
Figure 3. Normalized Maximum Transient Thermal Impedance  
2000  
1000  
o
T
= 25 C  
C
FOR TEMPERATURES  
o
TRANSCONDUCTANCE  
MAY LIMIT CURRENT  
IN THIS REGION  
ABOVE 25 C DERATE PEAK  
CURRENT AS FOLLOWS:  
175 − T  
C
I = I  
25  
150  
V
= 10V  
GS  
100  
50  
−5  
−4  
−3  
−2  
−1  
0
1
10  
10  
10  
10  
10  
10  
10  
t, PULSE WIDTH (s)  
Figure 4. Peak Current Capability  
www.onsemi.com  
4
FDB2532−F085  
TYPICAL CHARACTERISTICS (CONTINUED)  
T
C
= 25°C UNLESS OTHERWISE NOTED  
NOTE: Refer to onsemi Application Notes AN−7515 and  
AN−7517  
1000  
100  
10  
200  
10 ms  
o
STARTING T = 25 C  
J
100  
100 ms  
o
OPERATION IN THIS  
AREA MAY BE  
1ms  
STARTING T = 150 C  
J
10  
LIMITED BY r  
DS(ON)  
10ms  
DC  
1
If R = 0  
= (L)(I )/(1.3*RATED BV  
If R p ꢀ  
SINGLE PULSE  
t
AV  
− V  
DD  
)
AS  
DSS  
T
= MAX RATED  
J
o
T
= 25 C  
t
= (L/R)ln[(I *R)/(1.3*RATED BV  
− V ) +1]  
DD  
DSS  
C
AV  
AS  
0.1  
1
1
10  
, DRAIN TO SOURCE VOLTAGE (V)  
100  
300  
0.001  
0.01  
0.1  
1
V
t
DS  
, TIME IN AVALANCHE (ms)  
AV  
Figure 5. Forward Bias Safe Operating Area  
Figure 6. Unclamped Inductive Switching  
Capability  
180  
180  
150  
120  
90  
PULSE DURATION = 80 ms  
V
= 7V  
GS  
V
= 10V  
GS  
DUTY CYCLE = 0.5% MAX  
V
150  
120  
90  
60  
30  
0
= 15V  
DD  
V
= 6V  
GS  
o
T
= 175 C  
J
o
T
= 25 C  
C
60  
V
= 5V  
GS  
o
o
T
J
= 25 C  
T
= −55 C  
J
30  
PULSE DURATION = 80 ms  
DUTY CYCLE = 0.5% MAX  
0
0.0  
1.0  
2.0  
3.0  
4.0  
5.0  
6.0  
3.0  
3.5  
4.0  
4.5  
5.0  
5.5  
6.0  
6.5  
V
, DRAIN TO SOURCE VOLTAGE (V)  
DS  
V
, GATE TO SOURCE VOLTAGE (V)  
GS  
Figure 7. Transfer Characteristics  
Figure 8. Saturation Characteristics  
18  
17  
16  
15  
14  
13  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
PULSE DURATION = 80 ms  
DUTY CYCLE = 0.5% MAX  
PULSE DURATION = 80 ms  
DUTY CYCLE = 0.5% MAX  
V
= 6V  
GS  
V
= 10V  
GS  
V
= 10V, I =33A  
D
GS  
0
20  
40  
60  
80  
−80  
−40  
0
40  
80  
120  
o
160  
200  
I , DRAIN CURRENT (A)  
D
T , JUNCTION TEMPERATURE ( C)  
J
Figure 9. Drain to Source On Resistance  
vs Drain Current  
Figure 10. Normalized Drain to Source On  
Resistance vs Junction Temperature  
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5
FDB2532−F085  
TYPICAL CHARACTERISTICS (CONTINUED)  
T
C
= 25°C UNLESS OTHERWISE NOTED  
1.2  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
I
= 250 mA  
V
= V , I = 250 mA  
DS D  
D
GS  
1.1  
1.0  
0.9  
−80  
−40  
0
40  
80  
120  
160  
200  
−80  
−40  
0
40  
80  
120  
160  
200  
o
o
T , JUNCTION TEMPERATURE ( C)  
T , JUNCTION TEMPERATURE ( C)  
J
J
Figure 11. Normalized Gate Threshold Voltage  
vs. Junction Temperature  
Figure 12. Normalized Drain to Source  
Breakdown Voltage vs Junction Temperature  
10000  
10  
8
V
= 75V  
DD  
C
C
+ C  
GS GD  
ISS  
C
@
C
+ C  
OSS  
DS GD  
6
1000  
C
C  
GD  
RSS  
4
WAVEFORMS IN  
DESCENDING ORDER:  
2
I
I
= 33A  
= 16A  
100  
50  
D
D
V
= 0V, f = 1MHz  
1
GS  
0
0.1  
10  
150  
0
20  
40  
60  
80  
100  
V
, DRAIN TO SOURCE VOLTAGE (V)  
Q , GATE CHARGE (nC)  
DS  
g
Figure 13. Capacitance vs. Drain to Source  
Voltage  
Figure 14. Gate Charge Waveforms for  
Constant Gate Currents  
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6
FDB2532−F085  
TEST CIRCUITS WAVEFORMS  
V
DS  
L
VARY tp TO OBTAIN  
REQUIRED PEAK I  
AS  
R
G
+
V
DD  
DUT  
V
GS  
tp  
0 V  
I
AS  
0.01 W  
Figure 15. Unclamped Energy  
Test Circuit  
Figure 16. Unclamped Energy  
Waveforms  
V
DS  
L
V
GS  
+
V
DD  
DUT  
I
g(REF)  
Figure 17. Gate Charge Test Circuit  
Figure 18. Gate Charge Waveforms  
V
DS  
R
L
+
V
GS  
V
DD  
DUT  
R
GS  
V
GS  
Figure 19. Switching Time Test Circuit  
Figure 20. Switching Time Waveforms  
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7
FDB2532−F085  
THERMAL RESISTANCE VS. MOUNTING PAD  
AREA  
onsemi provides thermal information to assist the  
designer’s preliminary application evaluation. Figure 21  
The maximum rated junction temperature, T , and the  
defines the R  
for the device as a function of the top copper  
JM  
JA  
q
thermal resistance of the heat dissipating path determines  
(component side) area. This is for a horizontally positioned  
FR−4 board with 1oz copper after 1 000 seconds of steady  
state power with no air flow. This graph provides the  
necessary information for calculation of the steady state  
junction temperature or power dissipation. Pulse  
applications can be evaluated using the onsemi device Spice  
thermal model or manually utilizing the normalized  
maximum transient thermal impedance curve.  
Thermal resistances corresponding to other copper areas  
can be obtained from Figure 21 or by calculation using  
Equation 2 or 3. Equation 2 is used for copper area defined  
in inches square and equation 3 is for area in centimeter  
square. The area, in square inches or square centimeters is  
the top copper area including the gate and source pads.  
the maximum allowable device power dissipation, P , in  
DM  
an application. Therefore the application’s ambient  
temperature, T (°C), and thermal resistance R  
(°C/W)  
qJA  
A
must be reviewed to ensure that T is never exceeded.  
JM  
Equation 1 mathematically represents the relationship and  
serves as the basis for establishing the rating of the part.  
(TJM * TA)  
+
(eq. 1)  
PDM  
RQJA  
In using surface mount devices such as the TO−263  
2
(D −PAK−3) package, the environment in which it is applied  
will have a significant influence on the part’s current and  
maximum power dissipation ratings. Precise determination  
of P  
is complex and influenced by many factors:  
DM  
19.84  
(0.262 ) Area)  
1. Mounting pad area onto which the device is  
attached and whether there is copper on one side  
or both sides of the board.  
2. The number of copper layers and the thickness of  
the board.  
RQJA + 26.51 )  
Area in Inches Squared.  
RQJA + 26.51 )  
(eq. 2)  
128  
(1.69 ) Area)  
(eq. 3)  
Area in Centimeters Squared.  
3. The use of external heat sinks.  
4. The use of thermal vias.  
5. Air flow and board orientation.  
6. For non steady state applications, the pulse width,  
the duty cycle and the transient thermal response  
of the part, the board and the environment they  
are in.  
80  
60  
40  
R
= 26.51+ 19.84/(0.262+Area) EQ.2  
QJA  
R
= 26.51+ 128/(1.69+Area) EQ.3  
QJA  
20  
0.1  
1
10  
(0.645)  
(6.45)  
(64.5)  
2
2
AREA, TOP COPPER AREA in (cm )  
Figure 21. Thermal Resistance vs. Mounting Pad Area  
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8
 
FDB2532−F085  
PSPICE ELECTRICAL MODEL  
.SUBCKT FDB2532 2 1 3 ; rev April 2002  
CA 12 8 1.4e−9  
CB 15 14 1.6e−9  
CIN 6 8 5.61e−9  
Dbody 7 5 DbodyMOD  
Dbreak 5 11 DbreakMOD  
Dplcap 10 5 DplcapMOD  
Ebreak 11 7 17 18 159  
Eds 14 8 5 8 1  
Egs 13 8 6 8 1  
Esg 6 10 6 8 1  
Evthres 6 21 19 8 1  
Evtemp 20 6 18 22 1  
It 8 17 1  
Lgate 1 9 9.56e−9  
Ldrain 2 5 1.0e−9  
Lsource 3 7 7.71e−9  
RLgate 1 9 95.6  
RLdrain 2 5 10  
RLsource 3 7 77.1  
Mmed 16 6 8 8 MmedMOD  
Mstro 16 6 8 8 MstroMOD  
Mweak 16 21 8 8 MweakMOD  
Rbreak 17 18 RbreakMOD 1  
Rdrain 50 16 RdrainMOD 9.6e−3  
Rgate 9 20 1.01  
RSLC1 5 51 RSLCMOD 1.0e−6  
RSLC2 5 50 1.0e3  
Rsource 8 7 RsourceMOD 3.0e−3  
Rvthres 22 8 RvthresMOD 1  
Rvtemp 18 19 RvtempMOD 1  
S1a 6 12 13 8 S1AMOD  
S1b 13 12 13 8 S1BMOD  
S2a 6 15 14 13 S2AMOD  
S2b 13 15 14 13 S2BMOD  
Vbat 22 19 DC 1  
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e−6*190),3))}  
.MODEL DbodyMOD D (IS=6.0E−11 N=1.09 RS=2.3e−3 TRS1=3.0e−3 TRS2=1.0e−6  
+ CJO=3.9e−9 M=0.65 TT=4.8e−8 XTI=4.2)  
.MODEL DbreakMOD D (RS=0.17 TRS1=3.0e−3 TRS2=−8.9e−6)  
.MODEL DplcapMOD D (CJO=1.0e−9 IS=1.0e−30 N=10 M=0.6)  
.MODEL MmedMOD NMOS (VTO=3.55 KP=10 IS=1e−30 N=10 TOX=1 L=1u W=1u RG=1.01)  
.MODEL MstroMOD NMOS (VTO=4.2 KP=145 IS=1e−30 N=10 TOX=1 L=1u W=1u)  
.MODEL MweakMOD NMOS (VTO=2.9 KP=0.05 IS=1e−30 N=10 TOX=1 L=1u W=1u RG=10.1 RS=0.1)  
.MODEL RbreakMOD RES (TC1=1.1e−3 TC2=−9.0e−7)  
.MODEL RdrainMOD RES (TC1=9.0e−3 TC2=3.5e−5)  
.MODEL RSLCMOD RES (TC1=3.4e−3 TC2=1.5e−6)  
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9
FDB2532−F085  
.MODEL RsourceMOD RES (TC1=4.0e−3 TC2=1.0e−6)  
.MODEL RvthresMOD RES (TC1=−4.1e−3 TC2=−1.4e−5)  
.MODEL RvtempMOD RES (TC1=−4.0e−3 TC2=3.5e−6)  
.MODEL S1AMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−6.0 VOFF=−4.0)  
.MODEL S1BMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−4.0 VOFF=−6.0)  
.MODEL S2AMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−1.4 VOFF=1.0)  
.MODEL S2BMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=1.0 VOFF=−1.4)  
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub−Circuit for the Power MOSFET  
Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by  
William J. Hepp and C. Frank Wheatley.  
Figure 22. PSPICE Electrical Model  
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10  
FDB2532−F085  
SABER ELECTRICAL MODEL  
REV April 2002  
ttemplate FDB2532 n2,n1,n3  
electrical n2,n1,n3  
{
var i iscl  
dp..model dbodymod = (isl=6.0e−11,nl=1.09,rs=2.3e−3,trs1=3.0e−3,trs2=1.0e−6,cjo=3.9e−9,m=0.65,tt=4.8e−8,xti=4.2)  
dp..model dbreakmod = (rs=0.17,trs1=3.0e−3,trs2=−8.9e−6)  
dp..model dplcapmod = (cjo=1.0e−9,isl=10.0e−30,nl=10,m=0.6)  
m..model mmedmod = (type=_n,vto=3.55,kp=10,is=1e−30, tox=1)  
m..model mstrongmod = (type=_n,vto=4.2,kp=145,is=1e−30, tox=1)  
m..model mweakmod = (type=_n,vto=2.9,kp=0.05,is=1e−30, tox=1,rs=0.1)  
sw_vcsp..model s1amod = (ron=1e−5,roff=0.1,von=−6.0,voff=−4.0)  
sw_vcsp..model s1bmod = (ron=1e−5,roff=0.1,von=−4.0,voff=−6.0)  
sw_vcsp..model s2amod = (ron=1e−5,roff=0.1,von=−1.4,voff=1.0)  
sw_vcsp..model s2bmod = (ron=1e−5,roff=0.1,von=1.0,voff=−1.4)  
c.ca n12 n8 = 1.4e−9  
c.cb n15 n14 = 1.6e−9  
c.cin n6 n8 = 5.61e−9  
dp.dbody n7 n5 = model=dbodymod  
dp.dbreak n5 n11 = model=dbreakmod  
dp.dplcap n10 n5 = model=dplcapmod  
spe.ebreak n11 n7 n17 n18 = 159  
spe.eds n14 n8 n5 n8 = 1  
spe.egs n13 n8 n6 n8 = 1  
spe.esg n6 n10 n6 n8 = 1  
spe.evthres n6 n21 n19 n8 = 1  
spe.evtemp n20 n6 n18 n22 = 1  
i.it n8 n17 = 1  
l.lgate n1 n9 = 9.56e−9  
l.ldrain n2 n5 = 1.0e−9  
l.lsource n3 n7 = 7.71e−9  
res.rlgate n1 n9 = 95.6  
res.rldrain n2 n5 = 10  
res.rlsource n3 n7 = 77.1  
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u  
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u  
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u  
res.rbreak n17 n18 = 1, tc1=1.1e−3,tc2=−9.0e−7  
res.rdrain n50 n16 = 9.6e−3, tc1=9.0e−3,tc2=3.5e−5  
res.rgate n9 n20 = 1.01  
res.rslc1 n5 n51 = 1.0e−6, tc1=3.4e−3,tc2=1.5e−6  
res.rslc2 n5 n50 = 1.0e3  
res.rsource n8 n7 = 3.0e−3, tc1=4.0e−3,tc2=1.0e−6  
res.rvthres n22 n8 = 1, tc1=−4.1e−3,tc2=−1.4e−5  
res.rvtemp n18 n19 = 1, tc1=−4.0e−3,tc2=3.5e−6  
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod  
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod  
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod  
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod  
www.onsemi.com  
11  
FDB2532−F085  
v.vbat n22 n19 = dc=1  
equations {  
i (n51−>n50) +=iscl  
iscl: v(n51,n50) = ((v(n5,n51)/(1e−9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/190))** 3))  
}
}
Figure 23. SABER Electrical Model  
www.onsemi.com  
12  
FDB2532−F085  
SPICE THERMAL MODEL  
th  
JUNCTION  
REV 26 February 2002  
FDB2532  
CTHERM1 TH 6 7.5e−3  
CTHERM2 6 5 8.0e−3  
CTHERM3 5 4 9.0e−3  
CTHERM4 4 3 2.4e−2  
CTHERM5 3 2 3.4e−2  
CTHERM6 2 TL 6.5e−2  
CTHERM1  
RTHERM1  
6
RTHERM1 TH 6 3.1e−4  
RTHERM2 6 5 2.5e−3  
RTHERM3 5 4 2.0e−2  
RTHERM4 4 3 8.0e−2  
RTHERM5 3 2 1.2e−1  
RTHERM6 2 TL 1.3e−1  
CTHERM2  
CTHERM3  
CTHERM4  
RTHERM2  
5
SABER THERMAL MODEL  
SABER thermal model FDB2532  
template thermal_model th tl  
thermal_c th, tl  
RTHERM3  
{
4
3
2
ctherm.ctherm1 th 6 =7.5e−3  
ctherm.ctherm2 6 5 =8.0e−3  
ctherm.ctherm3 5 4 =9.0e−3  
ctherm.ctherm4 4 3 =2.4e−2  
ctherm.ctherm5 3 2 =3.4e−2  
ctherm.ctherm6 2 tl =6.5e−2  
RTHERM4  
rrtherm.rtherm1 th 6 =3.1e−4  
rtherm.rtherm2 6 5 =2.5e−3  
rtherm.rtherm3 5 4 =2.0e−2  
rtherm.rtherm4 4 3 =8.0e−2  
rtherm.rtherm5 3 2 =1.2e−1  
rtherm.rtherm6 2 tl =1.3e−1  
}
CTHERM5  
RTHERM5  
CTHERM6  
RTHERM6  
tl  
CASE  
Figure 24. Thermal Model  
POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United  
States and/or other countries.  
www.onsemi.com  
13  
MECHANICAL CASE OUTLINE  
PACKAGE DIMENSIONS  
D2PAK3 (TO263, 3LEAD)  
CASE 418AJ  
ISSUE F  
DATE 11 MAR 2021  
SCALE 1:1  
XXXXXX = Specific Device Code  
A
= Assembly Location  
WL  
Y
= Wafer Lot  
= Year  
GENERIC MARKING DIAGRAMS*  
WW  
W
M
G
AKA  
= Work Week  
= Week Code (SSG)  
= Month Code (SSG)  
= PbFree Package  
= Polarity Indicator  
XX  
AYWW  
XXXXXXXXG  
AKA  
XXXXXXXXG  
AYWW  
XXXXXX  
XXYMW  
XXXXXXXXX  
AWLYWWG  
*This information is generic. Please refer to  
device data sheet for actual part marking.  
PbFree indicator, “G” or microdot “ G”,  
may or may not be present. Some products  
may not follow the Generic Marking.  
IC  
Standard  
Rectifier  
SSG  
Electronic versions are uncontrolled except when accessed directly from the Document Repository.  
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.  
DOCUMENT NUMBER:  
98AON56370E  
D2PAK3 (TO263, 3LEAD)  
PAGE 1 OF 1  
DESCRIPTION:  
ON Semiconductor and  
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.  
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding  
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically  
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the  
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© Semiconductor Components Industries, LLC, 2018  
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onsemi,  
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