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FDB2532 [ONSEMI]

N 沟道 PowerTrench® MOSFET，150V，79A，16mΩ;
FDB2532
型号： FDB2532
厂家： ONSEMI    ONSEMI
描述：

N 沟道 PowerTrench® MOSFET，150V，79A，16mΩ
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DATA SHEET  
www.onsemi.com  
MOSFET – N-Channel,  
POWERTRENCH)  
V
R
MAX  
I MAX  
D
DS  
DS(on)  
150 V  
16 mW @ 10 V  
79 A  
150 V, 79 A, 16 mW  
FDP2532, FDB2532  
TO−220−3LD  
CASE 340AT  
G
Features  
D
S
• R  
• Q  
= 14 mW (Typ.) @ V = 10 V, I = 33 A  
GS D  
DS(on)  
G(tot)  
D
D2PAK−3  
= 82 nC (Typ.) @ V = 10 V  
GS  
(TO−263, 3−LEAD)  
CASE 418AJ  
• Low Miller Charge  
G
S
• Low Q Body Diode  
rr  
• UIS Capability (Single Pulse and Repetitive Pulse)  
• These Devices are Pb−Free, Halide Free and are RoHS Compliant  
MARKING DIAGRAM  
Applications  
• Consumer Appliances  
&Z&3&K  
FDx2532  
• Synchronous Rectification  
• Battery Protection Circuit  
• Motor Drives and Uninterruptible Power Supplies  
• Micro Solar Inverter  
&Z  
&3  
&K  
= Assembly Plant Code  
= 3−Digit Date Code  
= 2−Digits Lot Run Traceability Code  
FDx2532 = Device Code (x = P, B)  
MOSFET MAXIMUM RATINGS (T = 25°C, unless otherwise noted)  
C
FDP2532 /  
FDB2532  
Symbol  
Parameter  
Drain to Source Voltage  
Gate to Source Voltage  
Unit  
V
D
V
DSS  
150  
V
GS  
+20  
V
I
Drain Current  
A
D
Continuous (T = 25°C, V = 10 V)  
79  
56  
8
C
GS  
Continuous (T = 100°C, V = 10 V)  
C
GS  
G
Continuous (T  
= 25°C, V = 10 V,  
amb  
GS  
= 43°C/W)  
R
q
JA  
Pulsed  
Figure 4  
400  
S
E
AS  
Single Pulse Avalanche Energy (Note 1)  
Power Dissipation  
mJ  
W
N−Channel  
P
310  
D
Derate above 25°C  
2.07  
W/°C  
T , T  
Operating and Storage Temperature  
−55 to 175  
°
C
J
STG  
ORDERING INFORMATION  
See detailed ordering and shipping information on page 12 of  
this data sheet.  
Stresses exceeding those listed in the Maximum Ratings table may damage the  
device. If any of these limits are exceeded, device functionality should not be  
assumed, damage may occur and reliability may be affected.  
THERMAL CHARACTERISTICS (T = 25°C, unless otherwise noted)  
C
FDP2532 /  
FDB2532  
Symbol  
Parameter  
Unit  
R
Thermal Resistance Junction to Case,  
Max. TO−220, D −PAK  
0.61  
°C/W  
q
JC  
2
R
Thermal Resistance Junction to Ambient,  
Max. TO−220, D2−PAK (Note 2)  
62  
43  
q
JA  
JA  
R
Thermal Resistance Junction to Ambient  
°C/W  
q
2
2
D −PAK, Max. 1 in Copper Pad Area  
© Semiconductor Components Industries, LLC, 2002  
1
Publication Order Number:  
April, 2023 − Rev. 4  
FDP2532/D  
FDP2532, FDB2532  
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)  
C
Symbol  
Parameter  
Test Condition  
Min  
Typ  
Max  
Unit  
OFF CHARACTERISTICS  
B
Drain to Source Breakdown Voltage  
Zero Gate Voltage Drain Current  
I
= 250 mA, V = 0 V  
150  
−
−
−
−
−
−
V
VDSS  
D
GS  
I
V
V
V
= 120 V, V = 0 V  
1
mA  
DSS  
DS  
DS  
GS  
GS  
= 120 V, V = 0 V, T = 150°C  
−
250  
100  
GS  
C
I
Gate to Source Leakage Current  
=
20 V  
−
nA  
GSS  
ON CHARACTERISTICS  
V
Gate to Source Threshold Voltage  
Drain to Source On Resistance  
V
= V , I = 250 mA  
2
−
−
−
−
4
V
GS(TH)  
GS  
DS D  
R
I
D
I
D
I
D
= 33 A, V = 10 V  
0.014  
0.016  
0.040  
0.016  
0.024  
0.048  
W
DS(on)  
GS  
= 16 A, V = 6 V  
GS  
= 33 A, V = 10 V, T = 175°C  
GS  
C
DYNAMIC CHARACTERISTICS  
C
Input Capacitance  
V
= 25 V, V = 0 V, f = 1 MHz  
−
−
−
−
5870  
615  
135  
82  
−
−
pF  
pF  
pF  
nC  
ISS  
DS  
GS  
C
OSS  
C
RSS  
Output Capacitance  
Reverse Transfer Capacitance  
Total Gate Charge at 10 V  
−
Q
g(TOT)  
V
GS  
= 0 V to 10 V, V = 75 V, I = 33 A,  
107  
DD  
D
I = 1.0 mA  
g
Q
g(TH)  
Threshold Gate Charge  
V
= 0 V to 2 V, V = 75 V, I = 33 A,  
−
11  
14  
nC  
GS  
DD  
D
I = 1.0 mA  
g
Q
Gate to Source Gate Charge  
Gate Charge Threshold to Plateau  
Gate to Drain “Miller” Charge  
V
DD  
= 75 V, I = 33 A, I = 1.0 mA  
−
−
−
23  
13  
19  
−
−
−
nC  
nC  
nC  
gs  
D
g
Q
gs2  
Q
gd  
SWITCHING CHARACTERISTICS (V = 10 V)  
GS  
t
Turn−On Time  
Turn−On Delay Time  
Rise Time  
V
R
= 75 V, I = 33 A, V = 10 V,  
= 3.6 W  
−
−
−
−
−
−
−
69  
−
ns  
ns  
ns  
ns  
ns  
ns  
ON  
DD  
D
GS  
GS  
t
16  
30  
39  
17  
−
d(ON)  
t
r
−
t
Turn−Off Delay Time  
Fall Time  
−
d(OFF)  
t
f
−
t
Turn−Off Time  
84  
OFF  
DRAIN−SOURCE CHARACTERISTICS  
V
Source to Drain Diode Voltage  
I
I
I
I
= 33 A  
= 16 A  
−
−
−
−
−
−
−
−
1.25  
1.0  
V
V
SD  
SD  
SD  
SD  
SD  
t
Reverse Recovery Time  
= 33 A, dI /dt = 100 A/ms  
105  
327  
ns  
nC  
rr  
SD  
Q
Reverse Recovery Charge  
= 33 A, dI /dt = 100 A/ms  
SD  
RR  
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product  
performance may not be indicated by the Electrical Characteristics if operated under different conditions.  
1. Starting T = 25°C, L = 0.5 mH, IAS = 40 A.  
J
2. Pulse Width = 100 s.  
www.onsemi.com  
2
FDP2532, FDB2532  
TYPICAL CHARACTERISTICS (T = 25°C, unless otherwise noted)  
C
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0
125  
V
GS  
= 10 V  
100  
75  
50  
25  
0
0
25  
50  
75  
100  
125  
150  
175  
25  
50  
75  
100  
125  
150  
175  
T , CASE TEMPERATURE (°C)  
C
T , CASE TEMPERATURE (°C)  
C
Figure 1. Normalized Power Dissipation vs.  
Ambient Temperature  
Figure 2. Maximum Continuous Drain Current vs.  
Case Temperature  
2.0  
DUTY CYCLE − DESCENDING ORDER  
0.5  
1.0  
0.2  
0.1  
0.05  
0.02  
0.01  
P
DM  
0.1  
t
1
t
2
NOTES:  
DUTY FACTOR: D = t / t  
SINGLE PULSE  
1
2
PEAK T = P  
x Z  
x R  
+ T  
JC C  
q
q
J
DM  
JC  
0.01  
10−5  
10−4  
10−3  
10−2  
100  
101  
10−1  
t, RECTANGULAR PULSE DURATION (s)  
Figure 3. Normalized Maximum Transient Thermal Impedance  
2000  
T = 25°C  
A
TRANSCONDUCTANCE  
MAY LIMIT CURRENT  
IN THIS REGION  
FOR TEMPERATURES  
ABOVE 25°C DERATE PEAK  
CURRENT AS FOLLOWS:  
1000  
175 * TC  
Ǹ
I + I25ƪ ƫ  
125  
100  
50  
10−5  
10−4  
10−3  
10−2  
10−1  
100  
101  
t, PULSE WIDTH (s)  
Figure 4. Peak Current Capability  
www.onsemi.com  
3
FDP2532, FDB2532  
TYPICAL CHARACTERISTICS (T = 25°C, unless otherwise noted) (continued)  
C
1000  
100  
10  
200  
10 ms  
STARTING T = 25°C  
J
100  
100 ms  
1 ms  
OPERATION IN THIS  
AREA MAY BE  
LIMITED BY R  
STARTING T = 150°C  
J
10  
10 ms  
DC  
DS(on)  
If R = 0  
= (L) (I ) / (1.3 x RATED BV  
1
SINGLE PULSE  
T = MAX RATED  
t
− V )  
DD  
AV  
AS  
DSS  
J
If R ≠ 0  
T
C
= 25°C  
tAV = (L / R) ln [(I x R) / (1.3 x RATED BVDSS − V ) +1]  
AS  
DD  
0.1  
1
1
10  
100 300  
0.001  
0.01  
0.1  
1
V
DS  
, DRAIN TO SOURCE VOLTAGE (V)  
t , TIME IN AVALANCHE (ms)  
AV  
NOTE: Refer to onsemi Application Notes AN7515 and AN7517  
Figure 5. Forward Bias Safe Operating Area  
Figure 6. Unclamped Inductive Switching Capability  
180  
180  
V
GS  
= 10 V  
V
GS  
= 7 V  
PULSE DURATION = 80 ms  
DUTY CYCLE = 0.5% MAX  
150  
120  
90  
60  
30  
0
150  
V
DD  
= 15 V  
V
GS  
= 6 V  
120  
90  
60  
30  
0
T = 175°C  
J
T = 25°C  
J
V
GS  
= 5 V  
T = 25°C  
J
T = −55°C  
J
PULSE DURATION = 80 ms  
DUTY CYCLE = 0.5% MAX  
3.0  
3.5  
4.0  
4.5  
5.0  
5.5  
6.0  
6.5  
0.0  
1.0  
2.0  
3.0  
4.0  
5.0  
6.0  
V
GS  
, GATE TO SOURCE VOLTAGE (V)  
V
DS  
, DRAIN TO SOURCE VOLTAGE (V)  
Figure 7. Transfer Characteristics  
Figure 8. Saturation Characteristics  
18  
17  
16  
15  
14  
13  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
PULSE DURATION = 80 ms  
DUTY CYCLE = 0.5% MAX  
PULSE DURATION = 80 ms  
DUTY CYCLE = 0.5% MAX  
V
GS  
= 6 V  
V
GS  
= 10 V  
V
= 10 V, I = 33 A  
GS  
D
0
20  
40  
60  
80  
−80  
−40  
0
40  
80  
120  
160  
200  
I , DRAIN CURRENT (A)  
D
T , JUNCTION TEMPERATURE (°C)  
J
Figure 9. Drain to Source On Resistance vs.  
Drain Current  
Figure 10. Normalized Drain to Source On Resistance  
vs. Junction Temperature  
www.onsemi.com  
4
FDP2532, FDB2532  
TYPICAL CHARACTERISTICS (T = 25°C, unless otherwise noted) (continued)  
C
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
1.2  
V
= V , I = 250 mA  
I = 250 mA  
D
GS  
DS  
D
1.1  
1.0  
0.9  
−80  
−40  
0
40  
80  
120  
160  
200  
−80  
−40  
0
40  
80  
120  
160  
200  
T , JUNCTION TEMPERATURE (°C)  
J
T , JUNCTION TEMPERATURE (°C)  
J
Figure 11. Normalized Gate Threshold Voltage vs.  
Junction Temperature  
Figure 12. Normalized Drain to Source Breakdown  
Voltage vs. Junction Temperature  
10000  
10  
V
DD  
= 75 V  
C
= C + C  
GS GD  
ISS  
8
6
4
2
0
C
≅ C + C  
DS GD  
OSS  
1000  
C
= C  
GD  
RSS  
WAVEFORMS IN  
DESCENDING ORDER:  
100  
50  
I
D
I
D
= 33 A  
= 16 A  
V
= 0 V, f = 1 MHz  
1
GS  
0.1  
10  
150  
0
20  
40  
60  
80  
100  
V
DS  
, DRAIN TO SOURCE VOLTAGE (V)  
Q , GATE CHARGE (nC)  
g
Figure 13. Capacitance vs. Drain to Source Voltage  
Figure 14. Gate Charge Waveforms for Constant  
Gate Currents  
www.onsemi.com  
5
FDP2532, FDB2532  
TEST CIRCUITS AND WAVEFORMS  
V
BV  
DS  
DSS  
t
P
V
DS  
L
I
AS  
V
DD  
VARY t TO OBTAIN  
P
+
R
REQUIRED PEAK I  
G
AS  
V
DD  
−
V
GS  
DUT  
t
P
I
0 V  
AS  
0
0.01 W  
t
AV  
Figure 15. Unclamped Energy Test Circuit  
Figure 16. Unclamped Energy Waveforms  
V
DS  
V
Q
DD  
g(TOT)  
V
DS  
V
GS  
L
V
= 10 V  
GS  
V
GS  
+
Q
gs2  
V
DD  
−
DUT  
V
= 2 V  
GS  
0
I
g(REF)  
Q
g(TH)  
Q
Q
gs  
gd  
I
g(REF)  
0
Figure 17. Gate Charge Test Circuit  
Figure 18. Gate Charge Waveforms  
t
t
V
ON  
OFF  
t
d(OFF)  
DS  
t
d(ON)  
t
t
f
r
R
L
V
DS  
90%  
90%  
+
V
GS  
V
DD  
10%  
10%  
0
−
90%  
50%  
DUT  
R
GS  
V
GS  
50%  
PULSE WIDTH  
10%  
V
GS  
0
Figure 19. Switching Time Test Circuit  
Figure 20. Switching Time Waveforms  
www.onsemi.com  
6
FDP2532, FDB2532  
THERMAL RESISTANCE VS. MOUNTING PAD AREA  
The maximum rated junction temperature, T , and the  
can be evaluated using the onsemi device Spice thermal  
JM  
thermal resistance of the heat dissipating path determines the  
model or manually utilizing the normalized maximum  
transient thermal impedance curve.  
maximum allowable device power dissipation, P , in an  
DM  
application. Therefore the application’s ambient temperature,  
Thermal resistances corresponding to other copper areas  
can be obtained from Figure 21 or by calculation using  
Equation 2 or 3. Equation 2 is used for copper area defined  
in inches square and Equation 3 is for area in centimeters  
square. The area, in square inches or square centimeters is  
the top copper area including the gate and source pads.  
T
(°C), and thermal resistance R  
(°C/W) must be  
A
qJA  
reviewed to ensure that T is never exceeded. Equation 1  
JM  
mathematically represents the relationship and serves as the  
basis for establishing the rating of the part.  
ǒT  
Ǔ
JM * TA  
PDM  
+
19.84  
(eq. 1)  
RqJA + 26.51 )  
RqJA  
(eq. 2)  
(0.262 ) Area)  
In using surface mount devices such as the TO−263  
package, the environment in which it is applied will have a  
significant influence on the part’s current and maximum  
Area in Inches Squared  
128  
RqJA + 26.51 )  
(eq. 3)  
(1.69 ) Area)  
power dissipation ratings. Precise determination of P  
complex and influenced by many factors:  
is  
DM  
Area in Centimeters Squared  
1. Mounting pad area onto which the device is attached  
and whether there is copper on one side or both sides  
of the board.  
2. The number of copper layers and the thickness of the  
board.  
80  
R
R
= 26.51 + 19.84 / (0.262 + Area) eq. 2  
= 26.51 + 128 / (1.69 + Area) eq. 3  
q
JA  
JA  
q
3. The use of external heat sinks.  
4. The use of thermal vias.  
5. Air flow and board orientation.  
60  
40  
6. For non steady state applications, the pulse width,  
the duty cycle and the transient thermal response of  
the part, the board and the environment they are in.  
onsemi provides thermal information to assist the  
designer’s preliminary application evaluation. Figure 21  
defines the R for the device as a function of the top copper  
qJA  
20  
(component side) area. This is for a horizontally positioned  
FR−4 board with 1 oz copper after 1000 seconds of steady  
state power with no air flow. This graph provides the  
necessary information for calculation of the steady state  
junction temperature or power dissipation. Pulse applications  
10  
(64.5)  
0.1  
1
(0.645)  
(6.45)  
2
2
AREA, TOP COPPER AREA in (cm )  
Figure 21. Thermal Resistance vs. Mounting Pad Area  
www.onsemi.com  
7
 
FDP2532, FDB2532  
PSPICE ELECTRICAL MODEL  
.SUBCKT FDB2532 2 1 3 ; rev April 2002  
CA 12 8 1.4e−9  
CB 15 14 1.6e−9  
CIN 6 8 5.61e−9  
Dbody 7 5 DbodyMOD  
Dbreak 5 11 DbreakMOD  
Dplcap 10 5 DplcapMOD  
Ebreak 11 7 17 18 159  
Eds 14 8 5 8 1  
Egs 13 8 6 8 1  
Esg 6 10 6 8 1  
Evthres 6 21 19 8 1  
Evtemp 20 6 18 22 1  
It 8 17 1  
Lgate 1 9 9.56e−9  
Ldrain 2 5 1.0e−9  
Lsource 3 7 7.71e−9  
RLgate 1 9 95.6  
RLdrain 2 5 10  
RLsource 3 7 77.1  
Mmed 16 6 8 8 MmedMOD  
Mstro 16 6 8 8 MstroMOD  
Mweak 16 21 8 8 MweakMOD  
Rbreak 17 18 RbreakMOD 1  
Rdrain 50 16 RdrainMOD 9.6e−3  
Rgate 9 20 1.01  
RSLC1 5 51 RSLCMOD 1.0e−6  
RSLC2 5 50 1.0e3  
Rsource 8 7 RsourceMOD 3.0e−3  
Rvthres 22 8 RvthresMOD 1  
Rvtemp 18 19 RvtempMOD 1  
S1a 6 12 13 8 S1AMOD  
S1b 13 12 13 8 S1BMOD  
S2a 6 15 14 13 S2AMOD  
S2b 13 15 14 13 S2BMOD  
Vbat 22 19 DC 1  
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e−6*190),3))}  
.MODEL DbodyMOD D (IS=6.0E−11 N=1.09 RS=2.3e−3 TRS1=3.0e−3 TRS2=1.0e−6  
+ CJO=3.9e−9 M=0.65 TT=4.8e−8 XTI=4.2)  
.MODEL DbreakMOD D (RS=0.17 TRS1=3.0e−3 TRS2=−8.9e−6)  
.MODEL DplcapMOD D (CJO=1.0e−9 IS=1.0e−30 N=10 M=0.6)  
.MODEL MmedMOD NMOS (VTO=3.55 KP=10 IS=1e−30 N=10 TOX=1 L=1u W=1u RG=1.01)  
.MODEL MstroMOD NMOS (VTO=4.2 KP=145 IS=1e−30 N=10 TOX=1 L=1u W=1u)  
.MODEL MweakMOD NMOS (VTO=2.9 KP=0.05 IS=1e−30 N=10 TOX=1 L=1u W=1u RG=10.1 RS=0.1)  
www.onsemi.com  
8
FDP2532, FDB2532  
.MODEL RbreakMOD RES (TC1=1.1e−3 TC2=−9.0e−7)  
.MODEL RdrainMOD RES (TC1=9.0e−3 TC2=3.5e−5)  
.MODEL RSLCMOD RES (TC1=3.4e−3 TC2=1.5e−6)  
.MODEL RsourceMOD RES (TC1=4.0e−3 TC2=1.0e−6)  
.MODEL RvthresMOD RES (TC1=−4.1e−3 TC2=−1.4e−5)  
.MODEL RvtempMOD RES (TC1=−4.0e−3 TC2=3.5e−6)  
.MODEL S1AMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−6.0 VOFF=−4.0)  
.MODEL S1BMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−4.0 VOFF=−6.0)  
.MODEL S2AMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−1.4 VOFF=1.0)  
.MODEL S2BMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=1.0 VOFF=−1.4)  
.ENDS  
NOTE: Note: For further discussion of the PSPICE model, consult A New PSPICE Sub−Circuit for the Power MOSFET  
Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written  
by William J. Hepp and C. Frank Wheatley.  
LDRAIN  
DPLCAP  
DRAIN  
2
5
10  
RLDRAIN  
DBODY  
RSLC1  
51  
DBREAK  
+
RSLC2  
5
51  
ESLC  
11  
−
+
50  
−
17  
18  
−
RDRAIN  
6
8
EBREAK  
ESG  
EVTHRES  
+
16  
21  
+
−
19  
8
MWEAK  
LGATE  
EVTEMP  
RGATE  
GATE  
1
6
+
−
18  
22  
MMED  
9
20  
MSTRO  
8
RLGATE  
LSOURCE  
CIN  
SOURCE  
3
7
RSOURCE  
RLSOURCE  
S1A  
S2A  
RBREAK  
12  
15  
13  
8
14  
13  
17  
18  
RVTEMP  
19  
−
S1B  
S2B  
13  
++  
CB  
CA  
IT  
14  
+
VBAT  
6
8
5
8
EGS  
EDS  
+
−
−−  
8
22  
RVTHRES  
Figure 22.  
www.onsemi.com  
9
FDP2532, FDB2532  
SABER ELECTRICAL MODEL  
REV April 2002  
ttemplate FDB2532 n2,n1,n3  
electrical n2,n1,n3  
{
var i iscl  
dp..model dbodymod = (isl=6.0e−11,nl=1.09,rs=2.3e−3,trs1=3.0e−3,trs2=1.0e−6,cjo=3.9e−9,m=0.65,tt=4.8e−8,xti=4.2)  
dp..model dbreakmod = (rs=0.17,trs1=3.0e−3,trs2=−8.9e−6)  
dp..model dplcapmod = (cjo=1.0e−9,isl=10.0e−30,nl=10,m=0.6)  
m..model mmedmod = (type=_n,vto=3.55,kp=10,is=1e−30, tox=1)  
m..model mstrongmod = (type=_n,vto=4.2,kp=145,is=1e−30, tox=1)  
m..model mweakmod = (type=_n,vto=2.9,kp=0.05,is=1e−30, tox=1,rs=0.1)  
sw_vcsp..model s1amod = (ron=1e−5,roff=0.1,von=−6.0,voff=−4.0)  
sw_vcsp..model s1bmod = (ron=1e−5,roff=0.1,von=−4.0,voff=−6.0)  
sw_vcsp..model s2amod = (ron=1e−5,roff=0.1,von=−1.4,voff=1.0)  
sw_vcsp..model s2bmod = (ron=1e−5,roff=0.1,von=1.0,voff=−1.4)  
c.ca n12 n8 = 1.4e−9  
c.cb n15 n14 = 1.6e−9  
c.cin n6 n8 = 5.61e−9  
dp.dbody n7 n5 = model=dbodymod  
dp.dbreak n5 n11 = model=dbreakmod  
dp.dplcap n10 n5 = model=dplcapmod  
spe.ebreak n11 n7 n17 n18 = 159  
spe.eds n14 n8 n5 n8 = 1  
spe.egs n13 n8 n6 n8 = 1  
spe.esg n6 n10 n6 n8 = 1  
spe.evthres n6 n21 n19 n8 = 1  
spe.evtemp n20 n6 n18 n22 = 1  
i.it n8 n17 = 1  
l.lgate n1 n9 = 9.56e−9  
l.ldrain n2 n5 = 1.0e−9  
l.lsource n3 n7 = 7.71e−9  
res.rlgate n1 n9 = 95.6  
res.rldrain n2 n5 = 10  
res.rlsource n3 n7 = 77.1  
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u  
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u  
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u  
res.rbreak n17 n18 = 1, tc1=1.1e−3,tc2=−9.0e−7  
res.rdrain n50 n16 = 9.6e−3, tc1=9.0e−3,tc2=3.5e−5  
res.rgate n9 n20 = 1.01  
res.rslc1 n5 n51 = 1.0e−6, tc1=3.4e−3,tc2=1.5e−6  
res.rslc2 n5 n50 = 1.0e3  
res.rsource n8 n7 = 3.0e−3, tc1=4.0e−3,tc2=1.0e−6  
res.rvthres n22 n8 = 1, tc1=−4.1e−3,tc2=−1.4e−5  
res.rvtemp n18 n19 = 1, tc1=−4.0e−3,tc2=3.5e−6  
www.onsemi.com  
10  
FDP2532, FDB2532  
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod  
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod  
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod  
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod  
v.vbat n22 n19 = dc=1  
equations {  
i (n51−>n50) +=iscl  
iscl: v(n51,n50) = ((v(n5,n51)/(1e−9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/190))** 3))  
}
}
LDRAIN  
DPLCAP  
DRAIN  
2
5
10  
RLDRAIN  
RSLC1  
51  
RSLC2  
ISCL  
DBREAK  
50  
−
RDRAIN  
6
8
11  
ESG  
DBODY  
EVTHRES  
+
16  
21  
+
−
19  
8
MWEAK  
LGATE  
EVTEMP  
RGATE  
GATE  
1
6
+
−
18  
22  
EBREAK  
+
MMED  
9
20  
MSTRO  
8
17  
18  
−
RLGATE  
LSOURCE  
CIN  
SOURCE  
3
7
RSOURCE  
RLSOURCE  
S1A  
S2A  
S2B  
RBREAK  
12  
15  
13  
8
14  
13  
17  
18  
RVTEMP  
19  
−
S1B  
13  
++  
CB  
CA  
IT  
14  
+
VBAT  
6
8
5
8
EGS  
EDS  
+
−
−−  
8
22  
RVTHRES  
Figure 23.  
www.onsemi.com  
11  
FDP2532, FDB2532  
JUNCTION  
th  
SPICE THERMAL MODEL  
REV 26 February 2002  
FDB2532  
RTHERM1  
RTHERM2  
RTHERM3  
RTHERM4  
RTHERM5  
RTHERM6  
CTHERM1  
CTHERM1 TH 6 7.5e−3  
CTHERM2 6 5 8.0e−3  
CTHERM3 5 4 9.0e−3  
CTHERM4 4 3 2.4e−2  
CTHERM5 3 2 3.4e−2  
CTHERM6 2 TL 6.5e−2  
6
CTHERM2  
CTHERM3  
CTHERM4  
CTHERM5  
CTHERM6  
RTHERM1 TH 6 3.1e−4  
RTHERM2 6 5 2.5e−3  
RTHERM3 5 4 2.0e−2  
RTHERM4 4 3 8.0e−2  
RTHERM5 3 2 1.2e−1  
RTHERM6 2 TL 1.3e−1  
5
4
3
2
SABER THERMAL MODEL  
SABER thermal model FDB2532  
template thermal_model th tl  
thermal_c th, tl  
{
ctherm.ctherm1 th 6 =7.5e−3  
ctherm.ctherm2 6 5 =8.0e−3  
ctherm.ctherm3 5 4 =9.0e−3  
ctherm.ctherm4 4 3 =2.4e−2  
ctherm.ctherm5 3 2 =3.4e−2  
ctherm.ctherm6 2 tl =6.5e−2  
rrtherm.rtherm1 th 6 =3.1e−4  
rtherm.rtherm2 6 5 =2.5e−3  
rtherm.rtherm3 5 4 =2.0e−2  
rtherm.rtherm4 4 3 =8.0e−2  
rtherm.rtherm5 3 2 =1.2e−1  
rtherm.rtherm6 2 tl =1.3e−1  
}
tl  
CASE  
Figure 24.  
PACKAGE MARKING AND ORDERING INFORMATION  
†
Device  
FDB2532  
Device Marking  
Package  
Reel Size  
Tape Width  
Shipping  
2
FDB2532  
D −PAK  
330 mm  
24 mm  
3000 Units / Tape & Reel  
800 Units / Tube  
(Pb−Free, Halide Free)  
FDP2532  
FDP2532  
TO−220  
N/A  
N/A  
(Pb−Free, Halide Free)  
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging  
Specifications Brochure, BRD8011/D.  
POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States  
and/or other countries.  
www.onsemi.com  
12  
MECHANICAL CASE OUTLINE  
PACKAGE DIMENSIONS  
TO−220−3LD  
CASE 340AT  
ISSUE A  
DATE 03 OCT 2017  
Scale 1:1  
Electronic versions are uncontrolled except when accessed directly from the Document Repository.  
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.  
DOCUMENT NUMBER:  
DESCRIPTION:  
98AON13818G  
TO−220−3LD  
PAGE 1 OF 1  
ON Semiconductor and  
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.  
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding  
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically  
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the  
rights of others.  
© Semiconductor Components Industries, LLC, 2019  
www.onsemi.com  
MECHANICAL CASE OUTLINE  
PACKAGE DIMENSIONS  
D2PAK−3 (TO−263, 3−LEAD)  
CASE 418AJ  
ISSUE F  
DATE 11 MAR 2021  
SCALE 1:1  
XXXXXX = Specific Device Code  
A
= Assembly Location  
WL  
Y
= Wafer Lot  
= Year  
GENERIC MARKING DIAGRAMS*  
WW  
W
M
G
AKA  
= Work Week  
= Week Code (SSG)  
= Month Code (SSG)  
= Pb−Free Package  
= Polarity Indicator  
XX  
AYWW  
XXXXXXXXG  
AKA  
XXXXXXXXG  
AYWW  
XXXXXX  
XXYMW  
XXXXXXXXX  
AWLYWWG  
*This information is generic. Please refer to  
device data sheet for actual part marking.  
Pb−Free indicator, “G” or microdot “ G”,  
may or may not be present. Some products  
may not follow the Generic Marking.  
IC  
Standard  
Rectifier  
SSG  
Electronic versions are uncontrolled except when accessed directly from the Document Repository.  
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.  
DOCUMENT NUMBER:  
98AON56370E  
D2PAK−3 (TO−263, 3−LEAD)  
PAGE 1 OF 1  
DESCRIPTION:  
ON Semiconductor and  
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.  
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding  
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically  
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the  
rights of others.  
© Semiconductor Components Industries, LLC, 2018  
www.onsemi.com  
onsemi,  
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates  
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A  
listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes without further notice to any  
products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising  
out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is  
responsible for its products and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or  
applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual  
performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey  
any license under its patent rights nor the rights of others. If the product is to be used as a critical component in life support systems, or any FDA Class 3 medical devices or medical devices  
with a similar or equivalent classification in a foreign jurisdiction, or any devices intended for implantation in the human body, sale is subject to onsemi’s advance written authorization  
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