FDB3672-F085 [ONSEMI]

100 V、44 A、24 mΩ、D2PAKN 沟道 UltraFET® Trench;
FDB3672-F085
型号: FDB3672-F085
厂家: ONSEMI    ONSEMI
描述:

100 V、44 A、24 mΩ、D2PAKN 沟道 UltraFET® Trench

开关 晶体管
文件: 总12页 (文件大小:566K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
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Is Now  
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www.onsemi.com  
onsemi andꢀꢀꢀꢀꢀꢀꢀand other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or  
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FDB3672-F085  
N-Channel PowerTrench® MOSFET  
100V, 44A, 28mΩ  
Applications  
Features  
r
= 24m(Typ.), V = 10V, I = 44A  
DC/DC converters and Off-Line UPS  
Distributed Power Architectures and VRMs  
Primary Switch for 24V and 48V Systems  
High Voltage Synchronous Rectifier  
Direct Injection / Diesel Injection Systems  
42V Automotive Load Control  
DS(ON)  
GS  
D
Q (tot) = 24nC (Typ.), V = 10V  
g
GS  
Low Miller Charge  
Low Q Body Diode  
RR  
Optimized efficiency at high frequencies  
UIS Capability (Single Pulse and Repetitive Pulse)  
Qualified to AEC Q101  
RoHS Compliant  
Electronic Valve Train Systems  
Formerly developmental type 82760  
DRAIN  
D
(FLANGE)  
GATE  
SOURCE  
G
TO-263AB  
FDB SERIES  
S
MOSFET Maximum Ratings T = 25°C unless otherwise noted  
C
Symbol  
Parameter  
Ratings  
100  
Units  
V
V
Drain to Source Voltage  
Gate to Source Voltage  
V
V
DSS  
GS  
±20  
Drain Current  
o
44  
31  
A
A
Continuous (T = 25 C, V = 10V)  
C
GS  
o
I
Continuous (T = 100 C, V = 10V)  
C GS  
D
o
o
Continuous (T  
= 25 C, V = 10V, R = 43 C/W)  
θJA  
7.2  
A
amb  
GS  
Pulsed  
Figure 4  
120  
A
E
P
Single Pulse Avalanche Energy (Note 1)  
Power dissipation  
mJ  
W
AS  
120  
D
o
o
Derate above 25 C  
0.8  
W/ C  
o
T , T  
Operating and Storage Temperature  
-55 to 175  
C
J
STG  
Thermal Characteristics  
o
R
R
R
Thermal Resistance Junction to Case TO-263  
1.25  
62  
C/W  
θJC  
θJA  
θJA  
o
Thermal Resistance Junction to Ambient TO-263 (Note 2)  
C/W  
2
o
Thermal Resistance Junction to Ambient TO-263, 1in copper pad area  
43  
C/W  
©2009 Semiconductor Components Industries, LLC.  
Publication Order Number:  
September-2017, Rev. 1  
FDB3672-F085/D  
Package Marking and Ordering Information  
Device Marking  
Device  
Package  
Reel Size  
Tape Width  
Quantity  
FDB3672-F085  
FDB3672  
TO-263AB  
330mm  
24mm  
800 units  
Electrical Characteristics T = 25°C unless otherwise noted  
C
Symbol  
Parameter  
Test Conditions  
Min  
Typ  
Max  
Units  
Off Characteristics  
B
Drain to Source Breakdown Voltage  
Zero Gate Voltage Drain Current  
Gate to Source Leakage Current  
I
= 250µA, V = 0V  
100  
-
-
-
-
-
V
VDSS  
D
GS  
V
V
= 80V  
= 0V  
-
-
-
1
DS  
GS  
I
I
µA  
nA  
DSS  
o
T = 150 C  
250  
±100  
C
V
= ±20V  
GSS  
GS  
On Characteristics  
V
Gate to Source Threshold Voltage  
V
= V , I = 250µA  
2
-
-
4
V
GS(TH)  
GS  
DS  
D
I
I
= 44A, V = 10V  
0.024 0.028  
0.031 0.047  
0.054 0.068  
D
D
GS  
r
Drain to Source On Resistance  
= 21A, V = 6V,  
-
DS(ON)  
GS  
o
I =44A, V =10V, T =175 C  
-
D
GS  
C
Dynamic Characteristics  
C
C
C
Input Capacitance  
-
-
-
-
-
-
-
-
1710  
247  
62  
-
-
pF  
pF  
pF  
nC  
nC  
nC  
nC  
nC  
ISS  
V
= 25V, V = 0V,  
GS  
DS  
Output Capacitance  
OSS  
RSS  
f = 1MHz  
Reverse Transfer Capacitance  
Total Gate Charge at 10V  
Threshold Gate Charge  
-
Q
Q
Q
Q
Q
V
V
= 0V to 10V  
= 0V to 2V  
24  
31  
4.5  
-
g(TOT)  
g(TH)  
gs  
GS  
3.5  
11  
GS  
V
= 50V  
DD  
Gate to Source Gate Charge  
Gate Charge Threshold to Plateau  
Gate to Drain “Miller” Charge  
I = 44A  
D
I = 1.0mA  
g
7.2  
4.5  
-
gs2  
-
gd  
Resistive Switching Characteristics (V = 10V)  
GS  
t
t
t
t
t
t
Turn-On Time  
Turn-On Delay Time  
Rise Time  
-
-
-
-
-
-
-
104  
ns  
ns  
ns  
ns  
ns  
ns  
ON  
11  
59  
26  
44  
-
-
d(ON)  
-
V
V
= 50V, I = 44A  
r
DD  
GS  
D
= 10V, R = 11.0Ω  
Turn-Off Delay Time  
Fall Time  
-
-
GS  
d(OFF)  
f
Turn-Off Time  
104  
OFF  
Drain-Source Diode Characteristics  
I
I
I
I
= 44A  
= 21A  
-
-
-
-
-
-
-
-
1.25  
1.0  
52  
V
V
SD  
SD  
SD  
SD  
V
Source to Drain Diode Voltage  
SD  
t
Reverse Recovery Time  
= 44A, dI /dt =100A/µs  
ns  
nC  
rr  
SD  
Q
Reverse Recovered Charge  
= 44A, dI /dt =100A/µs  
80  
RR  
SD  
Notes:  
1: Starting T = 25°C, L = 0.6mH, I = 20A.  
J
AS  
2: Pulse Width = 100s  
www.onsemi.com  
2
Typical Characteristics T = 25°C unless otherwise noted  
C
1.2  
50  
V
= 10V  
GS  
1.0  
40  
0.8  
30  
0.6  
20  
0.4  
10  
0.2  
0
0
0
25  
50  
75  
100  
150  
175  
125  
o
25  
50  
75  
100  
125  
150  
175  
o
T
, CASE TEMPERATURE ( C)  
C
T , CASE TEMPERATURE ( C)  
C
Figure 1. Normalized Power Dissipation vs  
Ambient Temperature  
Figure 2. Maximum Continuous Drain Current vs  
Case Temperature  
2
DUTY CYCLE - DESCENDING ORDER  
0.5  
0.2  
1
0.1  
0.05  
0.02  
0.01  
P
DM  
0.1  
t
1
t
2
NOTES:  
DUTY FACTOR: D = t /t  
SINGLE PULSE  
1
2
PEAK T = P  
x Z  
x R  
+ T  
J
DM  
θJC  
θJC C  
0.01  
-5  
-4  
-3  
-2  
-1  
0
1
10  
10  
10  
10  
10  
10  
10  
t, RECTANGULAR PULSE DURATION (s)  
Figure 3. Normalized Maximum Transient Thermal Impedance  
500  
o
T
= 25 C  
C
TRANSCONDUCTANCE  
MAY LIMIT CURRENT  
IN THIS REGION  
FOR TEMPERATURES  
o
ABOVE 25 C DERATE PEAK  
CURRENT AS FOLLOWS:  
175 - T  
150  
C
I = I  
25  
V
= 10V  
GS  
100  
30  
-5  
-4  
-3  
-2  
-1  
0
1
10  
10  
10  
10  
t, PULSE WIDTH (s)  
10  
10  
10  
Figure 4. Peak Current Capability  
www.onsemi.com  
3
Typical Characteristics T = 25°C unless otherwise noted  
C
200  
100  
300  
100  
If R = 0  
= (L)(I )/(1.3*RATED BV  
10µs  
t
AV  
- V  
DD  
)
AS  
DSS  
If R 0  
t
= (L/R)ln[(I *R)/(1.3*RATED BV  
- V ) +1]  
DD  
AV  
AS  
DSS  
100µs  
10  
1
o
OPERATION IN THIS  
AREA MAY BE  
STARTING T = 25 C  
J
LIMITED BY r  
DS(ON)  
10  
1ms  
10ms  
DC  
o
STARTING T = 150 C  
J
SINGLE PULSE  
T
= MAX RATED  
= 25 C  
J
o
T
C
1
0.1  
0.001  
0.01  
0.1  
1
10  
1
10  
, DRAIN TO SOURCE VOLTAGE (V)  
100  
200  
V
t , TIME IN AVALANCHE (ms)  
AV  
DS  
Figure 5. Forward Bias Safe Operating Area  
Figure 6. Unclamped Inductive Switching  
Capability  
80  
80  
PULSE DURATION = 80µs  
o
T
= 25 C  
C
V
= 10V  
DUTY CYCLE = 0.5% MAX  
GS  
V
= 7V  
GS  
V
= 15V  
DD  
60  
40  
20  
0
60  
40  
20  
0
V
= 6V  
GS  
o
T
= 175 C  
J
PULSE DURATION = 80µs  
DUTY CYCLE = 0.5% MAX  
o
T
= 25 C  
J
o
T
= -55 C  
J
V
= 5V  
2.0  
GS  
3.5  
4.0  
4.5  
5.0  
5.5  
6.0  
6.5  
0
0.5  
1.0  
1.5  
2.5  
3.0  
V
, GATE TO SOURCE VOLTAGE (V)  
V
, DRAIN TO SOURCE VOLTAGE (V)  
DS  
GS  
Figure 7. Transfer Characteristics  
Figure 8. Saturation Characteristics  
40  
35  
30  
25  
20  
15  
2.5  
PULSE DURATION = 80µs  
DUTY CYCLE = 0.5% MAX  
PULSE DURATION = 80µs  
DUTY CYCLE = 0.5% MAX  
2.0  
1.5  
1.0  
0.5  
V
= 6V  
GS  
V
= 10V  
GS  
V
= 10V, I = 44A  
D
GS  
0
10  
20  
30  
40  
50  
-80  
-40  
0
40  
80  
120  
160  
200  
o
I , DRAIN CURRENT (A)  
T , JUNCTION TEMPERATURE ( C)  
D
J
Figure 9. Drain to Source On Resistance vs Drain  
Current  
Figure 10. Normalized Drain to Source On  
Resistance vs Junction Temperature  
www.onsemi.com  
4
Typical Characteristics T = 25°C unless otherwise noted  
C
1.2  
1.0  
0.8  
0.6  
0.4  
1.2  
1.1  
1.0  
0.9  
I
= 250µA  
D
V
= V , I = 250µA  
DS D  
GS  
-80  
-40  
0
40  
80  
120  
160  
200  
-80  
-40  
0
40  
80  
120  
160  
200  
o
o
T , JUNCTION TEMPERATURE ( C)  
T , JUNCTION TEMPERATURE ( C)  
J
J
Figure 11. Normalized Gate Threshold Voltage vs  
Junction Temperature  
Figure 12. Normalized Drain to Source  
Breakdown Voltage vs Junction Temperature  
3000  
10  
V
= 50V  
DD  
C
= C + C  
GS GD  
ISS  
1000  
100  
10  
8
6
4
2
0
C
C
+ C  
OSS  
DS GD  
C
= C  
GD  
RSS  
WAVEFORMS IN  
DESCENDING ORDER:  
I
I
= 44A  
= 22A  
V
= 0V, f = 1MHz  
D
D
GS  
0
5
10  
15  
20  
25  
0.1  
1
10  
100  
V
, DRAIN TO SOURCE VOLTAGE (V)  
Q , GATE CHARGE (nC)  
DS  
g
Figure 13. Capacitance vs Drain to Source  
Voltage  
Figure 14. Gate Charge Waveforms for Constant  
Gate Currents  
www.onsemi.com  
5
Test Circuits and Waveforms  
V
BV  
DSS  
DS  
t
P
V
DS  
L
I
AS  
V
DD  
VARY t TO OBTAIN  
P
+
-
R
REQUIRED PEAK I  
G
AS  
V
DD  
V
GS  
DUT  
t
P
I
0V  
AS  
0
0.01Ω  
t
AV  
Figure 15. Unclamped Energy Test Circuit  
Figure 16. Unclamped Energy Waveforms  
V
DS  
V
Q
DD  
g(TOT)  
V
DS  
L
V
= 10V  
GS  
V
GS  
+
-
V
DD  
V
GS  
V
= 2V  
DUT  
GS  
Q
gs2  
0
I
g(REF)  
Q
g(TH)  
Q
Q
gd  
gs  
I
g(REF)  
0
Figure 17. Gate Charge Test Circuit  
Figure 18. Gate Charge Waveforms  
V
DS  
t
t
ON  
OFF  
t
d(OFF)  
t
d(ON)  
R
t
t
f
L
r
V
0
DS  
90%  
90%  
+
-
V
GS  
V
DD  
10%  
10%  
DUT  
90%  
50%  
R
GS  
V
GS  
50%  
PULSE WIDTH  
10%  
V
GS  
0
Figure 19. Switching Time Test Circuit  
Figure 20. Switching Time Waveforms  
www.onsemi.com  
6
Thermal Resistance vs. Mounting Pad Area  
The maximum rated junction temperature, T , and the  
thermal resistance of the heat dissipating path determines  
80  
60  
40  
20  
JM  
R
= 26.51+ 19.84/(0.262+Area) EQ.2  
θJA  
the maximum allowable device power dissipation, P , in an  
DM  
R
= 26.51+ 128/(1.69+Area) EQ.3  
θJA  
application.  
Therefore the application’s ambient  
o
o
temperature, T ( C), and thermal resistance R  
( C/W)  
A
θJA  
must be reviewed to ensure that T  
is never exceeded.  
JM  
Equation 1 mathematically represents the relationship and  
serves as the basis for establishing the rating of the part.  
(T  
T )  
JM  
A
(EQ. 1)  
P
= -----------------------------  
DM  
RθJA  
In using surface mount devices such as the TO-252  
package, the environment in which it is applied will have a  
significant influence on the part’s current and maximum  
0.1  
(0.645)  
1
10  
(6.45)  
(64.5)  
power dissipation ratings. Precise determination of P  
complex and influenced by many factors:  
is  
DM  
2
2
AREA, TOP COPPER AREA in (cm )  
Figure 21. Thermal Resistance vs Mounting  
Pad Area  
1. Mounting pad area onto which the device is attached and  
whether there is copper on one side or both sides of the  
board.  
2. The number of copper layers and the thickness of the  
board.  
3. The use of external heat sinks.  
4. The use of thermal vias.  
5. Air flow and board orientation.  
6. For non steady state applications, the pulse width, the  
duty cycle and the transient thermal response of the part,  
the board and the environment they are in.  
ON Semiconductor provides thermal information to  
assist  
evaluation. Figure 21  
defines the R for the device as a function of the top  
the  
designer’s  
preliminary  
application  
θJA  
copper (component side) area. This is for a horizontally  
positioned FR-4 board with 1oz copper after 1000 seconds  
of steady state power with no air flow. This graph provides  
the necessary information for calculation of the steady state  
junction temperature or power dissipation. Pulse  
applications  
can  
be  
evaluated  
using  
the  
ON  
Semiconductor device Spice thermal model or manually  
utilizing the normalized maximum transient thermal  
impedance curve.  
Thermal resistances corresponding to other copper areas  
can be obtained from Figure 21 or by calculation using  
Equation 2 or 3. Equation 2 is used for copper area defined  
in inches square and equation 3 is for area in centimeters  
square. The area, in square inches or square centimeters is  
the top copper area including the gate and source pads.  
19.84  
(0.262 + Area)  
R
R
= 26.51 + ------------------------------------  
(EQ. 2)  
θJA  
θJA  
Area in Inches Squared  
128  
= 26.51 + ---------------------------------  
(EQ. 3)  
(1.69 + Area)  
Area in Centimeters Squared  
www.onsemi.com  
7
PSPICE Electrical Model  
.SUBCKT FDB3672 2 1 3 ;  
CA 12 8 5.8e-10  
Cb 15 14 6.8e-10  
Cin 6 8 1.6e-9  
rev May 2004  
LDRAIN  
DPLCAP  
DRAIN  
2
5
10  
Dbody 7 5 DbodyMOD  
Dbreak 5 11 DbreakMOD  
Dplcap 10 5 DplcapMOD  
RLDRAIN  
RSLC1  
51  
DBREAK  
+
RSLC2  
5
51  
ESLC  
11  
Ebreak 11 7 17 18 105  
Eds 14 8 5 8 1  
Egs 13 8 6 8 1  
Esg 6 10 6 8 1  
Evthres 6 21 19 8 1  
Evtemp 20 6 18 22 1  
-
+
50  
-
17  
DBODY  
RDRAIN  
6
8
EBREAK 18  
-
ESG  
EVTHRES  
+
16  
21  
+
-
19  
8
MWEAK  
LGATE  
EVTEMP  
RGATE  
GATE  
1
+
6
-
18  
22  
It 8 17 1  
MMED  
9
20  
MSTRO  
8
RLGATE  
Lgate 1 9 9.56e-9  
Ldrain 2 5 1.0e-9  
Lsource 3 7 4.45e-9  
LSOURCE  
CIN  
SOURCE  
3
7
RSOURCE  
RLSOURCE  
RLgate 1 9 95.6  
RLdrain 2 5 10  
RLsource 3 7 44.5  
S1A  
S2A  
RBREAK  
12  
15  
13  
8
14  
13  
17  
18  
RVTEMP  
19  
S1B  
S2B  
Mmed 16 6 8 8 MmedMOD  
Mstro 16 6 8 8 MstroMOD  
Mweak 16 21 8 8 MweakMOD  
13  
CB  
CA  
IT  
14  
-
+
+
VBAT  
6
8
5
8
EGS  
EDS  
+
Rbreak 17 18 RbreakMOD 1  
Rdrain 50 16 RdrainMOD 6.0e-3  
Rgate 9 20 1.5  
-
-
8
22  
RVTHRES  
RSLC1 5 51 RSLCMOD 1.0e-6  
RSLC2 5 50 1.0e3  
Rsource 8 7 RsourceMOD 9.5e-3  
Rvthres 22 8 RvthresMOD 1  
Rvtemp 18 19 RvtempMOD 1  
S1a 6 12 13 8 S1AMOD  
S1b 13 12 13 8 S1BMOD  
S2a 6 15 14 13 S2AMOD  
S2b 13 15 14 13 S2BMOD  
Vbat 22 19 DC 1  
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*98),3))}  
.MODEL DbodyMOD D (IS=1.0E-11 N=1.05 RS=3.7e-3 TRS1=2.5e-3 TRS2=1.0e-6  
+ CJO=1.2e-9 M=0.58 TT=3.75e-8 XTI=4.0)  
.MODEL DbreakMOD D (RS=15 TRS1=4.0e-3 TRS2=-5.0e-6)  
.MODEL DplcapMOD D (CJO=3.8e-10 IS=1.0e-30 N=10 M=0.60)  
.MODEL MmedMOD NMOS (VTO=3.6 KP=3 IS=1e-40 N=10 TOX=1 L=1u W=1u RG=1.5)  
.MODEL MstroMOD NMOS (VTO=4.3 KP=59 IS=1e-30 N=10 TOX=1 L=1u W=1u)  
.MODEL MweakMOD NMOS (VTO=3.09 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=15 RS=0.1)  
.MODEL RbreakMOD RES (TC1=9.0e-4 TC2=-1.0e-7)  
.MODEL RdrainMOD RES (TC1=11.0e-3 TC2=5.0e-5)  
.MODEL RSLCMOD RES (TC1=3.0e-3 TC2=1.0e-6)  
.MODEL RsourceMOD RES (TC1=4.0e-3 TC2=1.0e-6)  
.MODEL RvthresMOD RES (TC1=-3.5e-3 TC2=-1.5e-5)  
.MODEL RvtempMOD RES (TC1=-4.3e-3 TC2=1.5e-6)  
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-5.0 VOFF=-3.5)  
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.5 VOFF=-5.0)  
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=0.3)  
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.3 VOFF=-0.5)  
.ENDS  
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global  
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank  
Wheatley.  
www.onsemi.com  
8
SABER Electrical Model  
REV May 2004  
template FDB3672 n2,n1,n3  
electrical n2,n1,n3  
{
var i iscl  
dp..model dbodymod = (isl=1.0e-11,nl=1.05,rs=3.7e-3,trs1=2.5e-3,trs2=1.0e-6,cjo=1.2e-9,m=0.58,tt=3.75e-8,xti=4.0)  
dp..model dbreakmod = (rs=15,trs1=4.0e-3,trs2=-5.0e-6)  
dp..model dplcapmod = (cjo=3.8e-10,isl=10.0e-30,nl=10,m=0.60)  
m..model mmedmod = (type=_n,vto=3.6,kp=3,is=1e-40, tox=1)  
m..model mstrongmod = (type=_n,vto=4.3,kp=59,is=1e-30, tox=1)  
LDRAIN  
m..model mweakmod = (type=_n,vto=3.09,kp=0.05,is=1e-30, tox=1,rs=0.1)  
DPLCAP  
DRAIN  
2
5
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-5.0,voff=-3.5)  
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3.5,voff=-5.0) 10  
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.5,voff=0.3)  
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.3,voff=-0.5)  
c.ca n12 n8 = 5.8e-10  
c.cb n15 n14 = 6.8e-10  
c.cin n6 n8 = 1.6e-9  
RLDRAIN  
RSLC1  
51  
RSLC2  
ISCL  
DBREAK  
11  
50  
-
RDRAIN  
dp.dbody n7 n5 = model=dbodymod  
dp.dbreak n5 n11 = model=dbreakmod  
dp.dplcap n10 n5 = model=dplcapmod  
6
8
ESG  
DBODY  
EVTHRES  
+
16  
21  
+
-
19  
8
MWEAK  
LGATE  
EVTEMP  
RGATE  
GATE  
1
+
6
spe.ebreak n11 n7 n17 n18 = 105  
spe.eds n14 n8 n5 n8 = 1  
-
18  
22  
EBREAK  
+
MMED  
9
20  
MSTRO  
8
17  
18  
-
RLGATE  
spe.egs n13 n8 n6 n8 = 1  
LSOURCE  
spe.esg n6 n10 n6 n8 = 1  
spe.evthres n6 n21 n19 n8 = 1  
CIN  
SOURCE  
3
7
spe.evtemp n20 n6 n18 n22 = 1  
RSOURCE  
RLSOURCE  
S1A  
S2A  
i.it n8 n17 = 1  
RBREAK  
12  
15  
13  
8
14  
13  
17  
18  
l.lgate n1 n9 = 95.6e-9  
l.ldrain n2 n5 = 1.0e-9  
l.lsource n3 n7 = 4.45e-9  
RVTEMP  
19  
S1B  
S2B  
13  
CB  
CA  
IT  
14  
-
+
+
VBAT  
res.rlgate n1 n9 = 9.56  
res.rldrain n2 n5 = 10  
res.rlsource n3 n7 = 44.5  
6
8
5
8
EGS  
EDS  
+
-
-
8
22  
RVTHRES  
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u  
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u  
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u  
res.rbreak n17 n18 = 1, tc1=9.0e-4,tc2=-1.0e-7  
res.rdrain n50 n16 = 6.0e-3, tc1=11.0e-3,tc2=5.0e-5  
res.rgate n9 n20 = 1.5  
res.rslc1 n5 n51 = 1.0e-6, tc1=3.0e-3,tc2=1.0e-6  
res.rslc2 n5 n50 = 1.0e3  
res.rsource n8 n7 = 9.5e-3, tc1=4.0e-3,tc2=1.0e-6  
res.rvthres n22 n8 = 1, tc1=-3.5e-3,tc2=-1.5e-5  
res.rvtemp n18 n19 = 1, tc1=-4.3e-3,tc2=1.5e-6  
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod  
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod  
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod  
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod  
v.vbat n22 n19 = dc=1  
equations {  
i (n51->n50) +=iscl  
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/98))** 3))  
}
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9
SPICE Thermal Model  
JUNCTION  
th  
REV May 2004  
FDB3672  
CTHERM1 TH 6 3.2e-3  
CTHERM2 6 5 3.3e-3  
CTHERM3 5 4 3.4e-3  
CTHERM4 4 3 3.5e-3  
CTHERM5 3 2 6.4e-3  
CTHERM6 2 TL 1.9e-2  
RTHERM1  
RTHERM2  
RTHERM3  
RTHERM4  
RTHERM5  
RTHERM6  
CTHERM1  
6
RTHERM1 TH 6 5.5e-4  
RTHERM2 6 5 5.0e-3  
RTHERM3 5 4 4.5e-2  
RTHERM4 4 3 10.5e-2  
RTHERM5 3 2 3.4e-1  
RTHERM6 2 TL 3.5e-1  
CTHERM2  
CTHERM3  
CTHERM4  
CTHERM5  
CTHERM6  
5
SABER Thermal Model  
SABER thermal model FDB3672  
template thermal_model th tl  
thermal_c th, tl  
{
cctherm.ctherm1 th 6 =3.2e-3  
ctherm.ctherm2 6 5 =3.3e-3  
ctherm.ctherm3 5 4 =3.4e-3  
ctherm.ctherm4 4 3 =3.5e-3  
ctherm.ctherm5 3 2 =6.4e-3  
ctherm.ctherm6 2 tl =1.9e-2  
4
3
2
rtherm.rtherm1 th 6 =5.5e-4  
rtherm.rtherm2 6 5 =5.0e-3  
rtherm.rtherm3 5 4 =4.5e-2  
rtherm.rtherm4 4 3 =10.5e-2  
rtherm.rtherm5 3 2 =3.4e-1  
rtherm.rtherm6 2 tl =3.5e-1  
}
tl  
CASE  
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10  
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