FDD24AN06LA0-F085 [ONSEMI]
N 沟道，PowerTrench® MOSFET，60V，40A，16mΩ;
| 型号： | FDD24AN06LA0-F085 |
| 厂家： | 
ONSEMI |
| 描述： | N 沟道，PowerTrench® MOSFET，60V，40A，16mΩ |
| 文件： | 总10页 (文件大小：672K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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August 2011
FDD24AN06LA0_F085
N-Channel Logic Level PowerTrench MOSFET
®
60V, 36A, 24mΩ
Features
Applications
•
•
•
•
•
•
•
r
DS(ON) = 20mΩ (Typ.), VGS = 5V, ID = 36A
•
•
•
•
•
•
•
Motor / Body Load Control
Qg(tot) = 16nC (Typ.), VGS = 5V
Low Miller Charge
ABS Systems
Powertrain Management
Low QRR Body Diode
Injection Systems
UIS Capability (Single Pulse and Repetitive Pulse)
Qualified to AEC Q101
DC-DC converters and Off-line UPS
Distributed Power Architectures and VRMs
Primary Switch for 12V and 24V systems
RoHS Compliant
Formerly developmental type 83547
DRAIN (FLANGE)
D
GATE
SOURCE
G
TO-252AA
FDD SERIES
S
MOSFET Maximum Ratings TC = 25°C unless otherwise noted
Symbol
VDSS
VGS
Parameter
Ratings
60
Units
Drain to Source Voltage
Gate to Source Voltage
Drain Current
V
V
±20
Continuous (TC = 25oC, VGS = 10V)
Continuous (TC = 25oC, VGS = 5V)
Continuous (TC = 100oC, VGS = 5V)
Continuous (TA = 25oC, VGS = 5V, RθJA = 52oC/W)
Pulsed
40
A
36
25
A
A
ID
7.1
A
Figure 4
32
A
EAS
Single Pulse Avalanche Energy (Note 1)
Power dissipation
mJ
W
75
PD
Derate above 25oC
0.5
W/oC
oC
TJ, TSTG
Operating and Storage Temperature
-55 to 175
Thermal Characteristics
RθJC
RθJA
RθJA
Thermal Resistance Junction to Case TO-252
2.0
100
52
oC/W
oC/W
oC/W
Thermal Resistance Junction to Ambient TO-252
Thermal Resistance Junction to Ambient TO-252, 1in2 copper pad area
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a
copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.
All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems
certification.
©2011 Fairchild Semiconductor Corporation
FDD24AN06LA0_F085 Rev. C1
www.fairchildsemi.com
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
Tape Width
Quantity
FDD24AN06LA0
FDD24AN06LA0
TO-252AA
330mm
16mm
2500 units
Electrical Characteristics TC = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
ID = 250µA, VGS = 0V
60
-
-
-
-
-
-
V
V
DS = 50V
1
IDSS
µA
nA
VGS = 0V
TC = 150oC
-
250
±100
IGSS
VGS = ±20V
-
On Characteristics
VGS(TH)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250µA
D = 40A, VGS = 10V
ID = 36A, VGS = 5V
1
-
-
2
V
I
0.016 0.019
0.020 0.024
-
rDS(ON)
Drain to Source On Resistance
Ω
I
D = 36A, VGS = 5V,
-
0.047 0.056
TJ = 175oC
Dynamic Characteristics
CISS
Input Capacitance
-
-
-
1850
180
75
-
-
pF
pF
pF
nC
nC
nC
nC
nC
VDS = 25V, VGS = 0V,
f = 1MHz
COSS
CRSS
Qg(TOT)
Qg(TH)
Qgs
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge at 5V
Threshold Gate Charge
-
VGS = 0V to 5V
16
21
2.4
-
VGS = 0V to 1V
-
-
-
-
1.8
6.3
4.5
5.0
VDD = 30V
ID = 36A
Gate to Source Gate Charge
Gate Charge Threshold to Plateau
Gate to Drain “Miller” Charge
Ig = 1.0mA
Qgs2
-
Qgd
-
Switching Characteristics (VGS = 5V)
tON
td(ON)
tr
Turn-On Time
Turn-On Delay Time
Rise Time
-
-
-
-
-
-
-
12
118
26
41
-
195
ns
ns
ns
ns
ns
ns
-
-
VDD = 30V, ID = 36A
VGS = 5V, RGS = 9.1Ω
td(OFF)
tf
Turn-Off Delay Time
Fall Time
-
-
tOFF
Turn-Off Time
101
Drain-Source Diode Characteristics
I
SD = 36A
-
-
-
-
-
-
-
-
1.25
1.0
34
V
V
VSD
Source to Drain Diode Voltage
ISD = 18A
trr
Reverse Recovery Time
ISD = 36A, dISD/dt = 100A/µs
ISD = 36A, dISD/dt = 100A/µs
ns
nC
QRR
Reverse Recovered Charge
30
Notes:
1: Starting T = 25°C, L = 80µH, I = 28A.
J
AS
©2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FDD24AN06LA0_F085 Rev. C1
Typical Characteristics TC = 25°C unless otherwise noted
1.2
1.0
0.8
0.6
0.4
0.2
0
50
40
30
20
V
= 10V
GS
V
= 5V
GS
10
0
150
0
25
50
75
100
175
125
o
25
50
75
T , CASE TEMPERATURE ( C)
C
100
125
150
175
o
T
, CASE TEMPERATURE ( C)
C
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
1
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t /t
1
2
SINGLE PULSE
PEAK T = P x Z
x R
+ T
θJC C
J
DM
θJC
0.01
-5
-4
-3
-2
-1
0
1
10
10
10
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
400
o
T
= 25 C
C
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
FOR TEMPERATURES
o
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
V
= 10V
175 - T
GS
C
I = I
25
150
100
V
= 5V
GS
30
-5
-4
-3
-2
-1
0
1
10
10
10
10
t, PULSE WIDTH (s)
10
10
10
Figure 4. Peak Current Capability
www.fairchildsemi.com
©2011 Fairchild Semiconductor Corporation
FDD24AN06LA0_F085 Rev. C1
Typical Characteristics TC = 25°C unless otherwise noted
1000
100
10
100
10
1
10µs
100µs
o
STARTING T = 25 C
J
1ms
10ms
OPERATION IN THIS
AREA MAY BE
o
STARTING T = 150 C
J
LIMITED BY r
DS(ON)
If R = 0
1
t
= (L)(I )/(1.3*RATED BV
- V
)
AV
DC
AS
DSS
DD
SINGLE PULSE
If R
AV
≠
0
T
= MAX RATED
= 25 C
t
= (L/R)ln[(I *R)/(1.3*RATED BV
AS
- V ) +1]
DD
J
DSS
o
T
C
0.1
0.001
0.01
0.1
t , TIME IN AVALANCHE (ms)
AV
1
10
100
1
10
, DRAIN TO SOURCE VOLTAGE (V)
100
V
DS
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching
Capability
Figure 5. Forward Bias Safe Operating Area
60
60
V
= 10V
V
= 5V
PULSE DURATION = 80µs
GS
GS
DUTY CYCLE = 0.5% MAX
V
= 3.5V
GS
V
= 15V
DD
45
45
30
15
0
30
15
0
V
= 3V
GS
o
T
= 175 C
J
o
T
= 25 C
J
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
o
T
= -55 C
J
o
T
= 25 C
C
1
2
3
4
0
0.5
V , DRAIN TO SOURCE VOLTAGE (V)
DS
1.0
1.5
2.0
V
, GATE TO SOURCE VOLTAGE (V)
GS
Figure 7. Transfer Characteristics
Figure 8. Saturation Characteristics
50
2.5
PULSE DURATION = 80µs
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
DUTY CYCLE = 0.5% MAX
2.0
40
30
20
10
I
= 40A
D
1.5
1.0
0.5
0
I
= 5A
D
V
= 10V, I = 40A
D
GS
-80
-40
0
40
80
120
160
200
2
4
6
8
10
o
V
, GATE TO SOURCE VOLTAGE (V)
T , JUNCTION TEMPERATURE ( C)
GS
J
Figure 9. Drain to Source On Resistance vs Gate
Voltage and Drain Current
Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
©2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FDD24AN06LA0_F085 Rev. C1
Typical Characteristics TC = 25°C unless otherwise noted
1.25
1.00
0.75
0.50
0.25
1.10
1.05
1.00
0.95
0.90
V
= V , I = 250µA
DS D
I
= 250µA
GS
D
-80
-40
0
40
80
120
160
200
-80
-40
0
40
80
120
160
200
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
Figure 11. Normalized Gate Threshold Voltage vs
Junction Temperature
Figure 12. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
2500
10
V
= 30V
DD
C
= C + C
GS GD
ISS
8
1000
C
C
+ C
OSS
DS GD
6
4
2
0
C
= C
GD
RSS
WAVEFORMS IN
DESCENDING ORDER:
100
40
I
I
= 36A
= 5A
D
D
V
= 0V, f = 1MHz
1
GS
0.1
10
60
0
5
10
15
20
25
30
V
, DRAIN TO SOURCE VOLTAGE (V)
Q , GATE CHARGE (nC)
g
DS
Figure 13. Capacitance vs Drain to Source
Voltage
Figure 14. Gate Charge Waveforms for Constant
Gate Current
www.fairchildsemi.com
©2011 Fairchild Semiconductor Corporation
FDD24AN06LA0_F085 Rev. C1
Test Circuits and Waveforms
V
DS
BV
DSS
t
P
L
V
DS
I
VARY t TO OBTAIN
P
AS
+
-
V
DD
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
0V
AS
0
0.01Ω
t
AV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
V
DS
V
Q
DD
g(TOT)
V
DS
L
V
GS
V
= 5V
GS
V
GS
+
Q
gs2
V
DD
-
DUT
V
= 1V
GS
I
g(REF)
0
Q
g(TH)
Q
Q
gs
gd
I
g(REF)
0
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
V
DS
t
t
ON
OFF
t
d(OFF)
t
d(ON)
R
t
t
f
L
r
V
DS
90%
90%
+
V
GS
V
DD
10%
10%
-
0
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
V
10%
GS
0
Figure 19. Switching Time Test Circuit
Figure 20. Switching Time Waveforms
©2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FDD24AN06LA0_F085 Rev. C1
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the
125
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in an
R
= 33.32+ 23.84/(0.268+Area) EQ.2
θJA
R
= 33.32+ 154/(1.73+Area) EQ.3
θJA
application.
Therefore the application’s ambient
100
75
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
(T
– T )
JM
A
(EQ. 1)
P
= -----------------------------
50
DM
Rθ JA
In using surface mount devices such as the TO-252
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of PDM is
complex and influenced by many factors:
25
0.01
(0.0645)
0.1
1
10
(0.645)
(6.45)
(64.5)
2
2
AREA, TOP COPPER AREA in (cm )
Figure 21. Thermal Resistance vs Mounting
Pad Area
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inches square and equation 3 is for area in centimeters
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.
23.84
(0.268 + Area)
R
= 33.32 + ------------------------------------
(EQ. 2)
θ JA
θ JA
Area in Inches Squared
154
= 33.32 + ---------------------------------
(1.73 + Area)
R
(EQ. 3)
Area in Centimeters Squared
www.fairchildsemi.com
©2011 Fairchild Semiconductor Corporation
FDD24AN06LA0_F085 Rev. C1
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The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not
intended to be an exhaustive list of all such trademarks.
®
®
2Cool™
FlashWriter
FPS™
*
PDP SPM™
Power-SPM™
PowerTrench
PowerXS™
The Power Franchise
AccuPower™
Auto-SPM™
AX-CAP™*
The Right Technology for Your Success™
®
®
F-PFS™
®
FRFET
®
SM
BitSiC
Global Power Resource
Green FPS™
Green FPS™ e-Series™
Gmax™
Programmable Active Droop™
TinyBoost™
TinyBuck™
TinyCalc™
®
Build it Now™
CorePLUS™
CorePOWER™
CROSSVOLT™
CTL™
Current Transfer Logic™
DEUXPEED
Dual Cool™
EcoSPARK
QFET
QS™
Quiet Series™
RapidConfigure™
™
®
TinyLogic
GTO™
TINYOPTO™
TinyPower™
TinyPWM™
TinyWire™
IntelliMAX™
ISOPLANAR™
MegaBuck™
MICROCOUPLER™
MicroFET™
®
Saving our world, 1mW/W/kW at a time™
SignalWise™
SmartMax™
®
TranSiC
®
TriFault Detect™
TRUECURRENT *
EfficentMax™
ESBC™
MicroPak™
SMART START™
®
®
MicroPak2™
MillerDrive™
MotionMax™
Motion-SPM™
mWSaver™
SPM
μSerDes™
STEALTH™
®
®
SuperFET
®
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
Fairchild
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FACT
FAST
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®*
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tm
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