FDD3682 [ONSEMI]
N沟道Power Trench® MOSFET，100V，32A，0.036 ohm;
| 型号： | FDD3682 |
| 厂家： | 
ONSEMI |
| 描述： | N沟道Power Trench® MOSFET，100V，32A，0.036 ohm 开关 晶体管 |
| 文件： | 总13页 (文件大小：445K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Is Now Part of
To learn more about ON Semiconductor, please visit our website at
www.onsemi.com
Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers
will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor
product management systems do not have the ability to manage part nomenclature that utilizes an underscore
(_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain
device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated
device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please
email any questions regarding the system integration to Fairchild_questions@onsemi.com.
ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number
of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right
to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON
Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON
Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA
Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended
or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out
of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor
is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
March 2015
FDD3682
N-Channel PowerTrench® MOSFET
100V, 32A, 36mΩ
Features
Applications
•
•
•
•
•
•
rDS(ON) = 32mΩ (Typ.), VGS = 10V, ID = 32A
Qg(tot) = 18.5nC (Typ.), VGS = 10V
Low Miller Charge
•
•
•
•
•
•
•
DC/DC converters and Off-Line UPS
Distributed Power Architectures and VRMs
Primary Switch for 24V and 48V Systems
High Voltage Synchronous Rectifier
Direct Injection / Diesel Injection System
42V Automotive Load Control
Low QRR Body Diode
UIS Capability (Single Pulse and Repetitive Pulse)
Qualified to AEC Q101
Formerly developmental type 82755
Electronic Valve Train System
DRAIN
(FLANGE)
D
GATE
G
SOURCE
TO-252AA
FDD SERIES
S
MOSFET Maximum Ratings TC = 25°C unless otherwise noted
Symbol
VDSS
VGS
Parameter
Ratings
100
Units
Drain to Source Voltage
Gate to Source Voltage
Drain Current
V
V
±20
Continuous (TC = 25oC, VGS = 10V)
Continuous (TC = 100oC, VGS = 10V)
Continuous (Tamb = 25oC, VGS = 10V, RθJA = 52oC/W)
Pulsed
32
23
A
A
ID
5.5
A
Figure 4
55
A
EAS
Single Pulse Avalanche Energy (Note 1)
mJ
Power dissipation
Derate above 25oC
95
W
PD
0.63
W/oC
oC
TJ, TSTG
Operating and Storage Temperature
-55 to 175
Thermal Characteristics
RθJC
RθJA
RθJA
Thermal Resistance Junction to Case TO-252
1.58
100
52
oC/W
oC/W
oC/W
Thermal Resistance Junction to Ambient TO-252
Thermal Resistance Junction to Ambient TO-252, 1in2 copper pad area
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a
copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.
All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems
certification.
©2002 Fairchild Semiconductor Corporation
FDD3682 Rev. 1.2
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
Tape Width
Quantity
FDD3682
FDD3682
TO-252AA
330mm
16mm
2500 units
Electrical Characteristics TC = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
ID = 250µA, VGS = 0V
100
-
-
-
-
-
V
VDS = 80V
-
-
-
1
IDSS
µA
VGS = 0V
TC = 150oC
250
±100
IGSS
VGS = ±20V
nA
On Characteristics
VGS(TH)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250µA
2
-
-
4
V
ID = 32A, VGS = 10V
0.032
0.040
0.036
0.060
I
D = 16A, VGS = 6V
-
rDS(ON)
Drain to Source On Resistance
Ω
ID = 32A, VGS = 10V,
TC = 175oC
-
0.080
0.090
Dynamic Characteristics
CISS
Input Capacitance
-
-
-
-
-
-
-
-
1250
190
45
-
-
pF
pF
pF
nC
nC
nC
nC
nC
VDS = 25V, VGS = 0V,
f = 1MHz
COSS
CRSS
Qg(TOT)
Qg(TH)
Qgs
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge at 10V
Threshold Gate Charge
-
VGS = 0V to 10V
18.5
2.4
28
3.6
-
VGS = 0V to 2V
VDD = 50V
ID = 32A
Gate to Source Gate Charge
Gate Charge Threshold to Plateau
Gate to Drain “Miller” Charge
6.5
Ig = 1.0mA
Qgs2
4.1
-
Qgd
4.6
-
Resistive Switching Characteristics (VGS = 10V)
tON
td(ON)
tr
Turn-On Time
Turn-On Delay Time
Rise Time
-
-
-
-
-
-
-
83
-
ns
ns
ns
ns
ns
ns
9
46
24
26
-
-
VDD = 50V, ID = 32A
VGS = 10V, RGS = 16Ω
td(OFF)
tf
Turn-Off Delay Time
Fall Time
-
-
tOFF
Turn-Off Time
75
Drain-Source Diode Characteristics
ISD = 32A
-
-
-
-
-
-
-
-
1.25
1.0
55
V
V
VSD
Source to Drain Diode Voltage
ISD = 16A
trr
Reverse Recovery Time
Reverse Recovery Charge
ISD = 32A, dISD/dt = 100A/µs
ISD = 32A, dISD/dt = 100A/µs
ns
nC
QRR
92
Notes:
1: Starting T = 25°C, L = 0.27mH, I = 20A.
J
AS
©2002 Fairchild Semiconductor Corporation
FDD3682 Rev. 1.2
Typical Characteristics TC = 25°C unless otherwise noted
1.2
35
V
= 10V
GS
30
25
20
15
10
5
1.0
0.8
0.6
0.4
0.2
0
0
150
0
25
50
75
100
175
125
o
25
50
75
100
125
150
175
o
T
, CASE TEMPERATURE ( C)
C
T
, CASE TEMPERATURE ( C)
C
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
1
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t /t
SINGLE PULSE
1
2
PEAK T = P
x Z
x R
+ T
θJC C
J
DM
θJC
0.01
-4
-3
-2
-1
0
1
-5
10
10
10
t, RECTANGULAR PULSE DURATION (s)
10
10
10
10
Figure 3. Normalized Maximum Transient Thermal Impedance
400
o
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
T = 25 C
C
FOR TEMPERATURES
o
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
175 - T
150
C
I = I
25
V
= 10V
GS
100
30
-5
-4
-3
-2
-1
0
1
10
10
10
10
t, PULSE WIDTH (s)
10
10
10
Figure 4. Peak Current Capability
©2002 Fairchild Semiconductor Corporation
FDD3682 Rev. 1.2
Typical Characteristics TC = 25°C unless otherwise noted
100
200
100
10µs
If R = 0
= (L)(I )/(1.3*RATED BV
t
- V
DD
)
AV
AS
DSS
If R ≠ 0
AV
100µs
t
= (L/R)ln[(I *R)/(1.3*RATED BV
- V ) +1]
DSS DD
AS
1ms
10ms
10
o
STARTING T = 25 C
J
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
DS(ON)
1
SINGLE PULSE
o
STARTING T = 150 C
J
DC
T
= MAX RATED
J
o
T
= 25 C
C
1
0.1
200
1
10
, DRAIN TO SOURCE VOLTAGE (V)
100
0.001
0.01
t
0.1
, TIME IN AVALANCHE (ms)
1
10
V
AV
DS
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching
Capability
Figure 5. Forward Bias Safe Operating Area
80
80
PULSE DURATION = 80µs
V
= 20V
GS
DUTY CYCLE = 0.5% MAX
V
= 10V
= 6V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
GS
V
= 15V
DD
60
40
20
0
60
40
20
0
o
T
= 25 C
C
V
GS
o
T
= 175 C
J
o
T
= 25 C
J
o
V
= 5V
T
= -55 C
GS
J
0
1
2
3
4
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
V
, GATE TO SOURCE VOLTAGE (V)
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
GS
Figure 7. Transfer Characteristics
Figure 8. Saturation Characteristics
60
50
40
30
20
3.0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80ms
DUTY CYCLE = 0.5% MAX
2.5
2.0
1.5
1.0
0.5
VGS = 6V
VGS = 10V
V
= 10V, I =32A
D
GS
-80
-40
0
40
80
120
160
200
0
5
10
15
20
25
30
35
o
T , JUNCTION TEMPERATURE ( C)
Id, DRAIN CURRENT (A)
J
Figure 9. Drain to Source On Resistance vs Drain
Current
Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
©2002 Fairchild Semiconductor Corporation
FDD3682 Rev. 1.2
Typical Characteristics TC = 25°C unless otherwise noted
1.2
1.0
0.8
0.6
0.4
1.2
1.1
1.0
0.9
V
= V , I = 250µA
DS D
GS
I
= 250µA
D
-80
-40
0
40
80
120
160
200
-80
-40
0
40
80
120
160
200
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
Figure 11. Normalized Gate Threshold Voltage vs
Junction Temperature
Figure 12. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
2000
1000
10
V
= 50V
DD
C
= C + C
GS GD
ISS
8
6
4
2
0
C
C
+ C
OSS
DS GD
C
= C
GD
RSS
100
20
WAVEFORMS IN
DESCENDING ORDER:
I
I
= 32A
= 16A
D
D
V
= 0V, f = 1MHz
1
GS
0.1
10
100
0
5
10
Qg, GATE CHARGE (nC)
15
20
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
Figure 13. Capacitance vs Drain to Source
Voltage
Figure 14. Gate Charge Waveforms for Constant
Gate Currents
©2002 Fairchild Semiconductor Corporation
FDD3682 Rev. 1.2
Test Circuits and Waveforms
V
BV
DSS
DS
t
P
V
DS
L
I
AS
V
DD
VARY t TO OBTAIN
P
+
-
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
0V
0
AS
0.01Ω
t
AV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
V
DS
V
Q
DD
g(TOT)
V
DS
L
V
= 10V
GS
V
GS
+
V
DD
V
GS
-
V
= 2V
DUT
GS
Q
gs2
0
I
g(REF)
Q
g(TH)
Q
Q
gd
gs
I
g(REF)
0
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
V
DS
t
t
ON
OFF
t
d(OFF)
t
d(ON)
R
t
t
f
L
r
V
0
DS
90%
90%
+
V
GS
V
DD
10%
10%
-
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
Figure 19. Switching Time Test Circuit
Figure 20. Switching Time Waveforms
©2002 Fairchild Semiconductor Corporation
FDD3682 Rev. 1.2
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the
125
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in an
R
= 33.32+ 23.84/(0.268+Area) EQ.2
= 33.32+ 154/(1.73+Area) EQ.3
θJA
R
application.
Therefore the application’s ambient
θJA
100
75
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
(T
– T )
JM
A
-----------------------------
=
(EQ. 1)
P
50
DM
Rθ JA
In using surface mount devices such as the TO-252
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of PDM is
complex and influenced by many factors:
25
0.01
(0.0645)
0.1
(0.645)
1
10
(6.45)
(64.5)
2
2
AREA, TOP COPPER AREA in (cm )
Figure 21. Thermal Resistance vs Mounting
Pad Area
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inches square and equation 3 is for area in centimeter
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.
23.84
(0.268 + Area)
------------------------------------
R
= 33.32 +
(EQ. 2)
θ JA
θ JA
Area in Inches Squared
154
---------------------------------
R
= 33.32 +
(EQ. 3)
(1.73 + Area)
Area in Centimeters Squared
©2002 Fairchild Semiconductor Corporation
FDD3682 Rev. 1.2
PSPICE Electrical Model
.SUBCKT FDD3682 2 1 3 ;
Ca 12 8 4e-10
rev Jun 2002
Cb 15 14 6e-10
Cin 6 8 1.22e-9
LDRAIN
DPLCAP
DRAIN
2
5
10
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
RLDRAIN
RSLC1
51
DBREAK
+
RSLC2
5
ESLC
11
51
Ebreak 11 7 17 18 112
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
-
+
50
-
17
DBODY
RDRAIN
6
8
EBREAK 18
-
ESG
EVTHRES
+
16
21
+
-
19
8
MWEAK
LGATE
EVTEMP
RGATE
GATE
1
6
+
-
18
22
It 8 17 1
MMED
9
20
MSTRO
8
RLGATE
Lgate 1 9 4.88e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 2.24e-9
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RLSOURCE
RLgate 1 9 48.8
RLdrain 2 5 10
RLsource 3 7 22.4
S1A
S2A
RBREAK
12
15
13
8
14
13
17
18
RVTEMP
19
-
S1B
S2B
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
13
CB
CA
IT
14
+
+
VBAT
6
8
5
8
EGS
EDS
+
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 10.5e-3
Rgate 9 20 1.8
-
-
8
22
RVTHRES
RSLC1 5 51 RSLCMOD 1.0e-6
RSLC2 5 50 1.0e3
Rsource 8 7 RsourceMOD 11.9e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*70),2.5))}
.MODEL DbodyMOD D (IS=2.4E-12 RS=4.4e-3 TRS1=2.0e-3 TRS2=4.5e-7
+ CJO=9e-10 M=0.58 TT=2.9e-8 XTI=4.0)
.MODEL DbreakMOD D (RS=0.6 TRS1=1.4e-3 TRS2=-5.0e-5)
.MODEL DplcapMOD D (CJO=2.75e-10 IS=1.0e-30 N=10 M=0.56)
.MODEL MstroMOD NMOS (VTO=4.16 KP=32 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MmedMOD NMOS (VTO=3.48 KP=2.7 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.8)
.MODEL MweakMOD NMOS (VTO=2.96 KP=0.068 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=18 RS=0.1)
.MODEL RbreakMOD RES (TC1=1.1e-3 TC2=-1.1e-8)
.MODEL RdrainMOD RES (TC1=1.5e-2 TC2=4e-5)
.MODEL RSLCMOD RES (TC1=3.0e-3 TC2=2.9e-6)
.MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-3.9e-3 TC2=-1.4e-5)
.MODEL RvtempMOD RES (TC1=-3.5e-3 TC2=1.3e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-5.0 VOFF=-2.0)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.0 VOFF=-5.0)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.4 VOFF=0.3)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.3 VOFF=-0.4)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2002 Fairchild Semiconductor Corporation
FDD3682 Rev. 1.2
SABER Electrical Model
REV Jun 2002
template FDD3682 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=2.4e-12,rs=4.4e-3,trs1=2.0e-3,trs2=4.5e-7,cjo=9e-10,m=0.58,tt=2.9e-8,xti=4.0)
dp..model dbreakmod = (rs=0.6,trs1=1.4e-3,trs2=-5e-5)
dp..model dplcapmod = (cjo=2.7e-10,isl=10e-30,nl=10,m=0.56)
m..model mstrongmod = (type=_n,vto=4.16,kp=32,is=1e-30, tox=1)
m..model mmedmod = (type=_n,vto=3.48,kp=2.7,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=2.96,kp=0.068,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-5,voff=-2)
LDRAIN
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2,voff=-5)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.4,voff=0.3)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.3,voff=-0.4)
c.ca n12 n8 = 4e-10
c.cb n15 n14 = 6e-10
c.cin n6 n8 = 1.22e-9
DPLCAP
DRAIN
2
5
10
RLDRAIN
RSLC1
51
RSLC2
ISCL
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
DBREAK
11
50
-
RDRAIN
6
8
ESG
DBODY
EVTHRES
+
16
21
+
-
19
8
spe.ebreak n11 n7 n17 n18 = 112
MWEAK
LGATE
EVTEMP
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
RGATE
GATE
1
6
+
-
18
22
EBREAK
+
MMED
9
20
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
MSTRO
8
17
18
-
RLGATE
LSOURCE
CIN
SOURCE
3
7
RSOURCE
i.it n8 n17 = 1
RLSOURCE
S1A
S2A
l.lgate n1 n9 = 4.88e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 2.24e-9
RBREAK
12
15
13
8
14
13
17
18
RVTEMP
19
S1B
S2B
13
CB
res.rlgate n1 n9 = 48.8
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 22.4
CA
IT
14
-
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
22
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
RVTHRES
res.rbreak n17 n18 = 1, tc1=1.1e-3,tc2=-1.1e-8
res.rdrain n50 n16 = 10.5e-3, tc1=1.5e-2,tc2=4e-5
res.rgate n9 n20 = 1.8
res.rslc1 n5 n51 = 1.0e-6, tc1=3.0e-3,tc2=2.9e-6
res.rslc2 n5 n50 = 1.0e3
res.rsource n8 n7 = 11.9e-3, tc1=1e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-3.9e-3,tc2=-1.4e-5
res.rvtemp n18 n19 = 1, tc1=-3.5e-3,tc2=1.3e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/70))** 2.5))
}
}
©2002 Fairchild Semiconductor Corporation
FDD3682 Rev. 1.2
SPICE Thermal Model
JUNCTION
th
REV 20 Jun 2002
FDD3682_JC TH TL
CTHERM1 TH 6 1.6e-3
CTHERM2 6 5 4.5e-3
CTHERM3 5 4 5.0e-3
CTHERM4 4 3 8.0e-3
CTHERM5 3 2 8.2e-3
CTHERM6 2 TL 4.7e-2
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
CTHERM1
6
RTHERM1 TH 6 3.3e-2
RTHERM2 6 5 7.9e-2
RTHERM3 5 4 9.5e-2
RTHERM4 4 3 1.4e-1
RTHERM5 3 2 2.9e-1
RTHERM6 2 TL 6.7e-1
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
5
SABER Thermal Model
SABER thermal model FDD3682
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 =1.6e-3
ctherm.ctherm2 6 5 =4.5e-3
ctherm.ctherm3 5 4 =5.0e-3
ctherm.ctherm4 4 3 =8.0e-3
ctherm.ctherm5 3 2 =8.2e-3
ctherm.ctherm6 2 tl =4.7e-2
4
3
2
rtherm.rtherm1 th 6 =3.3e-2
rtherm.rtherm2 6 5 =7.9e-2
rtherm.rtherm3 5 4 =9.5e-2
rtherm.rtherm4 4 3 =1.4e-1
rtherm.rtherm5 3 2 =2.9e-1
rtherm.rtherm6 2 tl =6.7e-1
}
tl
CASE
©2002 Fairchild Semiconductor Corporation
FDD3682 Rev. 1.2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
© Semiconductor Components Industries, LLC
www.onsemi.com
相关型号：
FDD3682_F085
Power Field-Effect Transistor, 5.5A I(D), 100V, 0.036ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA, ROHS COMPLIANT PACKAGE-3
FAIRCHILD
FDD3682_NL
Power Field-Effect Transistor, 5.5A I(D), 100V, 0.036ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA, LEAD FREE PACKAGE-3
FAIRCHILD
FDD3690_NL
Power Field-Effect Transistor, 22A I(D), 100V, 0.064ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252, DPAK-3
FAIRCHILD
©2020 ICPDF网 联系我们和版权申明