FDG6320C [ONSEMI]
双 N 和 P 沟道 数字 FET，25V;
| 型号： | FDG6320C |
| 厂家： | 
ONSEMI |
| 描述： | 双 N 和 P 沟道 数字 FET，25V PC 开关 光电二极管 晶体管 |
| 文件： | 总11页 (文件大小：322K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Digital FET, Dual N & P
Channel
FDG6320C
General Description
These dual N & P−Channel logic level enhancement mode field
effect transistors are produced using ON Semiconductor’s proprietary,
high cell density, DMOS technology, this very high density process is
especially tailored to minimize on−state resistance. This device has
been designed especially for low voltage applications as a replacement
for bipolar digital transistors and small signal MOSFETS. Since bias
resistors are not required, this dual digital FET can replace several
different digital transistors, with different bias resistor values.
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S2
G2
D1
D2
G1
S1
Pin 1
SC−88/SC70−6/SOT−363
CASE 419B−02
Features
• N−Ch 0.22 A, 0.25 V
MARKING DIAGRAM
♦ R
♦ R
= 4.0 W @ V = 4.5 V
GS
DS(ON)
= 5.0 W @ V = 2.7 V
DS(ON)
GS
20M
• P−Ch −0.14 A, −25 V
♦ R
♦ R
= 10 W @ V = −4.5 V
GS
= 13 W @ V = −2.7 V
DS(ON)
DS(ON)
GS
20
M
= Specific Device Code
= Assembly Operation Month
• Very Small Package Outline SC70−6
• Very Low Level Gate Drive Requirements Allowing Direct
Operation in 3 V Circuits (V
< 1.5 V)
GS(th)
PIN CONNECTIONS
• Gate−Source Zener for ESD Ruggedness (>6 kV Human Body
Model)
• These Devices are Pb−Free and are RoHS Compliant
1
6
ABSOLUTE MAXIMUM RATINGS (T = 25°C unless otherwise noted)
A
2
3
5
4
Symbol
Parameter
Drain−Source Voltage
Gate−Source Voltage
Drain Current Continuous
Pulsed
N−Channel P−Channel Units
V
25
8
−25
−8
V
V
A
DSS
GSS
V
I
D
0.22
0.65
−0.14
−0.4
ORDERING INFORMATION
See detailed ordering and shipping information on page 8 of
this data sheet.
P
Maximum Power Dissipation
(Note 1)
0.3
W
°C
kV
D
T , T
Operating and Storage
Temperature Range
−55 to 150
J
STG
ESD
Electrostatic Discharge
Rating MIL−STD−883D
Human Body Model (100 pF /
1500 W)
6
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
© Semiconductor Components Industries, LLC, 1998
1
Publication Order Number:
June, 2020 − Rev. 5
FDG6320C/D
FDG6320C
THERMAL CHARACTERISTICS
Symbol
Parameter
Ratings
Unit
R
Thermal Resistance, Junction−to−Ambient (Note 1)
415
_C/W
q
JA
1. R
is the sum of the junction−to−case and case−to−ambient thermal resistance where the case thermal reference is defined as the solder
q
JA
mounting surface of the drain pins. R
is guaranteed by design while R
is determined by the user’s board design. R
= 415°C/W on
q
q
q
JC
CA
JA
minimum pad mounting on FR−4 board in still air.
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
A
Symbol
Parameter
Conditions
Type
Min
Typ
Max
Unit
V
OFF CHARACTERISTICS
BV
Drain−Source Breakdown Voltage
N−Ch
P−Ch
N−Ch
P−Ch
N−Ch
25
−25
−
−
−
−
−
V
V
I
= 0 V, I = 250 mA
DSS
GS
D
= 0 V, I = −250 mA
GS
D
DBV
/ DT
Breakdown Voltage Temperature
Coefficient
= 250 mA, Referenced to 25_C
= −250 mA, Referenced to 25_C
25
−19
−
−
mV/_C
mA
DSS
J
D
I
D
−
−
I
I
Zero Gate Voltage Drain Current
Zero Gate Voltage Drain Current
Gate−Body Leakage Current
V
DS
V
DS
V
DS
V
DS
V
GS
V
GS
= 20 V, V = 0 V
−
1
DSS
GS
= 20 V, V = 0 V, T = 55_C
−
−
10
−1
−10
100
GS
J
= −20 V, V = 0 V
P−Ch
−
−
mA
DSS
GS
= −20 V, V = 0 V, T = 55_C
−
−
GS
J
I
= 8 V, V = 0 V
N−Ch
P−Ch
−
−
nA
GSS
DS
= −8 V, V = 0 V
−
−
−100
DS
ON CHARACTERISTICS (Note 2)
Gate Threshold Voltage
V
GS(th)
N−Ch
P−Ch
N−Ch
P−Ch
N−Ch
0.65
0.85
−0.82
−2.1
2.1
1.5
−1.5
−
V
mV/_C
W
V
V
I
= V , I = 250 mA
DS
GS
D
= V , I = −250 mA
−0.65
DS
GS
D
DV
/ DT
Gate Threshold Voltage
Temperature Coefficient
= 250 mA, Referenced to 25_C
= −250 mA, Referenced to 25_C
−
−
−
−
GS(th)
J
D
I
D
−
R
Static Drain−Source
On−Resistance
V
GS
= 4.5 V, I = 0.22 A
2.6
4
DS(ON)
D
V
GS
= 4.5 V, I = 0.22 A,
5.3
7
D
T = 125_C
J
V
GS
V
GS
V
GS
= 2.7 V, I = 0.19 A
−
−
−
3.7
7.3
11
5
D
= −4.5 V, I = −0.14 A
P−Ch
10
17
D
= −4.5 V, I = −0.14 A,
D
T = 125_C
J
V
GS
V
GS
V
GS
V
DS
V
DS
= −2.7 V, I = −0.05 A
−
0.22
−0.14
−
10.4
−
13
−
D
I
On−State Drain Current
= 4.5 V, V = 5 V
N−Ch
P−Ch
N−Ch
P−Ch
A
S
D(ON)
DS
= −4.5 V, V = −5 V
−
−
DS
g
FS
Forward Transconductance
= 5 V, I = 0.22 A
0.2
0.12
−
D
= −5 V, I = −0.14 A
−
−
D
DYNAMIC CHARACTERISTICS
C
Input Capacitance
N−Channel
= 10 V, V = 0 V, f = 1.0 MHz
N−Ch
P−Ch
N−Ch
P−Ch
N−Ch
P−Ch
−
−
−
−
−
−
9.5
12
6
−
−
−
−
−
−
pF
iss
V
DS
GS
P−Channel
= −10 V, V = 0 V,
C
Output Capacitance
oss
V
DS
GS
f = 1.0 MHz
7
C
Reverse Transfer Capacitance
1.3
1.5
rss
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2
FDG6320C
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted) (continued)
A
Symbol
SWITCHING CHARACTERISTICS (Note 2)
Parameter
Conditions
Type
Min
Typ
Max
Unit
ns
t
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Total Gate Charge
Gate−Source Charge
Gate−Drain Charge
N−Channel
N−Ch
P−Ch
N−Ch
P−Ch
N−Ch
P−Ch
N−Ch
P−Ch
N−Ch
P−Ch
N−Ch
P−Ch
N−Ch
P−Ch
−
−
−
−
−
−
−
−
−
−
−
−
−
−
5
5
12
12
10
16
8
D(on)
V
DD
V
GS
= 5 V, I = 0.5 A,
D
= 4.5 V, R
= 50 W
GEN
t
r
4.5
8
ns
P−Channel
V
DD
V
GS
= −5 V, I = −0.5 A,
D
= −4.5 V, R
= 50 W
GEN
t
4
ns
D(off)
9
18
7
t
f
3.2
5
ns
12
0.4
0.31
−
Q
N−Channel
0.29
0.22
0.12
0.12
0.03
0.05
nC
nC
nC
g
V
DS
V
GS
= 5 V, I = 0.22 A,
D
= 4.5 V
Q
gs
P−Channel
V
DS
V
GS
= −5 V, I =−0.14 A,
D
−
= −4.5 V
Q
−
gd
−
DRAIN−SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
Maximum Continuous Source Current
I
S
N−Ch
P−Ch
N−Ch
P−Ch
−
−
−
−
−
−
0.25
−0.25
1.2
A
V
V
SD
Drain−Source Diode Forward
Voltage
V
GS
= 0 V, I = 0.5 A (Note 2)
0.8
−0.8
S
V
GS
= 0 V, I = −0.5 A (Note 2)
−1.2
S
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2.0%
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3
FDG6320C
TYPICAL PERFORMANCE CHARACTERISTICS: N−CHANNEL
5
0.5
0.4
0.3
0.2
0.1
0
V
=4.5 V
GS
3.5 V
4.5
4
V
= 2.5 V
GS
3.0 V
2.7 V
2.7 V
3.0 V
3.5
3
2.5 V
3.5 V
4.0 V
0.3
4.5 V
2.0 V
5.0 V
2.5
2
0
0.1
0.2
, DRAIN CURRENT (A)
0.4
0
1
2
3
4
5
I
V
, DRAIN−SOURCE VOLTAGE (V)
D
DS
Figure 1. On−Region Characteristics
Figure 2. On−Resistance Variation with
Drain Current and Gate Voltage
20
1.8
1.6
1.4
1.2
1
I
= 0.22 A
I
D
= 0.10 A
D
V
= 4.5 V
GS
16
12
8
T
=125°C
25°C
A
0.8
4
0.6
0
−50
−25
0
25
50
75
100
125
150
1
2
3
4
5
T
, JUNCTION TEMPERATURE (°C)
V
, GATE TO SOURCE VOLTAGE (V)
J
GS
Figure 3. On−Resistance Variation with
Figure 4. On−Resistance Variation with
Gate−to−Source Voltage
Temperature
0.4
0.2
T
= -55°C
V
= 0 V
V
= 5 V
J
GS
DS
25°C
125°C
0.1
0.15
0.1
0.05
0
T = 125°C
J
0.01
25°C
−55°C
0.001
0.0001
0
0.2
V
0.4
0.6
0.8
1
1.2
0.5
1
1.5
2
2.5
3
, BODY DIODE FORWARD VOLTAGE (V)
V
, GATE TO SOURCE VOLTAGE (V)
SD
GS
Figure 5. Transfer Characteristics
Figure 6. Body Diode Forward Voltage
Variation with Source Current and Temperature
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4
FDG6320C
TYPICAL PERFORMANCE CHARACTERISTICS: N−CHANNEL (continued)
30
6
5
4
3
2
1
0
VDS = 5 V
I D = 0.22 A
10 V
15
C
iss
8
5
C
oss
C
rss
f = 1 MHz
3
2
V
= 0 V
GS
0.1
0.3
1
3
10
25
0
0.1
0.2
Q
0.3
0.4
0.5
0.6
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
, GATE CHARGE (nC)
g
Figure 7. Gate Charge Characteristics
Figure 8. Capacitance Characteristics
1
50
40
30
20
10
SINGLE PULSE
R
= 415°C/W
q
JA
T
A
= 25°C
0.3
0.1
V
= 4.5 V
GS
SINGLE PULSE
R
T
A
0.03
0.01
= 415°C/W
= 25°C
q
JA
0
0.0001
0.001
0.01
0.1
1
10
200
0.4
0.8
2
5
10
25
40
SINGLE PULSE TIME (sec)
V
, DRAIN−SOURCE VOLTAGE (V)
DS
Figure 9. Maximum Safe Operating Area
Figure 10. Single Pulse Maximum Power
Dissipation
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5
FDG6320C
TYPICAL PERFORMANCE CHARACTERISTICS: P−CHANNEL
2.5
0.2
0.15
0.1
V
= −4.5 V
GS
V
= −2.0 V
GS
−3.5 V
−3.0 V
−2.7 V
2
1.5
1
−2.5 V
−2.7 V
−2.5 V
−3.0 V
−3.5 V
−2.0 V
−4.0 V
−4.5 V
0.05
0
0.5
0
1
2
3
4
0
0.05
0.1
−I , DRAIN CURRENT (A)
0.15
0.2
−V , DRAIN−SOURCE VOLTAGE (V)
DS
D
Figure 11. On−Region Characteristics
Figure 12. On−Resistance Variation
with Drain Current and Gate Voltage
25
20
15
10
5
1.6
1.4
1.2
1
I
= −0.07 A
D
I
= −0.14 A
= −4.5 V
D
V
GS
T
= 125°C
A
T
= 25°C
A
0.8
0.6
0
−50
−25
0
25
50
75
100
125
150
1.5
2
2.5
3
3.5
4
4.5
5
T , JUNCTION TEMPERATURE (°C)
−V
GS
, GATE TO SOURCE VOLTAGE (V)
J
Figure 13. On−Resistance Variation with
Figure 14. On−Resistance Variation
with Gate−to−Source Voltage
Temperature
0.3
0.14
V = 0 V
GS
V
= −5.0 V
DS
T
= −55°C
A
0.1
0.12
0.1
25°C
125°C
T
A
= 125°C
25°C
−55°C
0.01
0.001
0.08
0.06
0.04
0.02
0
0.0001
0.2
0.4
0.6
0.8
1
1.2
0
1
2
3
4
−V , BODY DIODE FORWARD VOLTAGE (V)
−V , GATE TO SOURCE VOLTAGE (V)
GS
SD
Figure 15. Transfer Characteristics
Figure 16. Body Diode Forward Voltage
Variation with Source Current and Temperature
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6
FDG6320C
TYPICAL PERFORMANCE CHARACTERISTICS: P−CHANNEL (continued)
8
6
4
2
0
40
ID = −0.14 A
VDS= −5 V
20
−10 V
−15 V
C
iss
10
C
oss
5
3
C
rss
1
f = 1 MHz
VGS = 0 V
0.5
0.1
0.2
0.5
1
2
5
10
20
0
0.1
0.2
0.3
0.4
0.5
−VDS , DRAIN TO SOURCE VOLTAGE (V)
Q
, GATE CHARGE (nC)
g
Figure 17. Gate Charge Characteristics
Figure 18. Capacitance Characteristics
1
50
40
30
20
10
SINGLE PULSE
R
= 415°C/W
q
JA
0.3
0.1
T
A
= 25°C
0.03
V
= −4.5 V
GS
SINGLE PULSE
= See Note 1b
R
q
JA
T
A
= 25°C
0
0.005
0.0001
0.001
0.01
0.1
1
10
200
1
2
3
5
10
20
40
SINGLE PULSE TIME (sec)
− V
, DRAIN−SOURCE VOLTAGE (V)
DS
Figure 19. Maximum Safe Operating Area
Figure 20. Single Pulse Maximum Power
Dissipation
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7
FDG6320C
TYPICAL PERFORMANCE CHARACTERISTICS: N & P−CHANNEL
1
D = 0.5
0.5
0.2
0.1
0.05
R
R
(t) = r(t) * R
= 415°C/W
0.2
0.1
qJA
qJA
q
JA
0.05
P(pk)
0.02
0.01
Single Pulse
0.02
0.01
t1
t 2
− T = P * R
q
JA
T
(t)
J
A
0.005
Duty Cycle, D = t / t
1
2
0.002
0.0001
0.001
0.01
0.1
1
10
100 200
t , TIME (sec)
1
Thermal characterization performed using the conditions described in Note 1.
Transient thermal response will change depending on the circuit board design.
Figure 21. Transient Thermal Response Curve
ORDERING INFORMATION
Device Order Number
FDG6320C
†
Device Marking
Package Type
Shipping
20
SC−88/SC70−6/SOT−363
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
1
DATE 11 DEC 2012
SCALE 2:1
2X
aaa H
D
NOTES:
D
H
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
A
3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRU-
SIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.
4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY AND DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.
7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDI-
TION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OF THE FOOT.
D
GAGE
PLANE
6
1
5
2
4
3
L
L2
E1
E
DETAIL A
aaa
C
2X
2X 3 TIPS
bbb H
D
e
MILLIMETERS
DIM MIN NOM MAX
−−−
INCHES
MIN
−−−
NOM MAX
−−− 0.043
−−− 0.004
6X b
B
TOP VIEW
A
−−−
−−−
1.10
A1 0.00
A2 0.70
0.10 0.000
M
ddd
C A-B D
0.90
0.20
0.15
2.00
2.10
1.25
0.65 BSC
0.36
1.00 0.027 0.035 0.039
0.25 0.006 0.008 0.010
0.22 0.003 0.006 0.009
2.20 0.070 0.078 0.086
2.20 0.078 0.082 0.086
1.35 0.045 0.049 0.053
0.026 BSC
b
C
D
E
0.15
0.08
1.80
2.00
A2
DETAIL A
A
E1 1.15
e
L
0.26
0.46 0.010 0.014 0.018
0.006 BSC
L2
0.15 BSC
0.15
aaa
bbb
ccc
ddd
0.006
0.012
0.004
0.004
0.30
0.10
0.10
6X
ccc C
A1
SEATING
PLANE
c
C
SIDE VIEW
END VIEW
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
6
6X
0.30
XXXMG
6X
0.66
G
1
2.50
XXX = Specific Device Code
M
= Date Code*
G
= Pb−Free Package
0.65
(Note: Microdot may be in either location)
PITCH
*Date Code orientation and/or position may
vary depending upon manufacturing location.
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42985B
SC−88/SC70−6/SOT−363
PAGE 1 OF 2
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© Semiconductor Components Industries, LLC, 2019
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SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
DATE 11 DEC 2012
STYLE 1:
PIN 1. EMITTER 2
2. BASE 2
STYLE 2:
CANCELLED
STYLE 3:
CANCELLED
STYLE 4:
STYLE 5:
STYLE 6:
PIN 1. ANODE 2
2. N/C
PIN 1. CATHODE
2. CATHODE
3. COLLECTOR
4. EMITTER
5. BASE
PIN 1. ANODE
2. ANODE
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
3. COLLECTOR
3. CATHODE 1
4. ANODE 1
5. N/C
4. EMITTER
5. BASE
6. COLLECTOR 2
6. ANODE
6. CATHODE
6. CATHODE 2
STYLE 7:
STYLE 8:
CANCELLED
STYLE 9:
STYLE 10:
STYLE 11:
STYLE 12:
PIN 1. SOURCE 2
2. DRAIN 2
3. GATE 1
PIN 1. EMITTER 2
2. EMITTER 1
3. COLLECTOR 1
4. BASE 1
PIN 1. SOURCE 2
2. SOURCE 1
3. GATE 1
PIN 1. CATHODE 2
2. CATHODE 2
3. ANODE 1
PIN 1. ANODE 2
2. ANODE 2
3. CATHODE 1
4. ANODE 1
5. ANODE 1
6. CATHODE 2
4. SOURCE 1
5. DRAIN 1
6. GATE 2
4. DRAIN 1
5. DRAIN 2
6. GATE 2
4. CATHODE 1
5. CATHODE 1
6. ANODE 2
5. BASE 2
6. COLLECTOR 2
STYLE 13:
PIN 1. ANODE
2. N/C
STYLE 14:
PIN 1. VREF
2. GND
STYLE 15:
STYLE 16:
STYLE 17:
STYLE 18:
PIN 1. VIN1
2. VCC
PIN 1. ANODE 1
2. ANODE 2
PIN 1. BASE 1
2. EMITTER 2
3. COLLECTOR 2
4. BASE 2
PIN 1. BASE 1
2. EMITTER 1
3. COLLECTOR 2
4. BASE 2
3. COLLECTOR
4. EMITTER
5. BASE
3. GND
3. ANODE 3
3. VOUT2
4. VIN2
5. GND
6. VOUT1
4. IOUT
5. VEN
6. VCC
4. CATHODE 3
5. CATHODE 2
6. CATHODE 1
5. EMITTER 1
6. COLLECTOR 1
5. EMITTER 2
6. COLLECTOR 1
6. CATHODE
STYLE 19:
PIN 1. I OUT
2. GND
STYLE 20:
STYLE 21:
PIN 1. ANODE 1
2. N/C
STYLE 22:
PIN 1. D1 (i)
2. GND
STYLE 23:
PIN 1. Vn
2. CH1
3. Vp
STYLE 24:
PIN 1. CATHODE
2. ANODE
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
3. GND
3. ANODE 2
4. CATHODE 2
5. N/C
3. D2 (i)
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
4. V CC
4. EMITTER
5. COLLECTOR
6. COLLECTOR
4. D2 (c)
5. VBUS
6. D1 (c)
4. N/C
5. V EN
5. CH2
6. N/C
6. V REF
6. CATHODE 1
STYLE 30:
STYLE 25:
STYLE 26:
PIN 1. SOURCE 1
2. GATE 1
STYLE 27:
PIN 1. BASE 2
2. BASE 1
STYLE 28:
PIN 1. DRAIN
2. DRAIN
3. GATE
STYLE 29:
PIN 1. ANODE
2. ANODE
PIN 1. SOURCE 1
2. DRAIN 2
3. DRAIN 2
4. SOURCE 2
5. GATE 1
PIN 1. BASE 1
2. CATHODE
3. COLLECTOR 2
4. BASE 2
3. DRAIN 2
4. SOURCE 2
5. GATE 2
3. COLLECTOR 1
4. EMITTER 1
5. EMITTER 2
6. COLLECTOR 2
3. COLLECTOR
4. EMITTER
5. BASE/ANODE
6. CATHODE
4. SOURCE
5. DRAIN
6. DRAIN
5. EMITTER
6. COLLECTOR 1
6. DRAIN 1
6. DRAIN 1
Note: Please refer to datasheet for
style callout. If style type is not called
out in the datasheet refer to the device
datasheet pinout or pin assignment.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42985B
SC−88/SC70−6/SOT−363
PAGE 2 OF 2
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