FDH047AN08A0 [ONSEMI]
N 沟道,PowerTrench® MOSFET,75V,80A,4.7mΩ;型号: | FDH047AN08A0 |
厂家: | ONSEMI |
描述: | N 沟道,PowerTrench® MOSFET,75V,80A,4.7mΩ 局域网 开关 晶体管 |
文件: | 总15页 (文件大小:779K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
MOSFET – N-Channel,
POWERTRENCH)
V
R
MAX
I MAX
D
DSS
DS(ON)
75 V
4.7 mW
80 A
75 V, 80 A, 4.7 mW
D
S
FDH047AN08A0,
FDP047AN08A0
G
Features
R
Q
= 4.0 mW (Typ.), V = 10 V, I = 80 A
GS D
DS(ON)
g(TOT)
= 92 nC (Typ.), V = 10 V
GS
TO−247−3
CASE 340CK
Low Miller Charge
Low Q Body Diode
UIS Capability (Single Pulse and Repetitive Pulse)
This Device is Pb−Free and is RoHS Compliant
G
rr
D
D
S
TO−220−3
CASE 340AT
Applications
G
Synchronous Rectification for ATX / Server / Telecom PSU
Battery Protection Circuit
S
Motor Drives and Uninterruptible Power Supplies
MARKING DIAGRAM
&Z&3&K
FDX047AN
08A0
&Z
&3
&K
= Assembly Plant Code
= Data Code (Year & Week)
= Lot
FDX047AN08A0
X
= Specific Device Code
= H/P
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
Semiconductor Components Industries, LLC, 2003
1
Publication Order Number:
April, 2023 − Rev. 5
FDH047AN08A0/D
FDH047AN08A0, FDP047AN08A0
MOSFET MAXIMUM RATINGS (T = 25C, Unless otherwise noted)
C
Symbol
Parameter
Value
75
Unit
V
V
DSS
Drain to Source Voltage
Gate to Source Voltage
Drain Current
V
GS
20
80
V
I
D
− Continuous (T < 144C, V = 10 V)
A
C
GS
− Continuous (T = 25C, V = 10 V,
15
C
GS
R
= 62C/W)
q
JA
I
Drain Current
− Pulsed
Figure 4
475
A
mJ
W
D
E
AS
Single Pulse Avalanche Energy (Note 1)
Power Dissipation
P
310
D
Derate Above 25C
2.0
W/C
C
T , T
Operating and Storage Temperature Range
−55 to +175
J
STG
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Starting T = 25C, L = 0.232 mH, I = 64 A.
J
AS
THERMAL CHARACTERISTICS
Symbol
Parameter
Value
0.48
62
Unit
R
q
JC
R
q
JA
R
q
JA
Thermal Resistance, Junction to Case, Max. TO−220, TO−247
Thermal Resistance, Junction to Ambient, Max. TO−220 (Note 2)
Thermal Resistance, Junction to Ambient, Max. TO−247 (Note 2)
_C/W
_C/W
_C/W
30
2. Pulse Width = 100 s.
PACKAGE MARKING AND ORDERING INFORMATION
Device Marking
FDH047AN08A0
FDP047AN08A0
Device
Package
TO−247
TO−220
Reel Size
Tube
Tape Width
Quantity
FDH047AN08A0
FDP047AN08A0
N/A
N/A
30 Units
50 Units
Tube
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2
FDH047AN08A0, FDP047AN08A0
ELECTRICAL CHARACTERISTICS (T = 25C unless otherwise noted)
C
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
OFF CHARACTERISTICS
B
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
I
= 250 mA, V = 0 V
75
−
−
−
−
−
−
1
V
VDSS
D
GS
I
V
V
V
= 60 V, V = 0 V
mA
DSS
DS
DS
GS
GS
= 60 V, V = 0 V, T = 150_C
−
250
100
GS
C
I
Gate to Source Leakage Current
= 20 V
−
nA
GSS
ON CHARACTERISTICS
V
GS(TH)
R
DS(ON)
Gate to Source Threshold Voltage
Drain to Source On Resistance
V
= V , I = 250 mA
2.0
−
−
4.0
V
GS
DS
D
I
D
I
D
I
D
= 80 A, V = 10 V
0.0040 0.0047
0.0058 0.0087
W
GS
= 37 V, V = 6 V
−
GS
= 80 A, V = 10 V, T = 175 C
−
0.0082
0.011
GS
j
DYNAMIC CHARACTERISTICS
C
Input Capacitance
V
= 25 V, V = 0 V, f = 1 MHz
−
−
−
−
6600
1000
240
92
−
−
pF
pF
pF
nC
ISS
DS
GS
C
OSS
C
RSS
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge at 10 V
−
Q
V
GS
V
DD
= 0 V to 10 V,
138
g(TOT)
= 40 V, I = 80 A, I = 1.0 mA
D
g
Q
Threshold Gate Charge
V
GS
V
DD
= 0 V to 2 V,
−
11
17
nC
g(TH)
= 40 V, I = 80 A, I = 1.0 mA
D
g
Q
Gate to Source Gate Charge
Gate Charge Threshold to Plateau
Gate to Drain “Miller” Charge
V
DD
= 40 V, I = 80 A, I = 1.0 mA
−
−
−
27
16
21
−
−
−
nC
nC
nC
gs
D
g
Q
gs2
Q
gd
SWITCHING CHARACTERISTICS (V = 10 V)
GS
t
Turn-On Time
Turn-On Delay Time
Rise Time
V
DD
V
GS
= 40 V, I = 80 A,
−
−
−
−
−
−
−
160
−
ns
ns
ns
ns
ns
ns
ON
D
= 10 V, R = 3.3 W
GS
t
18
88
40
45
−
d(ON)
t
r
−
t
Turn-Off Delay Time
Fall Time
−
d(OFF)
t
f
−
t
Turn-Off Time
128
OFF
DRAIN−SOURCE DIODE CHARACTERISTICS
V
Source to Drain Diode Voltage
I
I
I
I
= 80 A
= 40 A
−
−
−
−
−
−
−
−
1.25
1
V
V
SD
SD
SD
SD
SD
t
Reverse Recovery Time
= 75 A, dl /dt = 100 A/ms
53
54
ns
nC
rr
SD
Q
Reverse Recovered Charge
= 75 A, dl /dt = 100 A/ms
SD
RR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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3
FDH047AN08A0, FDP047AN08A0
TYPICAL CHARACTERISTICS
(T = 25C UNLESS OTHERWISE NOTED)
C
1.2
1.0
0.8
0.6
0.4
0.2
0
200
160
120
80
CURRENT LIMITED
BY PACKAGE
40
0
0
25
50
75
100
150
175
125
o
25
50
75
T , CASE TEMPERATURE ( C)
C
100
125
150
175
o
T
, CASE TEMPERATURE ( C)
C
Figure 1. Normalized Power
Figure 2. Maximum Continuous
Dissipation vs. Case Temperature
Drain Current vs. Case Temperature
2
DUTY CYCLE − DESCENDING ORDER
0.5
0.2
1
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t /t
1
2
SINGLE PULSE
0.01
PEAK T = P
x Z
Q
x R
+ T
JC C
Q
J
DM
JC
−5
−4
−3
−2
−1
0
1
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
10
10
10
Figure 3. Normalized Maximum Transient Thermal Impedance
2000
1000
o
T
= 25 C
C
FOR TEMPERATURES
o
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
175 − T
C
V
= 10V
I = I
GS
25
150
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
100
50
−5
−4
−3
−2
−1
0
1
10
10
10
10
t, PULSE WIDTH (s)
10
10
10
Figure 4. Peak Current Capability
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4
FDH047AN08A0, FDP047AN08A0
TYPICAL CHARACTERISTICS (CONTINUED)
(T = 25C UNLESS OTHERWISE NOTED)
C
NOTE: Refer to onsemi Application Notes
AN−7514 and AN−7515
500
2000
1000
If R = 0
AV
10ms
t
= (L)(I )/(1.3*RATED BV
− V
)
AS
DSS
DD
If R 0 0
100ms
t
= (L/R)ln[(I *R)/(1.3*RATED BV
− V ) +1]
DSS DD
AV
AS
100
100
10
1
1ms
o
STARTING T = 25 C
J
10ms
OPERATION IN THIS
AREA MAY BE
10
DC
LIMITEDD BY r
DS(ON)
o
STARTING T = 150 C
J
SINGLE PULSE
T
T
= MAX RATED
= 25 C
J
o
C
1
0.1
0.1
1
10
100
.01
0.1
AV
1
10
100
t
, TIME IN AVALANCHE (ms)
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
Figure 5. Forward Bias Safe
Operating Area
Figure 6. Unclamped Inductive
Switching Capability
150
120
90
60
30
0
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
150
120
V
= 10V
V
= 7V
GS
GS
V
= 15V
DD
V
= 6V
GS
90
60
30
0
o
T
= 175 C
J
V
= 5V
o
GS
o
T = −55
C
T
= 25 C
J
J
o
T
= 25 C
C
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
0
0.5
1.0
1.5
4.0
4.5
5.0
5.5
6.0
V
, DRAIN TO SOURCE VOLTAGE (V)
V
, GATE TO SOURCE VOLTAGE (V)
DS
GS
Figure 7. Transfer Characteristics
Figure 8. Saturation Characteristics
7
6
5
4
3
2.5
2.0
1.5
1.0
0.5
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
V
= 6V
GS
V
= 10V
GS
V
= 10V, I = 80A
D
GS
0
2 0
40
, DRAIN CURRENT (A)
60
80
−80
−40
0
40
80
120
160
200
o
I
T , JUNCTION TEMPERATURE ( C)
D
J
Figure 9. Drain to Source On Resistance
vs. Drain Current
Figure 10. Normalized Drain to Source On
Resistance vs. Junction Temperature
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FDH047AN08A0, FDP047AN08A0
TYPICAL CHARACTERISTICS (CONTINUED)
(T = 25C UNLESS OTHERWISE NOTED)
C
1.2
1.0
0.8
0.6
0.4
1.15
V
= V , I = 250 mA
I = 250 mA
D
GS
DS
D
1.10
1.05
1.00
0.95
0.90
−80
−40
0
40
80
120
160
200
−80
−40
0
40
80
120
160
200
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
Figure 11. Normalized Gate Threshold Voltage
vs. Junction Temperature
Figure 12. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
10000
10
V
= 40V
DD
C
= C + C
GS
ISS
GD
8
6
4
2
0
C
^ C + C
OSS
DS
GD
1000
C
= C
GD
RSS
WAVEFORMS IN
DESCENDING ORDER:
I
I
= 80A
= 10A
D
D
V
= 0V, f = 1MHz
1
GS
100
0.1
10
75
0
25
50
Q , GATE CHARGE (nC)
75
100
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
g
Figure 13. Capacitance vs. Drain
to Source Voltage
Figure 14. Gate Charge Waveforms
for Constant Gate Currents
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FDH047AN08A0, FDP047AN08A0
TEST CIRCUITS AND WAVEFORMS
V
DS
L
VARY tp TO OBTAIN
REQUIRED PEAK I
AS
R
G
+
V
DD
DUT
−
V
GS
tp
0 V
I
AS
0.01 W
Figure 15. Unclamped Energy
Test Circuit
Figure 16. Unclamped Energy
Waveforms
V
DS
L
V
GS
+
V
DD
DUT
−
Ig(REF)
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
V
DS
R
L
+
V
GS
V
DD
−
DUT
R
GS
V
GS
Figure 19. Switching Time Test Circuit
Figure 20. Switching Time Waveforms
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FDH047AN08A0, FDP047AN08A0
PSPICE ELECTRICAL MODEL
.SUBCKT FDP047AN08A0 2 1 3 ; rev March 2002
CA 12 8 1.5e−9
CB 15 14 1.5e−9
CIN 6 8 6.4e−9
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 82.3
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN 2 5 1e−9
LGATE 1 9 4.81e−9
LSOURCE 3 7 4.63e−9
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 9e−4
RGATE 9 20 1.36
RLDRAIN 2 5 10
RLGATE 1 9 48.1
RLSOURCE 3 7 46.3
RSLC1 5 51 RSLCMOD 1e−6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 2.3e−3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e−6*250),10))}
.MODEL DBODYMOD D (IS = 2.4e−11 N = 1.04 RS = 1.76e−3 TRS1 = 2.7e−3 TRS2 = 2e−7 XTI=3.9 CJO = 4.35e−9
TT = 1e−8 M = 5.4e−1)
.MODEL DBREAKMOD D (RS = 1.5e−1 TRS1 = 1e−3 TRS2 = −8.9e−6)
.MODEL DPLCAPMOD D (CJO = 1.35e−9 IS = 1e−30 N = 10 M = 0.53)
.MODEL MMEDMOD NMOS (VTO = 3.7 KP = 9 IS =1e−30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.36)
.MODEL MSTROMOD NMOS (VTO = 4.4 KP = 250 IS = 1e−30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 3.05 KP = 0.03 IS = 1e−30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.36e1 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.05e−3 TC2 = −9e−7)
.MODEL RDRAINMOD RES (TC1 = 1.9e−2 TC2 = 4e−5)
.MODEL RSLCMOD RES (TC1 = 1.3e−3 TC2 = 1e−5)
.MODEL RSOURCEMOD RES (TC1 = 1e−3 TC2 = 1e−6)
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FDH047AN08A0, FDP047AN08A0
.MODEL RVTHRESMOD RES (TC1 = −6e−3 TC2 = −1.9e−5)
.MODEL RVTEMPMOD RES (TC1 = −2.4e−3 TC2 = 1e−6)
.MODEL S1AMOD VSWITCH (RON = 1e−5 ROFF = 0.1 VON = −4.0 VOFF= −1.5)
.MODEL S1BMOD VSWITCH (RON = 1e−5 ROFF = 0.1 VON = −1.5 VOFF= −4.0)
.MODEL S2AMOD VSWITCH (RON = 1e−5 ROFF = 0.1 VON = −1.0 VOFF= 0.5)
.MODEL S2BMOD VSWITCH (RON = 1e−5 ROFF = 0.1 VON = 0.5 VOFF= −1.0)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub−Circuit for the Power MOSFET
Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by
William J. Hepp and C. Frank Wheatley.
Figure 21. PSPICE Electrical Model
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FDH047AN08A0, FDP047AN08A0
SABER ELECTRICAL MODEL
REV March 2002
template FDP047AN08A0 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl = 2.4e−11, n1 = 1.04, rs = 1.76e−3, trs1 = 2.7e−3, trs2 = 2e−7, xti = 3.9, cjo = 4.35e−9, tt = 1e−8,
m = 5.4e−1)
dp..model dbreakmod = (rs = 1.5e−1, trs1 = 1e−3, trs2 = −8.9e−6)
dp..model dplcapmod = (cjo = 1.35e−9, isl =10e−30, nl =10, m = 0.53)
m..model mmedmod = (type=_n, vto = 3.7, kp = 9, is =1e−30, tox=1)
m..model mstrongmod = (type=_n, vto = 4.4, kp = 250, is = 1e−30, tox = 1)
m..model mweakmod = (type=_n, vto = 3.05, kp = 0.03, is = 1e−30, tox = 1, rs=0.1)
sw_vcsp..model s1amod = (ron = 1e−5, roff = 0.1, von = −4.0, voff = −1.5)
sw_vcsp..model s1bmod = (ron =1e−5, roff = 0.1, von = −1.5, voff = −4.0)
sw_vcsp..model s2amod = (ron = 1e−5, roff = 0.1, von = −1.0, voff = 0.5)
sw_vcsp..model s2bmod = (ron = 1e−5, roff = 0.1, von = 0.5, voff = −1.0)
c.ca n12 n8 = 1.5e−9
c.cb n15 n14 = 1.5e−9
c.cin n6 n8 = 6.4e−9
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1e−9
l.lgate n1 n9 = 4.81e−9
l.lsource n3 n7 = 4.63e−9
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1 = 1.05e−3, tc2 = −9e−7
res.rdrain n50 n16 = 9e−4, tc1 = 1.9e−2, tc2 = 4e−5
res.rgate n9 n20 = 1.36
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 48.1
res.rlsource n3 n7 = 46.3
res.rslc1 n5 n51= 1e−6, tc1 = 1e−3, tc2 =1e−5
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 2.3e−3, tc1 = 1e−3, tc2 =1e−6
res.rvtemp n18 n19 = 1, tc1 = −2.4e−3, tc2 = 1e−6
res.rvthres n22 n8 = 1, tc1 = −6e−3, tc2 = −1.9e−5
spe.ebreak n11 n7 n17 n18 = 82.3
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
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FDH047AN08A0, FDP047AN08A0
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51−>n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e−9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/250))** 10))
}
}
Figure 22. SABER Electrical Model
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11
FDH047AN08A0, FDP047AN08A0
SPICE THERMAL MODEL
REV 23 March 2002
th
JUNCTION
FDP047AN08A0T
CTHERM1
RTHERM1
RTHERM2
RTHERM3
CTHERM1 th 6 6.45e−3
CTHERM2 6 5 3e−2
CTHERM3 5 4 1.4e−2
CTHERM4 4 3 1.65e−2
CTHERM5 3 2 4.85e−2
CTHERM6 2 tl 1e−1
6
5
CTHERM2
CTHERM3
CTHERM4
RTHERM1 th 6 3.24e−3
RTHERM2 6 5 8.08e−3
RTHERM3 5 4 2.28e−2
RTHERM4 4 3 1e−1
RTHERM5 3 2 1.1e−1
RTHERM6 2 tl 1.4e−1
SABER THERMAL MODEL
SABER thermal model FDP047AN08A0T
template thermal_model th tl
thermal_c th, tl
4
3
2
{
ctherm.ctherm1 th 6 = 6.45e−3
ctherm.ctherm2 6 5 = 3e−2
ctherm.ctherm3 5 4 = 1.4e−2
ctherm.ctherm4 4 3 = 1.65e−2
ctherm.ctherm5 3 2 = 4.85e−2
ctherm.ctherm6 2 tl = 1e−1
RTHERM4
rtherm.rtherm1 th 6 = 3.24e−3
rtherm.rtherm2 6 5 = 8.08e−3
rtherm.rtherm3 5 4 = 2.28e−2
rtherm.rtherm4 4 3 = 1e−1
rtherm.rtherm5 3 2 = 1.1e−1
rtherm.rtherm6 2 tl = 1.4e−1
}
CTHERM5
CTHERM6
RTHERM5
RTHERM6
tl
CASE
Figure 23. Thermal Model
POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United
States and/or other countries.
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12
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−220−3LD
CASE 340AT
ISSUE A
DATE 03 OCT 2017
Scale 1:1
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13818G
TO−220−3LD
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
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© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−247−3LD SHORT LEAD
CASE 340CK
ISSUE A
DATE 31 JAN 2019
P1
D2
A
E
P
A
A2
Q
E2
S
D1
D
E1
B
2
2
1
3
L1
A1
b4
L
c
(3X) b
(2X) b2
M
M
B A
0.25
MILLIMETERS
MIN NOM MAX
4.58 4.70 4.82
2.20 2.40 2.60
1.40 1.50 1.60
1.17 1.26 1.35
1.53 1.65 1.77
2.42 2.54 2.66
0.51 0.61 0.71
20.32 20.57 20.82
(2X) e
DIM
A
A1
A2
b
b2
b4
c
GENERIC
D
MARKING DIAGRAM*
D1 13.08
~
~
D2
E
0.51 0.93 1.35
15.37 15.62 15.87
AYWWZZ
XXXXXXX
XXXXXXX
E1 12.81
~
~
E2
e
L
4.96 5.08 5.20
5.56
15.75 16.00 16.25
3.69 3.81 3.93
3.51 3.58 3.65
XXXX = Specific Device Code
~
~
A
Y
= Assembly Location
= Year
WW = Work Week
ZZ = Assembly Lot Code
L1
P
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
P1 6.60 6.80 7.00
Q
S
5.34 5.46 5.58
5.34 5.46 5.58
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13851G
TO−247−3LD SHORT LEAD
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
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