FDH50N50-F133 [ONSEMI]
功率 MOSFET,N 沟道,UniFETTM,500 V,48 A,105 mΩ,TO-247;型号: | FDH50N50-F133 |
厂家: | ONSEMI |
描述: | 功率 MOSFET,N 沟道,UniFETTM,500 V,48 A,105 mΩ,TO-247 局域网 开关 脉冲 晶体管 |
文件: | 总11页 (文件大小:461K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MOSFET – N-Channel,
UniFETt
500 V, 48 A, 105 mW
FDH50N50, FDA50N50
Description
UniFET MOSFET is ON Semiconductor’s high voltage MOSFET
family based on planar stripe and DMOS technology. This MOSFET
is tailored to reduce on−state resistance, and to provide better
switching performance and higher avalanche energy strength. This
device family is suitable for switching power converter applications
such as power factor correction (PFC), flat panel display (FPD) TV
power, ATX and electronic lamp ballasts.
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V
R
MAX
I MAX
D
DS
DS(ON)
500 V
105 mW @ 10 V
48 A
D
Features
• R
= 89 mW (Typ.) @ V = 10 V, I = 24 A
GS D
• Low Gate Charge (Typ. 105 nC)
DS(on)
G
• Low C (Typ. 45 pF)
rss
• 100% Avalanche Tested
• Improved dv/dt Capability
S
N-CHANNEL MOSFET
• These Devices are Pb−Free and are RoHS Compliant
Applications
• Lighting
• Uninterruptible Power Supply
• AC−DC Power Supply
G
G
D
S
D
S
TO−3PN
CASE 340BZ
TO−247−3LD
CASE 340CK
MARKING DIAGRAM
$Y&Z&3&K
FDH
50N50
$Y&Z&3&K
FDA
50N50
$Y
&Z
&3
&K
= ON Semiconductor Logo
= Assembly Plant Code
= Numeric Date Code
= Lot Code
FDH50N50,
FDA50N50
= Specific Device Code
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
© Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
December, 2019 − Rev. 4
FDH50N50/D
FDH50N50, FDA50N50
ABSOLUTE MAXIMUM RATINGS (T = 25°C unless otherwise noted)
C
Symbol
Parameter
FDH50N50−F133/
Unit
FDA50N50
V
DSS
Drain to Source Voltage
500
V
I
D
Drain Current −
−Continuous (T = 25°C)
48
30.8
A
A
C
−Continuous (T = 100°C)
C
I
Drain Current
−Pulsed (Note 1)
192
20
A
V
DM
V
GSS
Gate−Source Voltage
E
Single Pulsed Avalanche Energy (Note 2)
Avalanche Current (Note 1)
1868
48
mJ
A
AS
I
AR
E
Repetitive Avalanche Energy (Note 1)
Peak Diode Recovery dv/dt (Note 3)
Power Dissipation
62.5
20
mJ
V/ns
AR
dv/dt
P
(T = 25°C)
−Derate Above 25°C
625
5
W
W/°C
D
C
T , T
Operating and Storage Temperature Range
−55 to + 150
°C
°C
J
STG
T
L
Maximum Lead Temperature for Soldering, 1/8″ from Case for 5 Second
300
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Repetitive Rating: Pulse width limited by maximum junction temperature.
2. L = 1.46 mH, I = 48 A, V = 50 V, R = 25 W, Starting T = 25 °C.
AS
DD
G
DSS
J
3. I ≤ 48 A, di/dt ≤ 200 A/ms, V ≤ BV
, Starting T = 25 °C.
J
SD
DD
PACKAGE MARKING AND ORDERING INFORMATION
Part Number
FDH50N50−F133
FDA50N50
Top Mark
FDH50N50
FDA50N50
Package
TO−247−3
TO−3PN
Package Method
Tube
Reel Size
N/A
Tape Width
N/A
Quantity
30 Units
30 Units
Tube
N/A
N/A
THERMAL CHARACTERISTICS
Symbol
Parameter
FDH50N50−F133/
Unit
FDA50N50
R
R
Thermal Resistance, Junction to Case, Max.
Thermal Resistance, Junction to Ambient, Max.
0.2
40
°C/W
q
JC
JA
q
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2
FDH50N50, FDA50N50
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
C
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
OFF CHARACTERISTICS
BV
Drain to Source Breakdown Voltage
I
I
= 250 mA, V = 0 V
500
−
−
−
V
DSS
D
GS
DBV
/ DT
Breakdown Voltage Temperature
Coefficient
= 250 mA, Referenced to 25°C
−
0.5
V/°C
DSS
J
D
I
Zero Gate Voltage Drain Current
V
V
V
V
= 500 V, V = 0 V
−
−
−
−
−
−
−
−
25
250
100
−100
mA
mA
nA
nA
DSS
DS
GS
= 400 V, T = 125°C
DS
GS
GS
C
I
Gate−Body Leakage Current, Forward
Gate−Body Leakage Current, Reverse
= 20 V, V = 0 V
DS
GSSF
I
= −20 V, V = 0 V
DS
GSSR
ON CHARACTERISTICS
V
Gate Threshold Voltage
V
DS
V
GS
V
DS
= V , I = 250 mA
3.0
−
−
0.089
20
5.0
0.105
−
V
W
S
GS(th)
DS(on)
GS
D
R
Static Drain−Source On−Resistance
Forward Transconductance
= 10 V, I = 24 A
D
g
FS
= 40 V, I = 48 A
−
D
DYNAMIC CHARACTERISTICS
C
Input Capacitance
V
= 25 V, V = 0 V, f = 1 MHz
−
−
−
−
−
4979
760
50
6460
1000
65
pF
pF
pF
pF
pF
iss
oss
rss
oss
DS
GS
C
C
C
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
V
V
= 400 V, V = 0 V, f = 1 MHz
161
342
−
DS
GS
C
(
Effective Output Capacitance
= 0 V to 400 V, V = 0 V
−
oss eff.)
DS
GS
SWITCHING CHARACTERISTICS
t
Turn-On Delay Time
Turn−On Rise Time
Turn-Off Delay Time
Turn−Off Fall Time
Total Gate Charge
Gate−Source Charge
Gate−Drain Charge
V
V
= 250 V, I = 48 A,
−
−
−
−
−
−
−
105
360
225
230
105
33
220
730
460
470
137
−
ns
ns
d(on)
DD
GS
D
= 10 V, R = 25 W
G
t
r
(Note 4)
t
ns
d(off)
t
f
ns
Q
V
DS
V
GS
= 400 V, I = 48 A
nC
nC
nC
g
D
,
= 10 V
Q
gs
gd
(Note 4)
Q
45
−
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
Maximum Continuous Drain−Source Diode Forward Current
Maximum Pulsed Drain−Source Diode Forward Current
−
−
−
−
−
−
−
48
192
1.4
−
A
A
S
I
SM
V
SD
Source to Drain Diode Voltage
Reverse Recovery Time
V
V
= 0 V, I = 48 A
−
V
GS
S
t
= 0 V, I = 48 A,
580
10
ns
mC
rr
GS
S
dI /dt = 100 A/ms
F
Q
Reverse Recovery Charge
−
rr
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Essentially Independent of Operating Temperature Typical Characteristics.
www.onsemi.com
3
FDH50N50, FDA50N50
TYPICAL CHARACTERISTICS
2
V
GS
10
100
Top:
15.0 V
10.0 V
8.0 V
7.0 V
6.5 V
6.0 V
5.5 V
25°C
150°C
1
10
10
10
Bottom:
−55°C
0
*Notes:
1
*Notes:
1. 250 ms Pulse Test
1. V = 40 V
DS
2. T = 25°C
C
2. 250 ms Pulse Test
−1
10
0.1
−1
0
1
10
10
10
4
5
6
7
8
9
10
V
DS
, Drain−Source Voltage [V]
V
GS
, Gate−Source Voltage [V]
Figure 2. Transfer Characteristics
Figure 1. On−Region Characteristics
160
120
0.4
0.3
150°C
25°C
V
= 10 V
GS
80
0.2
0.1
*Notes:
40
0
V
= 20 V
GS
1. V = 0 V
GS
2. 250 ms Pulse Test
*Note: T = 25°C
J
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0
25
50
75
100
125
150
175
V
SD
, Source−Drain Voltage [V]
I , Drain Current [A]
D
Figure 3. On−Resistance Variation vs. Drain Current
Figure 4. Body Diode Forward Voltage Variation
vs. Source Current and Temperature
and Gate Voltage
12
10
12000
V
= 100 V
= 250 V
DS
C
C
C
= C + C (C = shorted)
iss
oss
rss
gs
gd
ds
V
= C + C
DS
= 400 V
10000
8000
6000
ds
gd
gd
= C
V
DS
8
6
4
2
0
C
iss
*Notes:
4000
2000
0
C
oss
1. V = 0 V
GS
2. f = 1 MHz
C
rss
*Note: I = 48 A
D
1
0
−1
0
20
40
60
80
100
120
10
10
10
Q , Total Gate Charge [nC]
G
V
DS
, Drain−Source Voltage [V]
Figure 6. Gate Charge Characteristics
Figure 5. Capacitance Characteristics
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4
FDH50N50, FDA50N50
TYPICAL CHARACTERISTICS
1.2
1.1
1.0
0.9
0.8
2.5
2.0
1.5
1.0
*Notes:
*Notes:
1. V = 0 V
1. V = 10 V
GS
GS
0.5
2. I = 250 mA
2. I = 24 A
D
D
0.0
−100
−100
−50
0
50
100
150
200
200
−50
0
50
100
150
T , Junction Temperature [°C]
J
T , Junction Temperature [°C]
J
Figure 7. Breakdown Voltage Variation
vs. Temperature
Figure 8. On−Resistance Variation
vs. Temperature
3
50
40
30
10
Operation in This Area
is Limited by R
DS(on)
2
10 ms
100 ms
10
1 ms
10 ms
DC
1
10
10
20
10
0
*Notes:
0
1. T = 25°C
C
2. T = 150°C
J
3. Single Pulse
−1
10
2
3
0
1
10
, Drain−Source Voltage [V]
10
10
10
25
50
75
100
125
150
V
DS
T , Case Temperature [°C]
C
Figure 10. Maximum Drain Current
vs. Case Temperature
Figure 9. Maximum Safe Operating Area
4000
3500
3000
2500
2000
1500
1000
500
45
*Notes:
*Notes:
40
35
30
25
1. V = 400 V
DS
1. V = 400 V
DS
2. V = 12 V
GS
2. V = 12 V
GS
3. I = 25 A
D
3. I = 25 A
D
4. T = 125°C
J
4. T = 125°C
J
dv/dt(on)
di/dt(on)
20
15
10
dv/dt(off)
di/dt(off)
5
0
0
40
0
5
10 15 20 25 30 35
45 50
0
5
10 15 20 25 30 35 40 45 50
R , Gate Resistance [W]
G
R , Gate Resistance [W]
G
Figure 11. Typical Drain Current Slope
vs. Gate Resistance
Figure 12. Typical Drain−Source Voltage Slope
vs. Gate Resistance
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5
FDH50N50, FDA50N50
1000
800
600
400
100
*Notes:
1. If R = 0 W
t
AV
= (L) (I ) / (1.3 Rated BV
− V
DC
)
AS
DSS
2. If R ≠ 0 W
= (L/R) In [(I x R) / (1.3 Rated BV
t
AV
− V ) + 1]
AS
DSS
DC
Eoff
Starting T = 25°C
J
10
Eon
*Notes:
1. V = 400 V
DS
GS
D
J
Starting T = 150°C
J
2. V = 12 V
200
0
3. I = 25 A
4. T = 125°C
1
0.01
1
10
100
0.1
0
5
10 15 20 25 30 35 40 45 50
R , Gate Resistance [W]
G
t , Time In Avalanche [ms]
AV
Figure 13. Typical Switching Losses
vs. Gate Resistance
Figure 14. Unclamped Inductive Switching
Capability
−1
D=0.5
10
0.2
Notes:
1. Z (t) = 0.2°C/W Max.
q
JC
0.1
2. Duty Factor, D = t /t
1
2
0.05
0.02
0.01
3. T − T = P
* Z (t)
q
JC
JM
C
DM
−2
−3
10
P
DM
Single Pulse
t
1
t
2
10
1
−3
−2
−1
0
−5
−4
10
10
10
10
10
10
10
t , Square Wave Pulse Duration [sec]
1
Figure 15. Transient Thermal Resistance Curve
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6
FDH50N50, FDA50N50
Same Type
as DUT
50KW
Q
Q
12V
200nF
g
300nF
VDS
VGS
Q
gs
gd
DUT
I
G
= const.
Charge
Figure 16. Gate Charge Test Circuit & Waveform
R
L
V
DS
GS
90%
V
DS
V
DD
V
GS
R
G
10%
V
DUT
V
GS
t
t
d(off)
d(on)
t
r
t
f
t
on
t
off
Figure 17. Resistive Switching Test Circuit & Waveforms
L
BVDSS
BVDSS * VDD
2
1
2
EAS
+
@ LIAS
V
DS
BV
DSS
I
D
I
AS
R
G
V
DD
I (t)
D
V
DS
(t)
DUT
V
DD
V
GS
t
p
Time
t
p
Figure 18. Unclamped Inductive Switching Test Circuit & Waveforms
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7
FDH50N50, FDA50N50
+
DUT
V
DS
−
I
SD
L
Driver
R
G
Same Type
as DUT
V
DD
V
GS
− dv/dt controlled by R
G
− I controlled by pulse period
SD
Gate Pulse Width
D +
Gate Pulse Period
V
GS
10 V
(Driver)
I
, Body Diode Forward Current
FM
I
di/dt
SD
(DUT)
I
RM
Body Diode Reverse Current
Body Diode Recovery dv/dt
V
DS
V
DD
V
SD
(DUT)
Body Diode
Forward Voltage Drop
Figure 19. Peak Diode Recovery dv/dt Test Circuit & Waveforms
UniFET is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−3P−3LD / EIAJ SC−65, ISOLATED
CASE 340BZ
ISSUE O
DATE 31 OCT 2016
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13862G
TO−3P−3LD / EIAJ SC−65, ISOLATED
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−247−3LD SHORT LEAD
CASE 340CK
ISSUE A
DATE 31 JAN 2019
P1
D2
A
E
P
A
A2
Q
E2
S
D1
D
E1
B
2
2
1
3
L1
A1
b4
L
c
(3X) b
(2X) b2
M
M
B A
0.25
MILLIMETERS
MIN NOM MAX
4.58 4.70 4.82
2.20 2.40 2.60
1.40 1.50 1.60
1.17 1.26 1.35
1.53 1.65 1.77
2.42 2.54 2.66
0.51 0.61 0.71
20.32 20.57 20.82
(2X) e
DIM
A
A1
A2
b
b2
b4
c
GENERIC
D
MARKING DIAGRAM*
D1 13.08
~
~
D2
E
0.51 0.93 1.35
15.37 15.62 15.87
AYWWZZ
XXXXXXX
XXXXXXX
E1 12.81
~
~
E2
e
L
4.96 5.08 5.20
5.56
15.75 16.00 16.25
3.69 3.81 3.93
3.51 3.58 3.65
XXXX = Specific Device Code
~
~
A
Y
= Assembly Location
= Year
WW = Work Week
ZZ = Assembly Lot Code
L1
P
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
P1 6.60 6.80 7.00
Q
S
5.34 5.46 5.58
5.34 5.46 5.58
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13851G
TO−247−3LD SHORT LEAD
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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