FDMF6821B_技术文档

Extra-Small,

High-Performance,

High-Frequency DrMOS

Module

FDMF6821B

Description

www.onsemi.com

™

The XS DrMOS family is ON Semiconductor’s next−generation,

fully optimized, ultra−compact, integrated MOSFET plus driver

power stage solution for high−current, high− frequency, synchronous

buck DC−DC applications. The FDMF6821B integrates a driver IC,

two power MOSFETs, and a bootstrap Schottky diode into a thermally

enhanced, ultra−compact 6x6 mm package.

With an integrated approach, the complete switching power stage is

optimized with regard to driver and MOSFET dynamic performance,

PQFN40 6X6, 0.5P

CASE 483AN

system inductance, and power MOSFET R

. XS DrMOS uses

DS(ON)

®

ON Semiconductor’s high−performance POWERTRENCH

MOSFET technology, which dramatically reduces switch ringing,

eliminating the need for snubber circuit in most buck converter

applications.

MARKING DIAGRAM

A driver IC with reduced dead times and propagation delays further

enhances the performance. A thermal warning function warns of a

potential over−temperature situation. The FDMF6821B also

incorporates a Skip Mode (SMOD#) for improved light−load

efficiency. The FDMF6821B also provides a 3−state 3.3 V PWM input

for compatibility with a wide range of PWM controllers.

$Y&Z&3&K

FDMF

6821B

Features

$Y

&Z

&3

&K

= ON Semiconductor Logo

• Over 93% Peak−Efficiency

• High−Current Handling: 55 A

• High−Performance PQFN Copper−Clip Package

• 3−State 3.3 V PWM Input Driver

= Assembly Plant Code

= Numeric Date Code

= Lot Code

FDMF6821B

= Specific Device Code

• Skip−Mode SMOD# (Low−Side Gate Turn Off) Input

• Thermal Warning Flag for Over−Temperature Condition

• Driver Output Disable Function (DISB# Pin)

ORDERING INFORMATION

See detailed ordering and shipping information on page 2 of

this data sheet.

• Internal Pull−Up and Pull−Down for SMOD# and DISB# Inputs,

Respectively

• ON Semiconductor PowerTrench Technology MOSFETs for Clean

Voltage Waveforms and Reduced Ringing

• ON Semiconductor SyncFET (Integrated Schottky Diode)

Technology in Low−Side MOSFET

• Integrated Bootstrap Schottky Diode

• Adaptive Gate Drive Timing for Shoot−Through Protection

• Under−Voltage Lockout (UVLO)

• Optimized for Switching Frequencies up to 1 MHz

• Low−Profile SMD Package

®

• Based on the Intel 4.0 DrMOS Standard

• This Device is Pb−Free, Halogen Free/BFR Free and is RoHS

Compliant

1

Publication Order Number:

January, 2020 − Rev. 2

FDMF6821B/D

FDMF6821B

Benefits

• Compact Blade Servers, V−Core and Non−V−Core

• Ultra−Compact 6x6 mm PQFN, 72% Space−Saving

Compared to Conventional Discrete Solutions

• Fully Optimized System Efficiency

• Clean Switching Waveforms with Minimal Ringing

• High−Current Handling

DC−DC Converters

• Desktop Computers, V−Core and Non−V−Core

DC−DC Converters

• Workstations

• High−Current DC−DC Point−of−Load Converters

• Networking and Telecom Microprocessor Voltage

Applications

• High−Performance Gaming Motherboards

Regulators

• Small Form−Factor Voltage Regulator Modules

ORDERING INFORMATION

Part Number

Current Rating

Package

Top Mark

FDMF6821B

55 A

40−Lead, Clipbond PQFN DrMOS, 6.0 mm x 6.0 mm Package

Typical Application Circuit

V_IN

3V ~ 16V

V_5V

C_VIN

C_VDRV

VCIN

VIN

VDRV

R_BOOT

DISB#

BOOT

C_BOOT

PWM Input

OFF

PWM

FDMF6821B

PHASE

VSWH

SMOD#

ON

V_OUT

L_OUT

Open-Drain

Output

THWN#

C_OUT

PGND

CGND

Figure 1. Typical Application Circuit

www.onsemi.com

2

FDMF6821B

DrMOS Block Diagram

VDRV

BOOT

VIN

Q1

UVLO

VCIN

HS Power

MOSFET

D_Boot

DISB#

GH

Level−Shift

10 mA

V_CIN

30 kW

PHASE

Dead−Time

R_{UP_PWM}

Input

3−State

Logic

Control

VSWH

PWM

V_DRV

R_{DN_PWM}

GL

Logic

THWN#

V_CIN

30 kW

Q2

LS Power

MOSFET

Temp.

Sense

10 mA

CGND

SMOD#

PGND

Figure 2. DrMOS Block Diagram

Pin Configuration

Figure 3. Bottom View

Figure 4. Top View

www.onsemi.com

3

FDMF6821B

PIN DEFINITIONS

Pin #

Name

Description

1

SMOD#

When SMOD# = HIGH, the low−side driver is the inverse of the PWM input. When SMOD# = LOW, the low−side

driver is disabled. This pin has a 10 mA internal pull−up current source. Do not add a noise filter capacitor.

2

3

VCIN

VDRV

IC bias supply. Minimum 1 mF ceramic capacitor is recommended from this pin to CGND.

Power for the gate driver. Minimum 1 mF ceramic capacitor is recommended to be connected as close as possible

from this pin to CGND.

4

BOOT

Bootstrap supply input. Provides voltage supply to the high−side MOSFET driver. Connect a bootstrap capacitor

from this pin to PHASE.

5, 37, 41

6

CGND IC ground. Ground return for driver IC.

GH For manufacturing test only. This pin must float; it must not be connected to any pin.

PHASE Switch node pin for bootstrap capacitor routing. Electrically shorted to VSWH pin.

7

8

NC

No connect. The pin is not electrically connected internally, but can be connected to VIN for convenience.

Power input. Output stage supply voltage.

9 − 14, 42

VIN

VSWH

15, 29 −

35, 43

Switch node input. Provides return for high−side bootstrapped driver and acts as a sense point for the adaptive

shoot−through protection.

16 – 28

PGND Power ground. Output stage ground. Source pin of the low−side MOSFET.

36

38

GL

THWN#

For manufacturing test only. This pin must float; it must not be connected to any pin.

Thermal warning flag, open collector output. When temperature exceeds the trip limit, the output is pulled LOW.

THWN# does not disable the module.

39

40

DISB#

PWM

Output disable. When LOW, this pin disables the power MOSFET switching (GH and GL are held LOW).

This pin has a 10 mA internal pull−down current source. Do not add a noise filter capacitor.

PWM signal input. This pin accepts a three−state 3.3 V PWM signal from the controller.

www.onsemi.com

4

FDMF6821B

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Min.

−0.3

Max.

6.0

Unit

V

VCIN

VDRV

Supply Voltage

Referenced to CGND

Referenced to PGND, CGND

Drive Voltage

6.0

V

VDISB#

VPWM

VSMOD#

VGL

Output Disable

6.0

V

PWM Signal Input

Skip Mode Input

6.0

V

6.0

V

Low Gate Manufacturing Test Pin

Thermal Warning Flag

6.0

V

VTHWN#

6.0

V

VIN

Power Input

25.0

V

VBOOT

Bootstrap Supply

Referenced to VSWH, PHASE

Referenced to CGND

−0.3

6.0

V

25.0

VGH

High Gate Manufacturing Test Pin

Referenced to VSWH, PHASE

Referenced to CGND

−0.3

6.0

V

25.0

VPHS

VSWH

PHASE

Referenced to CGND

−0.3

25.0

V

Switch Node Input

Referenced to PGND, CGND (DC Only)

Referenced to PGND, <20 ns

−0.3

−8.0

25.0

28.0

V

VBOOT

Bootstrap Supply

Referenced to VDRV

22.0

25.0

7.0

55

V

Referenced to VDRV, <20 ns

ITHWN#

IO(AV)

THWN# Sink Current

−0.1

mA

A

(1)

Output Current

f

= 300 kHz, V = 12 V, V = 1.0 V

IN O

SW

= 1 MHz, V = 12 V, V = 1.0 V

50

SW

IN

O

Junction−to−PCB Thermal Resistance

2.7

°C/W

°C

qJPCB

T

A

Ambient Temperature Range

−40

+125

T

Maximum Junction Temperature

+150

°C

V

J

TSTG

Storage Temperature Range

−55

600

ESD

Electrostatic Discharge Protection

Human Body Model, JESD22−A114

Charged Device Model, JESD22−C101

2500

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. I

is rated using ON Semiconductor’s DrMOS evaluation board, at T = 25°C, with natural convection cooling. This rating is limited by

O(AV)

A

the peak DrMOS temperature, T = 150°C, and varies depending on operating conditions and PCB layout. This rating can be changed with

J

different application settings.

RECOMMENDED OPERATING CONDITIONS

Symbol

VCIN

Parameter

Min.

4.5

Typ.

5.0

Max.

5.5

Unit

V

Control Circuit Supply Voltage

Gate Drive Circuit Supply Voltage

Output Stage Supply Voltage

VDRV

VIN

4.5

5.0

5.5

V

3.0

12.0

16.0

(Note 2)

V

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

2. Operating at high V can create excessive AC overshoots on the VSWH−to−GND and BOOT−to−GND nodes during MOSFET switching

IN

transients. For reliable DrMOS operation, VSWH−to−GND and BOOT−to−GND must remain at or below the Absolute Maximum Ratings

shown in the table above. Refer to the “Application Information” and “PCB Layout Guidelines” sections of this datasheet for additional

information.

www.onsemi.com

5

FDMF6821B

ELECTRICAL CHARACTERISTICS

Typical values are V = 12 V, V

= 5 V, V

= 5 V, and T = T = +25°C unless otherwise noted.

IN

CIN

DRV

A

J

Symbol

Parameter

Condition

Min.

Typ.

Max.

Unit

BASIC OPERATION

I

Quiescent Current

UVLO Threshold

VUVLO_Hys UVLO Hysteresis

PWM INPUT (V = V = 5 V 10%)

I

= I

+ I , PWM = LOW or HIGH or Float

VDRV

2

mA

V

Q

VCIN

VUVLO

V

Rising

2.9

3.1

0.4

3.3

CIN

V

CIN

DRV

RUP_PWM

RDN_PWM

VIH_PWM

VTRI_HI

Pull−Up Impedance

V

= 5 V

= 0 V

26

kW

V

PWM

Pull−Down Impedance

PWM High Level Voltage

3−State Upper Threshold

3−State Lower Threshold

PWM Low Level Voltage

12

PWM

1.88

1.84

0.70

0.62

2.25

2.20

0.95

0.85

160

1.60

2.61

2.56

1.19

1.13

200

V

VTRI_LO

VIL_PWM

V

tD_HOLD−OFF 3−State Shut−Off Time

3−State Open Voltage

PWM INPUT (V = V = 5 V 5%)

ns

V

VHiZ_PWM

1.40

1.90

CIN

DRV

RUP_PWM

RDN_PWM

VIH_PWM

VTRI_HI

Pull−Up Impedance

V

= 5 V

= 0 V

26

kW

V

PWM

Pull−Down Impedance

PWM High Level Voltage

3−State Upper Threshold

3−State Lower Threshold

PWM Low Level Voltage

12

PWM

2.00

1.94

0.75

0.66

2.25

2.20

0.95

0.85

160

1.60

2.50

2.46

1.15

1.09

200

V

VTRI_LO

VIL_PWM

V

tD_HOLD−OFF 3−State Shut−Off Time

ns

V

VHiZ_PWM

3−State Open Voltage

1.45

2

1.80

DISB# INPUT

VIH_DISB

VIL_DISB

High−Level Input Voltage

Low−Level Input Voltage

V

0.8

IPLD

Pull−Down Current

10

25

mA

tPD_DISBL

Propagation Delay

PWM = GND, Delay Between DISB# from HIGH to LOW

to GL from HIGH to LOW

ns

tPD_DISBH

Propagation Delay

PWM = GND, Delay Between DISB# from LOW to HIGH

to GL from LOW to HIGH

25

SMOD# INPUT

VIH_SMOD

High−Level Input Voltage

Low−Level Input Voltage

2

V

VIL_SMOD

0.8

IPLU

Pull−Up Current

10

mA

tPD_SLGLL

Propagation Delay

PWM = GND, Delay Between SMOD# from HIGH to

LOW to GL from HIGH to LOW

ns

tPD_SHGLH

Propagation Delay

PWM = GND, Delay Between SMOD# from LOW to

HIGH to GL from LOW to HIGH

10

www.onsemi.com

6

FDMF6821B

ELECTRICAL CHARACTERISTICS

Typical values are V = 12 V, V

= 5 V, V

= 5 V, and T = T = +25°C unless otherwise noted.

IN

CIN

DRV

A

J

Symbol

Parameter

Condition

Min.

Typ.

Max.

Unit

THERMAL WARNING FLAG

TACT

TRST

Activation Temperature

150

135

30

°C

W

Reset Temperature

RTHWN

Pull−Down Resistance

I

= 5 mA

PLD

HIGH−SIDE DRIVER (F

= 1000 kHz, I

= 30 A, T = +25°C)

SW

OUT

A

RSOURCE_GH Output Impedance, Sourcing

Source Current = 100 mA

Sink Current = 100 mA

GH = 10% to 90%

1

W

RSINK_GH

tR_GH

Output Impedance, Sinking

Rise Time

0.8

10

ns

tF_GH

Fall Time

GH = 90% to 10%

10

15

ns

tD_DEADON LS to HS Deadband Time

GL Going LOW to GH Going HIGH,

1.0 V GL to 10% GH

tPD_PLGHL

tPD_PHGHH

tPD_TSGHH

20

30

ns

PWM LOW Propagation Delay PWM Going LOW to GH Going LOW,

V

to 90% GH

IL_PWM

PWM HIGH Propagation Delay PWM Going HIGH to GH Going HIGH, V

to 10%

IH_PWM

(SMOD# = 0)

GH (SMOD# = 0, I

>0)

D_LS

Exiting 3−State Propagation De- PWM (From 3−State) Going HIGH to GH Going HIGH,

lay to 10% GH

V

IH_PWM

LOW−SIDE DRIVER (F

= 1000 kHz, I

= 30 A, T = +25°C)

SW

OUT

A

RSOURCE_GL Output Impedance, Sourcing

Source Current = 100 mA

Sink Current = 100 mA

GL = 10% to 90%

1

W

RSINK_GL

tR_GL

Output Impedance, Sinking

Rise Time

0.5

25

ns

tF_GL

Fall Time

GL = 90% to 10%

10

15

ns

tD_DEADOFF HS to LS Deadband Time

SW Going LOW to GL Going HIGH,

2.2 V SW to 10% GL

tPD_PHGLL

tPD_TSGLH

10

20

25

ns

PWM−HIGH Propagation Delay PWM Going HIGH to GL Going LOW, V

to 90%

IH_PWM

GL

Exiting 3−State Propagation

PWM (From 3−State) Going LOW to GL Going HIGH,

V to 10% GL

IL_PWM

Delay

BOOT DIODE

V

Forward−Voltage Drop

I = 20 mA

0.3

V

F

V

R

Breakdown Voltage

I

R

= 1 mA

22

www.onsemi.com

7

FDMF6821B

V _{IH_PWM}

V_{IL_PWM}

PWM

GL

90%

1.0 V

10%

90%

1.2 V

GH

to

VSWH

10%

2.2 V

VSWH

t_PD

PLGHL

t

PD PHGLL

t_{D_DEADOFF}

Figure 5. PWM Timing Diagram

www.onsemi.com

8

FDMF6821B

TYPICAL PERFORMANCE CHARACTERISTICS

Test Conditions: V = 12 V, V

= 1 V, V

= 5 V, V

= 5 V, L = 250 nH, T = 25°C, and natural convection cooling,

OUT A

IN

OUT

CIN

DRV

unless otherwise specified.

55

50

45

11

10

9

V^IN= 12 V, VDRV & VCIN = 5 V, VOUT = 1 V

300kHz

500kHz

800kHz

1000kHz

F_SW= 300kHz

40

35

30

25

20

15

10

5

8

7

6

F_SW= 1000kHz

5

4

3

2

V^IN= 12 V, VDRV & VCIN = 5 V, VOUT = 1 V

1

0

25

50

75

100

125

150

0

5

10

15

20

25

30

35

40

45

50

55

PCB Temperature, TPCB (°C)

Module Output Current, IOUT (A)

Figure 7. Power Loss vs. Output Current

Figure 6. Safe Operating Area

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

0.9

1.10

1.08

1.06

1.04

1.02

1.00

0.98

0.96

VDRV & VCIN = 5 V, VOUT = 1 V, FSW = 300 kHz, IOUT = 30 A

VIN = 12 V, VDRV & VCIN = 5 V, VOUT = 1 V, IOUT = 30 A

100 200 300 400 500 600 700 800 900 1000 1100

4

6

8

10

12

14

16

18

Module Switching Frequency, F_SW(kHz)

Module Input Voltage, V_IN(V)

Figure 8. Power Loss vs. Switching Frequency

Figure 9. Power Loss vs. Input Voltage

2.0

1.8

1.6

1.4

1.2

1.0

0.8

1.15

1.10

1.05

1.00

0.95

0.90

VIN = 12 V, VOUT = 1 V, FSW = 300 kHz, IOUT = 30 A

VIN = 12 V, VDRV & VCIN = 5 V, FSW = 300 kHz, IOUT = 30 A

4.0

4.5

5.0

5.5

6.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

Driver Supply Voltage, V_DRV& V_CIN(V)

Module Output Voltage, V_OUT(V)

Figure 10. Power Loss vs. Driver Supply Voltage

Figure 11. Power Loss vs. Output Voltage

www.onsemi.com

9

FDMF6821B

TYPICAL PERFORMANCE CHARACTERISTICS

Test Conditions: V = 12 V, V

= 1 V, V

= 5 V, V

= 5 V, L = 250 nH, T = 25°C, and natural convection cooling,

OUT A

IN

OUT

CIN

DRV

unless otherwise specified.

1.01

60

VIN = 12 V, VDRV & VCIN = 5 V, FSW = 300 kHz, VOUT = 1V, IOUT = 30 A

VIN = 12 V, VDRV & VCIN = 5 V, VOUT = 1 V, IOUT = 0 A

1.00

0.99

0.98

0.97

0.96

0.95

0.94

50

40

30

20

10

0

100 200

300 400 500 600 700 800 900 1000 1100

200

250

300

350

400

450

500

Output Inductor, LOUT (nH)

Module Switching Frequency, F_SW(kHz)

Figure 13. Driver Supply Current vs. Switching

Frequency

Figure 12. Power Loss vs. Output Inductor

1.03

1.02

1.01

1.00

0.99

0.98

0.97

22

20

18

16

14

12

VIN = 12 V, VOUT = 1 V, FSW = 300 kHz, IOUT = 0 A

V^IN= 12 V, VDRV & VCIN = 5 V, VOUT = 1 V

F_SW= 300kHz

F

_SW= 1000kHz

4.0

4.5

5.0

5.5

6.0

0

5

10

15

20

25

30

35

40

45

50

55

Driver Supply Voltage, V^DRV& VCIN (V)

Module Output Current, IOUT (A)

Figure 14. Driver Supply Current vs. Driver Supply

Voltage

Figure 15. Driver Supply Current vs. Output

Current

3.2

3.0

2.5

2.0

1.5

1.0

0.5

T

_A= 25 °C

UVLO _UP

3.1

V_{IH_PWM}

3.0

2.9

2.8

2.7

V_{TRI_HI}

V_{HIZ_PWM}

V_{TRI_LO}

V_{IL_PWM}

UVLO_DN

125 150

2.6

−55

0

25

55

100

4.50

4.75

5.0

5.25

5.5

Driver IC Junction Temperature, T (5C)

Driver IC Supply Voltage, V_CIN(V)

J

Figure 16. UVLO Threshold vs. Temperature

Figure 17. PWM Threshold vs. Driver Supply Voltage

www.onsemi.com

10

FDMF6821B

TYPICAL PERFORMANCE CHARACTERISTICS

Test Conditions: V

= 5 V, V

= 5 V, T = 25°C, and natural convection cooling, unless otherwise specified.

CIN

DRV

A

3.0

2.5

2.0

1.5

1.0

0.5

2.2

T

_A= 25 °C

V_CIN= 5V

V_{IH_SMOD#}

2.0

1.8

1.6

1.4

1.2

V_{IH_PWM}

V_{TRI_HI}

V_{HIZ_PWM}

V_{IL_SMOD#}

V_{TRI_LO}

V_{IL_PWM}

125

−55

0

25

55

100

150

4.50

4.75

5.0

5.25

5.50

Driver IC Junction Temperature, T (5C)

Driver IC Supply Voltage, V_CIN(V)

J

Figure 19. SMOD# Threshold vs. Driver Supply

Voltage

Figure 18. PWM Threshold vs. Temperature

2.2

2

−9.0

−9.5

V_CIN= 5V

V_{IH_SMOD#}

−10.0

−10.5

−11.0

−11.5

−12.0

1.8

1.6

1.4

1.2

V_{IL_SMOD#}

−55

0

25

55

100

125

150

−55

0

25

55

100

125

150

Driver IC Junction Temperature, T_J(^oC)

Driver IC Junction Temperature, T (5C)

J

Figure 20. SMOD# Threshold vs. Temperature

Figure 21. SMOD# Pull−Up Current vs.

Temperature

2.2

2.0

1.8

1.6

1.4

1.2

2.2

2.0

1.8

1.6

1.4

1.2

V_CIN= 5V

T

_A= 25 °C

V_{IH_DISB#}

V_{IL_DISB#}

−55

0

25

55

100

125

150

4.50

4.75

5.0

5.25

5.50

Driver IC Junction Temperature, T_J(^oC)

Driver IC Supply Voltage, V (V)

CIN

Figure 22. DISB# Threshold vs. Driver Supply

Voltage

Figure 23. DISB# Threshold vs. Temperature

www.onsemi.com

11

FDMF6821B

TYPICAL PERFORMANCE CHARACTERISTICS

Test Conditions: V

= 5 V, V

= 5 V, T = 25°C, and natural convection cooling, unless otherwise specified.

CIN

DRV

A

12.0

11.5

11.0

10.5

10.0

9.5

500

V_CIN= 5V

I

_F= 20mA

450

400

350

300

250

200

150

100

9.0

−55

0

25

55

100

125

150

−55

0

25

55

100

125

150

Driver IC Junction Temperature, T (^oC)

Driver IC Junction Temperature, T_J(^oC)

J

Figure 24. DISB# Pull−Down Current

Figure 25. Boot Diode Forward Voltage

vs. Temperature

www.onsemi.com

12

FDMF6821B

FUNCTIONAL DESCRIPTION

Three−State PWM Input

The FDMF6821B is

a driver−plus−FET module

The FDMF6821B incorporates a three−state 3.3 V PWM

input gate drive design. The three−state gate drive has both

logic HIGH level and LOW level, along with a three−state

shutdown window. When the PWM input signal enters and

remains within the three−state window for a defined

optimized for the synchronous buck converter topology. A

single PWM input signal is all that is required to properly

drive the high−side and the low−side MOSFETs. Each part

is capable of driving speeds up to 1 MHz.

VCIN and Disable (DISB#)

The VCIN pin is monitored by an Under−Voltage Lockout

hold−off time (t ), both GL and GH are pulled

D_HOLD−OFF

LOW. This enables the gate drive to shut down both

high−side and low−side MOSFETs to support features such

as phase shedding, which is common on multi−phase

voltage regulators.

(UVLO) circuit. When V

rises above ~3.1 V, the driver

CIN

is enabled. When V

falls below ~2.7 V, the driver is

CIN

disabled (GH, GL = 0). The driver can also be disabled by

pulling the DISB# pin LOW (DISB# < V ), which

IL_DISB

Exiting Three−State Condition

holds both GL and GH LOW regardless of the PWM input

state. The driver can be enabled by raising the DISB# pin

When exiting

a valid three−state condition, the

FDMF6821B follows the PWM input command. If the

PWM input goes from three−state to LOW, the low−side

MOSFET is turned on. If the PWM input goes from

three−state to HIGH, the high−side MOSFET is turned on.

This is illustrated in Figure 27. The FDMF6821B design

allows for short propagation delays when exiting the

three−state window (see Electrical Characteristics).

voltage HIGH (DISB# > V

).

IH_DISB

Table 1. UVLO AND DISABLE LOGIC

UVLO

DISB#

Driver State

0

1

X

0

Disabled (GH, GL = 0)

Enabled (see Table 2)

Disabled (GH, GL = 0)

1

Low−Side Driver

The low−side driver (GL) is designed to drive a ground−

Open

referenced, low−R , N−channel MOSFET. The bias

DS(ON)

3. DISB# internal pull−down current source is 10 mA.

for GL is internally connected between the VDRV and

CGND pins. When the driver is enabled, the driver’s output

is 180° out of phase with the PWM input. When the driver

is disabled (DISB# = 0 V), GL is held LOW.

Thermal Warning Flag (THWN#)

The FDMF6821B provides a thermal warning flag

(THWN#) to warn of over−temperature conditions. The

thermal warning flag uses an open−drain output that pulls to

CGND when the activation temperature (150°C) is reached.

The THWN# output returns to a high− impedance state once

the temperature falls to the reset temperature (135°C). For

use, the THWN# output requires a pull−up resistor, which

can be connected to VCIN. THWN# does NOT disable the

DrMOS module.

High−Side Driver

The high−side driver (GH) is designed to drive a floating

N−channel MOSFET. The bias voltage for the high−side

driver is developed by a bootstrap supply circuit consisting

of the internal Schottky diode and external bootstrap

capacitor (C

). During startup, V

is held at PGND,

BOOT

SWH

allowing C

to charge to V

through the internal

BOOT

DRV

diode. When the PWM input goes HIGH, GH begins to

charge the gate of the high−side MOSFET (Q1).

150°C

135°C Reset

Temperature

A

HIGH

p

During this transition, the charge is removed from C

and delivered to the gate of Q1. As Q1 turns on, V

BOOT

rises

THWN#

Logic

State

SWH

to V , forcing the BOOT pin to V + V , which

IN

BOOT

Normal

Operation

Thermal

Warning

provides sufficient V enhancement for Q1. To complete

GS

the switching cycle, Q1 is turned off by pulling GH to V

.

SWH

C

BOOT

is then recharged to V

when V

falls to

LOW

DRV

SWH

PGND. GH output is in−phase with the PWM input. The

high−side gate is held LOW when the driver is disabled or

the PWM signal is held within the three−state window for

T_{J_driver IC}

Figure 26. THWN Operation

longer than the three−state hold−off time, t

.

D_HOLD−OFF

www.onsemi.com

13

FDMF6821B

Adaptive Gate Drive Circuit

propagation delay (t ). Once the GL pin is

PD_PHGLL

The driver IC advanced design ensures minimum

MOSFET dead−time, while eliminating potential shoot−

through (cross−conduction) currents. It senses the state of

the MOSFETs and adjusts the gate drive adaptively to ensure

they do not conduct simultaneously. Figure 27 provides the

relevant timing waveforms. To prevent overlap during the

LOW−to−HIGH switching transition (Q2 off to Q1 on), the

adaptive circuitry monitors the voltage at the GL pin. When

the PWM signal goes HIGH, Q2 begins to turn off after a

discharged below 1.0 V, Q1 begins to turn on after adaptive

delay t

.

D_DEADON

To preclude overlap during the HIGH−to−LOW transition

(Q1 off to Q2 on), the adaptive circuitry monitors the voltage

at the GH−to−PHASE pin pair. When the PWM signal goes

LOW, Q1 begins to turn off after a propagation delay

(t

). Once the voltage across GH−to−PHASE falls

PD_PLGHL

below 2.2 V, Q2 begins to turn on after adaptive delay

t

.

D_DEADOFF

V_{IH_PWM}

V_{TRI_HI}

t_{D_HOLD-OFF}

V_{TRI_LO}

V_{IL_PWM}

t_{R_GH}

t_{F_GH}

PWM

90%

10%

GH

to

VSWH

V_IN

DCM

CCM

DCM

V_OUT

2.2V

VSWH

GL

t_{R_GL}

t_{F_GL}

90%

1.0V

90%

10%

t_{PD_PHGLL}

t_{PD_PLGHL}

t_{PD_TSGHH}

t_{D_HOLD-OFF}

t_{PD_TSGLH}

t_{D_DEADON}

t_{D_DEADOFF}

NOTES:

tPD_xxx = propagation delay from external signal (PWM, SMOD#, etc.) to IC generated signal.

t^D_xxx= delay from IC generated signal to IC generated signal.

Example (tPD_PHGLL – PWM going HIGH to LS VGS (GL) going LOW)

Example (tD_DEADON – LS VGS (GL) LOW to HS VGS (GH) HIGH)

PWM

Exiting 3−state

t^PD_PHGLL= PWM rise to LS VGS fall, VIH_PWM to 90% LS VGS

tPD_PLGHL = PWM fall to HS VGS fall, VIL_PWM to 90% HS VGS

tPD_PHGHH = PWM rise to HS VGS rise, VIH_PWM to 10% HS VGS (SMOD# held LOW)

t^PD_TSGHH= PWM 3−state to HIGH to HS VGS rise, VIH_PWM to 10% HS VGS

tPD_TSGLH = PWM 3−state to LOW to LS VGS rise, VIL_PWM to 10% LS VGS

Dead Times

SMOD#

t^D_DEADON= LS VGS fall to HS VGS rise, LS−comp trip value (~1.0 V GL) to 10% HS VGS

t^PD_SLGLL= SMOD# fall to LS VGS fall, VIL_SMOD to 90% LS VGS

tPD_SHGLH = SMOD# rise to LS VGS rise, VIH_SMOD to 10% LS VGS

tD_DEADOFF = VSWH fall to LS VGS rise, SW−comp trip value (~2.2 V VSWH) to 10% LS

V^GS

Figure 27. PWM and 3−StateTiming Diagram

www.onsemi.com

14

FDMF6821B

Skip Mode (SMOD#)

allows for gating on the Low Side MOSFET. When the

SMOD# pin is pulled LOW, the low−side MOSFET is gated

off. If the SMOD# pin is connected to the PWM controller,

the controller can actively enable or disable SMOD# when

the controller detects light−load condition from output

current sensing. Normally this pin is active LOW. See

Figure 28 for timing delays.

The Skip Mode function allows for higher converter

efficiency when operated in light−load conditions. When

SMOD# is pulled LOW, the low−side MOSFET gate signal

is disabled (held LOW), preventing discharge of the output

capacitors as the filter inductor current attempts reverse

current flow – known as “Diode Emulation” Mode.

When the SMOD# pin is pulled HIGH, the synchronous

buck converter works in Synchronous Mode. This mode

Table 2. SMOD# LOGIC

DISB#

PWM

SMOD#

GH

0

GL

0

1

X

0

1

3−State

0

1

0

1

0

1

0

1

0

4. The SMOD# feature is intended to have a short propagation delay between the SMOD# signal and the low−side FET V response time

GS

to control diode emulation on a cycle−by−cycle basis.

SMOD#

V_{IH_SMOD}

V_{IL_SMOD}

V_{IH_PWM}

V_{IL_PWM}

PWM

90%

GH

to

VSWH

10%

DCM

V_OUT

CCM

2.2V

VSWH

GL

90%

1.0V

10%

t_{PD_PLGHL}

t_{PD_PHGLL}

t_{PD_PHGHH}

t_{PD_SHGLH}

t_{PD_SLGLL}

t_{D_DEADOFF}

t_{D_DEADON}

Delay from SMOD# going

LOW to LS V_GSLOW

Delay from SMOD# going

HIGH to LS V HIGH

GS

HS turn -on with SMOD# LOW

Figure 28. SMOD# Timing Diagram

www.onsemi.com

15

FDMF6821B

APPLICATION INFORMATION

Supply Capacitor Selection

can be connected directly to VCIN, the pin that provides

power to the logic section of the driver. For additional noise

immunity, an RC filter can be inserted between the VDRV

and VCIN pins. Recommended values would be 10 W and

1 mF.

For the supply inputs (V ), a local ceramic bypass

CIN

capacitor is recommended to reduce noise and to supply the

peak current. Use at least a 1 mF X7R or X5R capacitor. Keep

this capacitor close to the VCIN pin and connect it to the

GND plane with vias.

Power Loss and Efficiency

Bootstrap Circuit

The bootstrap circuit uses a charge storage capacitor

Measurement and Calculation

Refer to Figure 30 for power loss testing method. Power

loss calculations are:

(C ), as shown in Figure 30. A bootstrap capacitance of

BOOT

100 nF X7R or X5R capacitor is usually adequate. A series

bootstrap resistor may be needed for specific applications to

improve switching noise immunity. The boot resistor may be

required when operating above 15 V and is effective at

controlling the high−side MOSFET turn−on slew rate and

P

= (V × I ) + (V × I ) (W)

(1)

(2)

(3)

(4)

(5)

(6)

(7)

IN

5V

(W)

5V

= V × I

SW

OUT

= V

× I

(W)

OUT

IN

P^LOSS_MODULE= PIN - PSW (W)

P^LOSS_BOARD= PIN - POUT (W)

V

SHW

overshoot. R

values from 0.5 to 3.0 W are

BOOT

EFF

= 100 × P /P (%)

MODULE

SW IN

typically effective in reducing VSWH overshoot.

= 100 × P

/P (%)

BOARD

OUT IN

VCIN Filter

The VDRV pin provides power to the gate drive of the

high−side and low−side power MOSFET. In most cases, it

V_5V

A

V_IN

R_VCIN

I_5V

I_IN

C_VIN

C_VDRV

C_VCIN

VDRV

VCIN

VIN

DISB#

R_BOOT

PWM

Input

OFF

BOOT

PWM

FFDDMMF6678251B

C_BOOT

VSWH

I_OUT

A

SMOD#

ON

L_OUT

Open

PHASE

THWN#

V_OUT

Output

V

V_SW

PGND

CGND

C_OUT

Figure 29. Block Diagram With VCIN Filter

V_5V

A

V

IN

I_5V

I_IN

C_VDRV

C_VIN

VDRV

VCIN

VIN

DISB#

PWM

DISB#

R_BOOT

BOOT

VSWH

PHASE

PWM

Input

OFF

FDMF6821B

FDM

5

C_BOOT

I_OUT

A

SMOD#

THWN#

ON

L_OUT

Open

Output

V V_SW

PGND

CGND

C_OUT

Figure 30. Power Loss Measurement

www.onsemi.com

16

FDMF6821B

PCB LAYOUT GUIDELINES

Figure 31 and Figure 32 provide an example of a proper

layout for the FDMF6821B and critical components. All of

the high−current paths, such as VIN, VSWH, VOUT, and

GND copper, should be short and wide for low inductance

and resistance. This aids in achieving a more stable and

evenly distributed current flow, along with enhanced heat

radiation and system performance.

when operating above 15 V and is effective at

controlling the high−side MOSFET turn−on slew

IN

rate and V

overshoot. R

can improve

SHW

BOOT

noise operating margin in synchronous buck

designs that may have noise issues due to ground

bounce or high positive and negative V

SWH

ringing. Inserting a boot resistance lowers the

DrMOS efficiency. Efficiency versus noise

trade−offs must be considered. R

values from

Recommendations for PCB Designers

1. Input ceramic bypass capacitors must be placed

close to the VIN and PGND pins. This helps

reduce the high−current power loop inductance

and the input current ripple induced by the power

MOSFET switching operation

BOOT

0.5 W to 3.0 W are typically effective inreducing

overshoot

V

SWH

8. The VIN and PGND pins handle large current

transients with frequency components greater than

100 MHz. If possible, these pins should be

2. The V

copper trace serves two purposes. In

connected directly to the VIN and board GND

planes. The use of thermal relief traces in series

with these pins is discouraged since this adds

inductance to the power path. This added

inductance in series with either the VIN or PGND

pin degrades system noise immunity by increasing

SWH

addition to being the high−frequency current path

from the DrMOS package to the output inductor, it

serves as a heat sink for the low−side MOSFET in

the DrMOS package. The trace should be short

and wide enough to present a low−impedance path

for the high−frequency, high−current flow between

the DrMOS and inductor. The short and wide trace

minimizes electrical losses as well as the DrMOS

positive and negative V

ringing

SWH

9. GND pad and PGND pins should be connected to

the GND copper plane with multiple vias for

stable grounding. Poor grounding can create a

noise transient offset voltage level between CGND

and PGND. This could lead to faulty operation of

the gate driver and MOSFETs

temperature rise. Note that the V

node is a

SWH

high− voltage and high−frequency switching node

with high noise potential. Care should be taken to

minimize coupling to adjacent traces. Since this

copper trace acts as a heat sink for the lower

MOSFET, balance using the largest area possible

to improve DrMOS cooling while maintaining

acceptable noise emission

10. Ringing at the BOOT pin is most effectively

controlled by close placement of the boot

capacitor. Do not add an additional BOOT to the

PGND capacitor. This may lead to excess current

flow through the BOOT diode

3. An output inductor should be located close to the

FDMF6821B to minimize the power loss due to

11. The SMOD# and DISB# pins have weak internal

pull−up and pull−down current sources,

the V

copper trace. Care should also be taken

SWH

so the inductor dissipation does not heat the

DrMOS

respectively. These pins should not have any noise

filter capacitors. Do not to float these pins unless

absolutely necessary

4. POWERTRENCH MOSFETs are used in the

output stage and are effective at minimizing

ringing due to fast switching. In most cases, no

VSWH snubber is required. If a snubber is used, it

should be placed close to the VSWH and PGND

pins. The selected resistor and capacitor need to be

the proper size for power dissipation

12. Use multiple vias on the VIN and VOUT copper

areas to interconnect top, inner, and bottom layers

to distribute current flow and heat conduction. Do

not put many vias on the VSWH copper to avoid

extra parasitic inductance and noise on the

switching waveform. As long as efficiency and

thermal performance are acceptable, place only

one VSWH copper on the top layer and use no

vias on the VSWH copper to minimize switch

node parasitic noise. Vias should be relatively

large and of reasonably low inductance. Critical

5. VCIN, VDRV, and BOOT capacitors should be

placed as close as possible to the

VCIN−to−CGND, VDRV−to−CGND, and

BOOT−to−PHASE pin pairs to ensure clean and

stable power. Routing width and length should be

considered as well

6. Include a trace from the PHASE pin to the VSWH

pin to improve noise margin. Keep this trace as

short as possible

7. The layout should include the option to insert a

small−value series boot resistor between the boot

capacitor and BOOT pin. The boot−loop size,

high− frequency components, such as R

,

BOOT

C , RC snubber, and bypass capacitors; should

BOOT

be located as close to the respective DrMOS

module pins as possible on the top layer of the

PCB. If this is not feasible, they can be connected

from the backside through a network of

low−inductance vias

including R

and C , should be as small

BOOT

as possible. The boot resistor may be required

www.onsemi.com

17

FDMF6821B

Figure 31. PCB Layout Example (Top View)

Figure 32. PCB Layout Example (Bottom View)

XS DrMOS are trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.

POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other

countries.

Intel is a registered trademark of Intel Corporation in the U.S. and/or other countries.

www.onsemi.com

18

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

PQFN40 6X6, 0.5P

CASE 483AN

ISSUE A

DATE 08 JUN 2021

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON13663G

PQFN40 6X6, 0.5P

PAGE 1 OF 1

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

www.onsemi.com

onsemi,

, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates

and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.

A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any

products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the

information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use

of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products

and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information

provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may

vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license

under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems

or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should

Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

ADDITIONAL INFORMATION

TECHNICAL PUBLICATIONS:

Technical Library: www.onsemi.com/design/resources/technical−documentation

onsemi Website: www.onsemi.com

ONLINE SUPPORT: www.onsemi.com/support

For additional information, please contact your local Sales Representative at

www.onsemi.com/support/sales




型号：	FDMF6821B
厂家：	ONSEMI
描述：	超小型，高性能，高频率 DrMOS 模块服务器主板节能技术开关
文件：	总20页 (文件大小：644K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FDMF6821B [ONSEMI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E