FDMS3602AS [ONSEMI]
不对称双 N 沟道，PowerTrench® 功率级 MOSFET，25V;
| 型号： | FDMS3602AS |
| 厂家： | 
ONSEMI |
| 描述： | 不对称双 N 沟道，PowerTrench® 功率级 MOSFET，25V 开关 光电二极管 晶体管 |
| 文件： | 总17页 (文件大小：610K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Is Now Part of
To learn more about ON Semiconductor, please visit our website at
www.onsemi.com
Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers
will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor
product management systems do not have the ability to manage part nomenclature that utilizes an underscore
(_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain
device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated
device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please
email any questions regarding the system integration to Fairchild_questions@onsemi.com.
ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number
of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right
to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON
Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON
Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA
Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended
or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out
of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor
is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
March 2011
FDMS3602AS
PowerTrench® Power Stage
Asymmetric Dual N-Channel MOSFET
Features
General Description
Q1: N-Channel
This device includes two specialized N-Channel MOSFETs in a
dual PQFN package. The switch node has been internally
connected to enable easy placement and routing of synchronous
buck converters. The control MOSFET (Q1) and synchronous
SyncFET (Q2) have been designed to provide optimal power
efficiency.
Max rDS(on) = 5.6 mΩ at VGS = 10 V, ID = 15 A
Max rDS(on) = 8.5 mΩ at VGS = 4.5 V, ID = 14 A
Q2: N-Channel
Max rDS(on) = 2.2 mΩ at VGS = 10 V, ID = 26 A
Max rDS(on) = 3.4 mΩ at VGS = 4.5 V, ID = 22 A
Applications
Low inductance packaging shortens rise/fall times, resulting in
lower switching losses
Computing
MOSFET integration enables optimum layout for lower circuit
inductance and reduced switch node ringing
Communications
General Purpose Point of Load
Notebook VCORE
RoHS Compliant
G1
Pin 1
D1
D1
D1
Q2
D1
S2
D1
5
6
7
8
4
3
2
1
PHASE
(S1/D2)
PHASE
D1
D1
S2
S2
G2
G2
S2
S2
G1
Q1
S2
Bottom
Top
Power 56
MOSFET Maximum Ratings TA = 25°C unless otherwise noted
Symbol
VDS
VGS
Parameter
Q1
Q2
Units
Drain to Source Voltage
Gate to Source Voltage
25
±20
30
25
±20
V
V
(Note 3)
Drain Current -Continuous (Package limited)
-Continuous (Silicon limited)
TC = 25 °C
40
T
C = 25 °C
65
151a
135
261b
100
1445
2.51b
1.01d
ID
A
-Continuous
TA = 25 °C
-Pulsed
40
EAS
Single Pulse Avalanche Energy
Power Dissipation for Single Operation
Power Dissipation for Single Operation
Operating and Storage Junction Temperature Range
504
2.21a
1.01c
mJ
W
TA = 25°C
TA = 25°C
PD
TJ, TSTG
-55 to +150
°C
Thermal Characteristics
RθJA
RθJA
RθJC
Thermal Resistance, Junction to Ambient
571a
1251c
3.5
501b
1201d
2
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Case
°C/W
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
13”
Tape Width
Quantity
22OA
N7OC
FDMS3602AS
Power 56
12 mm
3000 units
©2011 Fairchild Semiconductor Corporation
FDMS3602AS Rev.C4
1
www.fairchildsemi.com
Electrical Characteristics TJ = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Type
Min
Typ
Max Units
Off Characteristics
I
I
D = 250 μA, VGS = 0 V
D = 1 mA, VGS = 0 V
Q1
Q2
25
25
BVDSS
Drain to Source Breakdown Voltage
V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID = 250 μA, referenced to 25°C
D = 10 mA, referenced to 25°C
Q1
Q2
20
20
mV/°C
I
Q1
Q2
1
IDSS
IGSS
Zero Gate Voltage Drain Current
VDS = 20 V, VGS = 0 V
μA
500
Gate to Source Leakage Current,
Forward
Q1
Q2
100
100
nA
nA
V
GS = 20 V, VDS = 0 V
On Characteristics
V
V
GS = VDS, ID = 250 μA
GS = VDS, ID = 1 mA
Q1
Q2
1
1
1.8
1.9
3
3
VGS(th)
Gate to Source Threshold Voltage
V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID = 250 μA, referenced to 25°C
D = 10 mA, referenced to 25°C
VGS = 10 V, ID = 15 A
Q1
Q2
-6
-5
mV/°C
I
4.4
6.2
5.9
5.6
8.5
8.7
V
V
GS = 4.5 V, ID = 14 A
GS = 10 V, ID = 15 A, TJ = 125°C
Q1
Q2
rDS(on)
Static Drain to Source On Resistance
mΩ
V
V
V
GS = 10 V, ID = 26 A
GS = 4.5 V, ID = 22 A
GS = 10 V, ID = 26 A, TJ = 125°C
1.7
2.6
2.5
2.2
3.4
3.9
V
V
DD = 5 V, ID = 15 A
DD = 5 V, ID = 26 A
Q1
Q2
67
132
gFS
Forward Transconductance
S
Dynamic Characteristics
Q1
Q2
1330 1770
3260 4335
Q1
Ciss
Coss
Crss
Rg
Input Capacitance
pF
pF
pF
Ω
VDS = 13 V, VGS = 0 V, f = 1 MHZ
Q1
Q2
358
892
475
1185
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
Q2
VDS = 13 V, VGS = 0 V, f = 1 MHZ
Q1
Q2
61
90
145
220
Q1
Q2
0.2
0.2
0.6
0.9
2
3
Switching Characteristics
Q1
Q2
7.9
12
16
22
td(on)
tr
td(off)
tf
Turn-On Delay Time
Rise Time
ns
ns
Q1
V
DD = 13 V, ID = 15 A, RGEN = 6 Ω
Q1
Q2
2
4.2
10
10
Q1
Q2
19
31
34
50
Q2
Turn-Off Delay Time
Fall Time
ns
V
DD = 13 V, ID = 26 A, RGEN = 6 Ω
Q1
Q2
1.8
3.2
10
10
ns
Q1
Q2
19
45
27
64
Qg(TOT)
Qg(TOT)
Qgs
Total Gate Charge
Total Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
VGS = 0V to 10 V
VGS = 0V to 4.5 V
nC
nC
nC
nC
Q1
DD = 13 V,
D = 15 A
V
I
Q1
Q2
9
21
13
30
Q1
Q2
3.9
9.1
Q2
V
DD = 13 V,
Q1
Q2
2.4
5.3
I
D = 26 A
Qgd
©2011 Fairchild Semiconductor Corporation
FDMS3602AS Rev.C4
2
www.fairchildsemi.com
Electrical Characteristics TJ = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Type
Min
Typ
Max Units
Drain-Source Diode Characteristics
V
V
GS = 0 V, IS = 15 A
GS = 0 V, IS = 26 A
(Note 2) Q1
(Note 2) Q2
0.8
0.8
1.2
V
VSD
trr
Source-Drain Diode Forward Voltage
Reverse Recovery Time
1.2
Q1
Q2
21
28
34
ns
44
Q1
IF = 15 A, di/dt = 100 A/s
Q2
IF = 26 A, di/dt = 300 A/s
Q1
Q2
6.6
28
13
nC
44
Qrr
Reverse Recovery Charge
Notes:
2
1. R
is determined with the device mounted on a 1 in pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
is guaranteed by design while R is determined
θCA
θJA
θJC
by the user's board design.
b. 50 °C/W when mounted on
a 1 in pad of 2 oz copper
a. 57 °C/W when mounted on
a 1 in pad of 2 oz copper
2
2
c. 125 °C/W when mounted on a
minimum pad of 2 oz copper
d. 120 °C/W when mounted on a
minimum pad of 2 oz copper
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3. As an N-ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied.
o
4. E of 50 mJ is based on starting T = 25 C; N-ch: L = 1 mH, I = 10 A, V = 23 V, V = 10 V. 100% test at L= 0.3 mH, I = 15 A.
AS
J
AS
DD
GS
AS
o
5. E of 144 mJ is based on starting T = 25 C; N-ch: L = 1 mH, I = 17 A, V = 23 V, V = 10 V. 100% test at L= 0.3 mH, I = 25 A.
AS
J
AS
DD
GS
AS
©2011 Fairchild Semiconductor Corporation
FDMS3602AS Rev.C4
3
www.fairchildsemi.com
Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted
40
30
20
10
0
6
5
4
3
2
1
0
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 10 V
VGS = 4.5 V
VGS = 3 V
VGS = 4 V
VGS = 3.5 V
VGS = 3.5 V
VGS = 4.5 V
VGS = 4 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
V
= 3 V
GS
VGS = 10 V
0
10
20
30
40
0.0
0.2
0.4
0.6
0.8
1.0
VDS, DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
Figure 1. On Region Characteristics
Figure2. N o r m a l i z e d O n - R e s i s ta n c e
vs Drain Current and Gate Voltage
1.6
25
ID = 15 A
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 10 V
1.4
1.2
1.0
0.8
0.6
20
15
10
5
ID = 15 A
TJ = 125 oC
TJ = 25 o
C
0
-75 -50 -25
0
25 50 75 100 125 150
2
4
6
8
10
TJ, JUNCTION TEMPERATURE (oC)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 3. Normalized On Resistance
vs Junction Temperature
Figure4. On-Resistance vs Gate to
Source Voltage
40
40
VGS = 0 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
10
30
20
10
0
TJ = 150 o
C
TJ = 25 oC
VDS = 5 V
1
TJ = 150 o
C
TJ = -55 o
C
0.1
TJ = 25 o
C
0.01
0.001
TJ = -55 o
C
1
2
3
4
0.0
0.2
0.4
0.6
0.8
1.0
1.2
VGS, GATE TO SOURCE VOLTAGE (V)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure6. Source to Drain Diode
Forward Voltage vs Source Current
©2011 Fairchild Semiconductor Corporation
FDMS3602AS Rev.C4
4
www.fairchildsemi.com
Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted
10
8
2000
1000
VDD = 10 V
ID = 15 A
Ciss
VDD = 13 V
Coss
6
VDD = 16 V
100
4
Crss
2
f = 1 MHz
GS = 0 V
V
0
10
0
5
10
Qg, GATE CHARGE (nC)
15
20
0.1
1
10
25
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics
Figure8. C a p a c i t a n c e v s D r a i n
to Source Voltage
20
80
60
40
20
0
RθJC = 3.5 oC/W
10
VGS = 10 V
TJ = 25 oC
TJ = 100 oC
VGS = 4.5 V
TJ = 125 o
C
Limited by Package
1
0.01
0.1
1
10
100
25
50
75
100
125
150
TC, CASE TEMPERATURE (oC)
t
AV, TIME IN AVALANCHE (ms)
Figure9. U n c l a m p e d I n d u c t i v e
Switching Capability
Figure10. Maximum Continuous Drain
Current vs Case Temperature
100
10
1000
SINGLE PULSE
RθJA = 125 oC/W
100 μs
T
A = 25 oC
100
10
1 ms
10 ms
1
THIS AREA IS
100 ms
LIMITED BY r
DS(on)
1s
10s
SINGLE PULSE
TJ = MAX RATED
0.1
R
θJA = 125 oC/W
A = 25 oC
DC
1
T
0.01
0.01
0.5
10-4
10-3
10-2
t, PULSE WIDTH (sec)
10-1
1
10
100 1000
0.1
1
10
100
200
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe
Operating Area
Figure12. Single Pulse Maximum
Power Dissipation
©2011 Fairchild Semiconductor Corporation
FDMS3602AS Rev.C4
5
www.fairchildsemi.com
Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
0.1
0.01
0.1
P
0.05
0.02
0.01
DM
t
1
SINGLE PULSE
θJA = 125 oC/W
t
2
R
NOTES:
DUTY FACTOR: D = t /t
1
2
(Note 1c)
PEAK T = P
J
x Z
x R
+ T
θJA A
DM
θJA
0.001
10-4
10-3
10-2
10-1
1
10
100
1000
t, RECTANGULAR PULSE DURATION (sec)
Figure 13. Junction-to-Ambient Transient Thermal Response Curve
©2011 Fairchild Semiconductor Corporation
FDMS3602AS Rev.C4
6
www.fairchildsemi.com
Typical Characteristics (Q2 N-Channel) TJ = 25 °C unless otherwise noted
100
80
60
40
20
0
8
6
4
2
0
VGS = 10 V
VGS = 4.5 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 3 V
VGS = 4 V
VGS = 3.5 V
VGS = 3.5 V
VGS = 4 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 3 V
VGS = 10 V
80 100
VGS = 4.5 V
60
0.0
0.2
0.4
0.6
0.8
1.0
0
20
40
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 14. On- Region Characteristics
Figure 15. Normalized on-Resistance vs Drain
Current and Gate Voltage
1.6
12
ID = 26 A
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 10 V
10
1.4
1.2
1.0
0.8
ID = 26 A
8
6
TJ = 125 oC
4
2
TJ = 25 o
C
0
2
4
6
8
10
-75 -50 -25
0
25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 17. On-Resistance vs Gate to
Source Voltage
Figure 16. Normalized On-Resistance
vs Junction Temperature
100
200
100
VGS = 0 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
80
60
40
20
0
VDS = 5 V
TJ = 125 o
C
TJ = 125 o
C
10
1
TJ = 25 o
C
TJ = 25 oC
TJ = -55 o
C
TJ = -55 o
C
0.1
1.5
2.0
2.5
3.0
3.5
4.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
VGS, GATE TO SOURCE VOLTAGE (V)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 18. Transfer Characteristics
Figure 19. Source to Drain Diode
Forward Voltage vs Source Current
©2011 Fairchild Semiconductor Corporation
FDMS3602AS Rev.C4
7
www.fairchildsemi.com
Typical Characteristics (Q2 N-Channel) TJ = 25°C unless otherwise noted
10
8
10000
ID = 26 A
Ciss
VDD = 10 V
Coss
6
1000
VDD = 13 V
4
VDD = 16 V
Crss
2
f = 1 MHz
VGS = 0 V
100
50
0
25
0.1
1
10
0
10
20
30
40
50
VDS, DRAIN TO SOURCE VOLTAGE (V)
Q , GATE CHARGE (nC)
g
Figure 21. Capacitance vs Drain
to Source Voltage
Figure 20. Gate Charge Characteristics
50
150
120
90
RθJC = 2 oC/W
VGS = 10 V
TJ = 25 oC
10
TJ = 100 oC
VGS = 4.5 V
60
TJ = 125 o
C
30
Limited by Package
1
0.01
0
0.1
1
10
100 300
25
50
75
100
125
150
TC, CASE TEMPERATURE (oC)
tAV, TIME IN AVALANCHE (ms)
Figure 22. Unclamped Inductive
Switching Capability
Figure 23. Maximum Continuous Drain
Current vs Case Temperature
200
100
10000
100 μs
SINGLE PULSE
RθJC = 2 oC/W
1000
100
10
1 ms
10
1
10 ms
THIS AREA IS
LIMITED BY r
100 ms
DS(on)
1s
SINGLE PULSE
TJ = MAX RATED
RθJA = 120 oC/W
10s
DC
0.1
T
A = 25 oC
0.01
1
0.01
0.1
1
10
100200
10-4
10-3
10-2
t, PULSE WIDTH (sec)
10-1
1
10
100 1000
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 24. Forward Bias Safe
Operating Area
Figure 25. Single Pulse Maximum Power
Dissipation
©2011 Fairchild Semiconductor Corporation
FDMS3602AS Rev.C4
8
www.fairchildsemi.com
Typical Characteristics (Q2 N-Channel) TJ = 25 °C unless otherwise noted
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
0.1
0.1
P
DM
0.05
0.02
0.01
0.001
0.01
t
1
t
2
SINGLE PULSE
θJA = 120 oC/W
NOTES:
DUTY FACTOR: D = t /t
R
1
2
PEAK T = P
J
x Z
x R
+ T
θJA A
(Note 1d)
DM
θJA
0.0001
10-4
10-3
10-2
10-1
t, RECTANGULAR PULSE DURATION (sec)
1
10
100
1000
Figure 26. Junction-to-Ambient Transient Thermal Response Curve
©2011 Fairchild Semiconductor Corporation
FDMS3602AS Rev.C4
9
www.fairchildsemi.com
Typical Characteristics (continued)
SyncFET Schottky body diode
Characteristics
Schottky barrier diodes exhibit significant leakage at high tem-
perature and high reverse voltage. This will increase the power
in the device.
Fairchild’s SyncFET process embeds a Schottky diode in parallel
with PowerTrench MOSFET. This diode exhibits similar
characteristics to a discrete external Schottky diode in parallel
with
a MOSFET. Figure 27 shows the reverse recovery
characteristic of the FDMS3602AS.
10-2
30
25
20
TJ = 125 o
C
10-3
10-4
10-5
10-6
TJ = 100 o
C
di/dt = 300 A/μs
15
10
5
TJ = 25 o
C
0
-5
0
5
10
15
20
25
0
50
100
TIME (ns)
150
200
250
VDS, REVERSE VOLTAGE (V)
Figure 27. FDMS3602AS SyncFET body
diode reverse recovery characteristic
Figure 28. SyncFET body diode reverse
leakage versus drain-source voltage
©2011 Fairchild Semiconductor Corporation
FDMS3602AS Rev.C4
10
www.fairchildsemi.com
Application Information
1. Switch Node Ringing Suppression
Fairchild’s Power Stage products incorporate a proprietary design* that minimizes the peak overshoot, ringing voltage on the switch
node (PHASE) without the need of any external snubbing components in a buck converter. As shown in the figure 29, the Power Stage
solution rings significantly less than competitor solutions under the same set of test conditions.
Power Stage Device
Competitors solution
Figure 29. Power Stage phase node rising edge, High Side Turn on
*Patent Pending
©2011 Fairchild Semiconductor Corporation
FDMS3602AS Rev.C4
11
www.fairchildsemi.com
Figure 30. Shows the Power Stage in a buck converter topology
2. Recommended PCB Layout Guidelines
As a PCB designer, it is necessary to address critical issues in layout to minimize losses and optimize the performance of the power
train. Power Stage is a high power density solution and all high current flow paths, such as VIN (D1), PHASE (S1/D2) and GND (S2),
should be short and wide for better and stable current flow, heat radiation and system performance. A recommended layout proce-
dure is discussed below to maximize the electrical and thermal performance of the part.
Figure 31. Recommended PCB Layout
©2011 Fairchild Semiconductor Corporation
FDMS3602AS Rev.C4
12
www.fairchildsemi.com
Following is a guideline, not a requirement which the PCB designer should consider:
1. Input ceramic bypass capacitors C1 and C2 must be placed close to the D1 and S2 pins of Power Stage to help reduce parasitic
inductance and high frequency conduction loss induced by switching operation. C1 and C2 show the bypass capacitors placed close
to the part between D1 and S2. Input capacitors should be connected in parallel close to the part. Multiple input caps can be connected
depending upon the application.
2. The PHASE copper trace serves two purposes; In addition to being the current path from the Power Stage package to the output
inductor (L), it also serves as heat sink for the lower FET in the Power Stage package. The trace should be short and wide enough to
present a low resistance path for the high current flow between the Power Stage and the inductor. This is done to minimize conduction
losses and limit temperature rise. Please note that the PHASE node is a high voltage and high frequency switching node with high
noise potential. Care should be taken to minimize coupling to adjacent traces. The reference layout in figure 31 shows a good balance
between the thermal and electrical performance of Power Stage.
3. Output inductor location should be as close as possible to the Power Stage device for lower power loss due to copper trace
resistance. A shorter and wider PHASE trace to the inductor reduces the conduction loss. Preferably the Power Stage should be
directly in line (as shown in figure 31) with the inductor for space savings and compactness.
4. The PowerTrench® Technology MOSFETs used in the Power Stage are effective at minimizing phase node ringing. It allows the
part to operate well within the breakdown voltage limits. This eliminates the need to have an external snubber circuit in most cases. If
the designer chooses to use an RC snubber, it should be placed close to the part between the PHASE pad and S2 pins to dampen
the high-frequency ringing.
5. The driver IC should be placed close to the Power Stage part with the shortest possible paths for the High Side gate and Low Side
gates through a wide trace connection. This eliminates the effect of parasitic inductance and resistance between the driver and the
MOSFET and turns the devices on and off as efficiently as possible. At higher-frequency operation this impedance can limit the gate
current trying to charge the MOSFET input capacitance. This will result in slower rise and fall times and additional switching losses.
Power Stage has both the gate pins on the same side of the package which allows for back mounting of the driver IC to the board. This
provides a very compact path for the drive signals and improves efficiency of the part.
6. S2 pins should be connected to the GND plane with multiple vias for a low impedance grounding. Poor grounding can create a noise
transient offset voltage level between S2 and driver ground. This could lead to faulty operation of the gate driver and MOSFET.
7. Use multiple vias on each copper area to interconnect top, inner and bottom layers to help smooth current flow and heat conduction.
Vias should be relatively large, around 8 mils to 10 mils, and of reasonable inductance. Critical high frequency components such as
ceramic bypass caps should be located close to the part and on the same side of the PCB. If not feasible, they should be connected
from the backside via a network of low inductance vias.
©2011 Fairchild Semiconductor Corporation
FDMS3602AS Rev.C4
13
www.fairchildsemi.com
4.00
C
L
5.10
4.90
0.10 C
A
1.27 TYP
0.65 TYP
(2X)
PKG
B
C
L
8
5
8
6
7
5
0.63
2.15
2.52
1.60
KEEP OUT AREA
6.25
5.90
C
PKG
C
L
0.00
L
4.16
1.21
2.13
2.31
3.15
1
4
0.10 C
(2X)
2
4
1
3
PIN # 1
INDICATOR
0.63
0.59
TOP VIEW
3.18
5.10
SEE
DETAIL A
RECOMMENDED LAND PATTERN
FOR SAWN / PUNCHED TYPE
SIDE VIEW
0.10
0.05
C A B
C
0.10 C
3.16
2.80
0.65
0.38
0.70
0.36
8X
0.45
0.25
(6X)
0.08 C
1.34
1.12
C
0.05
0.00
1
2
3
0.35
0.15
4
1.10
0.90
SEATING
PLANE
0.66±.05
(SCALE: 2X)
2.25
2.05
4.08
3.70
1.02
0.82
0.65
0.38
8
7
6
5
0.44
0.24
0.61
0.31 (8X)
1.27
3.81
BOTTOM VIEW
5.10
4.90
0.10 C
(2X)
SEE
0.35
0.15
PKG
DETAIL B
C
L
5
8
0.28
0.08
10°
6.25
5.90
5.90
5.70
PKG
C
L
(SCALE: 2X)
0.10 C
1
4
(2X)
0.41
0.21
(8X)
TOP VIEW
5.00
4.80
SEE
0.10 C
0.08 C
DETAIL C
0.35
0.15
8X
C
SIDE VIEW
SEATING
PLANE
1.10
0.90
(SCALE: 2X)
0.10
0.05
C A B
3.16
2.80
0.70
0.36
0.65
0.38
C
0.45
0.25
(6X)
1
2
3
1.34
1.12
4
NOTES: UNLESS OTHERWISE SPECIFIED
A) PACKAGE STANDARD REFERENCE:
0.66±.05
JEDEC REGISTRATION, MO-240, VARIATION AA.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS OR
MOLD FLASH. MOLD FLASH OR BURRS DOES
NOT EXCEED 0.10MM.
2.25
2.05
4.08
3.70
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-1994.
E) IT IS RECOMMENDED TO HAVE NO TRACES
OR VIAS WITHIN THE KEEP OUT AREA.
F) DRAWING FILE NAME: PQFN08EREV6.
G) FAIRCHILD SEMICONDUCTOR
1.02
0.82
0.65
0.38
6
8
7
5
0.61
0.44
0.24
(8X)
0.31
1.27
3.81
BOTTOM VIEW
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
© Semiconductor Components Industries, LLC
www.onsemi.com
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明