FDMS3606AS [ONSEMI]
30V，不对称双 N 沟道 MOSFET，PowerTrench® 功率级;
| 型号： | FDMS3606AS |
| 厂家： | 
ONSEMI |
| 描述： | 30V，不对称双 N 沟道 MOSFET，PowerTrench® 功率级 开关 晶体管 |
| 文件： | 总15页 (文件大小：1018K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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FDMS3606AS
PowerTrench® Power Stage
30 V Asymmetric Dual N-Channel MOSFET
Features
General Description
This device includes two specialized N-Channel MOSFETs in a
dual PQFN package. The switch node has been internally
connected to enable easy placement and routing of synchronous
buck converters. The control MOSFET (Q1) and synchronous
SyncFET (Q2) have been designed to provide optimal power
efficiency.
Q1: N-Channel
Max rDS(on) = 8 mΩ at VGS = 10 V, ID = 13 A
Max rDS(on) = 11 mΩ at VGS = 4.5 V, ID = 11 A
Q2: N-Channel
Applications
Max rDS(on) = 1.9 mΩ at VGS = 10 V, ID = 27 A
Max rDS(on) = 2.8 mΩ at VGS = 4.5 V, ID = 23 A
Computing
Low inductance packaging shortens rise/fall times, resulting in
lower switching losses
Communications
General Purpose Point of Load
Notebook VCORE
Sever
MOSFET integration enables optimum layout for lower circuit
inductance and reduced switch node ringing
RoHS Compliant
G1
D1
D1
D1
Q2
D1
S2
D1
5
6
7
8
4
3
2
1
PHASE
(S1/D2)
PHASE
D1
D1
S2
S2
G2
G2
S2
S2
S2
G1
Q1
Top
Bottom
Power 56
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
Parameter
Q1
Q2
Units
Drain to Source Voltage
Gate to Source Voltage
30
±20
30
30
±20
V
V
(Note 3)
TC = 25 °C
TC = 25 °C
TA = 25 °C
Drain Current
-Continuous (Package limited)
-Continuous (Silicon limited)
-Continuous
40
60
131a
148
271b
100
1625
2.51b
1.01d
ID
A
-Pulsed
40
EAS
Single Pulse Avalanche Energy
404
2.21a
1.01c
mJ
W
Power Dissipation for Single Operation
Power Dissipation for Single Operation
Operating and Storage Junction Temperature Range
TA = 25 °C
TA = 25 °C
PD
TJ, TSTG
-55 to +150
°C
Thermal Characteristics
RθJA
RθJA
RθJC
Thermal Resistance, Junction to Ambient
571a
1251c
3.5
501b
1201d
2
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Case
°C/W
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
13 ”
Tape Width
Quantity
22CA
N9CC
FDMS3606AS
Power 56
12 mm
3000 units
©2011 Semiconductor Components Industries, LLC.
October-2017, Rev. 3
Publication Order Number:
FDMS3606AS/D
Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Type
Min
Typ
Max
Units
Off Characteristics
ID = 250 μA, VGS = 0 V
ID = 1 mA, VGS = 0 V
Q1
Q2
30
30
BVDSS
Drain to Source Breakdown Voltage
V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID = 250 μA, referenced to 25 °C
Q1
Q2
15
20
mV/°C
I
D = 10 mA, referenced to 25 °C
Q1
Q2
1
500
μA
μA
IDSS
IGSS
Zero Gate Voltage Drain Current
VDS = 24 V, VGS = 0 V
Gate to Source Leakage Current,
Forward
Q1
Q2
100
100
nA
nA
V
V
GS = 20 V, VDS= 0 V
On Characteristics
GS = VDS, ID = 250 μA
Q1
Q2
1.1
1.1
2
1.8
2.7
3
VGS(th)
Gate to Source Threshold Voltage
V
VGS = VDS, ID = 1 mA
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID = 250 μA, referenced to 25 °C
ID = 10 mA, referenced to 25 °C
Q1
Q2
-6
-5
mV/°C
V
V
GS = 10 V, ID = 13 A
GS = 4.5 V, ID = 11 A
5.8
8.5
7.8
8
11
10.8
Q1
Q2
VGS = 10 V, ID = 13 A , TJ = 125 °C
rDS(on)
Drain to Source On Resistance
mΩ
VGS = 10 V, ID = 27 A
VGS = 4.5 V, ID = 23 A
VGS = 10 V, ID = 27 A , TJ = 125 °C
1.4
2
1.9
1.9
2.8
2.8
VDS = 5 V, ID = 13 A
Q1
Q2
61
154
gFS
Forward Transconductance
S
V
DS = 5 V, ID = 27 A
Dynamic Characteristics
Q1
Q2
1273
4129
1695
5490
Q1:
Ciss
Coss
Crss
Rg
Input Capacitance
pF
pF
pF
Ω
VDS = 15 V, VGS = 0 V, f = 1 MHZ
Q1
Q2
461
1527
615
2030
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
Q2:
VDS = 15 V, VGS = 0 V, f = 1 MHZ
Q1
Q2
50
98
75
150
Q1
Q2
0.2
0.2
0.6
0.8
2
3
Switching Characteristics
Q1
Q2
8.2
15
16
27
td(on)
tr
td(off)
tf
Turn-On Delay Time
Rise Time
ns
ns
Q1:
Q1
Q2
2.5
5.5
10
11
VDD = 15 V, ID = 13 A, RGEN = 6 Ω
Q1
Q2
20
36
32
58
Q2:
Turn-Off Delay Time
Fall Time
ns
VDD = 15 V, ID = 27 A, RGEN = 6 Ω
Q1
Q2
2.2
3.4
10
10
ns
Q1
Q2
21
59
29
83
Qg
Total Gate Charge
Total Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
VGS = 0 V to 10 V
Q1
nC
nC
nC
nC
VDD = 15 V,
ID = 13 A
Q1
Q2
10
27
14
38
Qg
VGS = 0 V to 4.5 V
Q1
Q2
3.9
12
Q2
VDD = 15 V,
Qgs
Qgd
Q1
Q2
3.1
5.7
ID = 27 A
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Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Type
Min
Typ
Max
Units
Drain-Source Diode Characteristics
VGS = 0 V, IS = 13 A
(Note 2) Q1
(Note 2) Q2
0.8
0.8
1.2
1.2
VSD
trr
Source to Drain Diode Forward Voltage
Reverse Recovery Time
V
V
GS = 0 V, IS = 27 A
Q1
Q2
25
39
40
62
Q1
ns
nC
IF = 13 A, di/dt = 100 A/μs
Q2
IF = 27 A, di/dt = 300 A/μs
Q1
Q2
9
57
18
91
Qrr
Reverse Recovery Charge
Notes:
2
1: R
is determined with the device mounted on a 1 in pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
is guaranteed by design while R is determined
θCA
θJA
θJC
by the user's board design.
b. 50 °C/W when mounted on
a 1 in pad of 2 oz copper
a. 57 °C/W when mounted on
a 1 in pad of 2 oz copper
2
2
c. 125 °C/W when mounted on a
minimum pad of 2 oz copper
d. 120 °C/W when mounted on a
minimum pad of 2 oz copper
2: Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3: As an N-ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied.
o
4: E of 40 mJ is based on starting T = 25 C; N-ch: L = 1 mH, I = 9 A, V = 27 V, V = 10 V. 100% test at L= 0.3 mH, I = 14 A.
AS
J
AS
DD
GS
AS
o
5: E of 162 mJ is based on starting T = 25 C; N-ch: L = 1 mH, I = 18 A, V = 27 V, V = 10 V. 100% test at L= 0.3 mH, I = 27 A.
AS
J
AS
DD
GS
AS
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Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
40
30
20
10
0
4
3
2
1
0
VGS = 10 V
= 6 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 3.5 V
V
GS
VGS = 4.5 V
VGS = 4 V
VGS = 4 V
VGS = 4.5 V
VGS = 6 V
VGS = 10 V
VGS = 3.5 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0
10
20
30
40
0.0
0.2
0.4
0.6
0.8
1.0
VDS, DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
Figure 1. On Region Characteristics
F i g u r e 2 . No rma li zed O n-Re si stan ce
vs Drain Current and Gate Voltage
1.6
20
ID = 13 A
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 10 V
1.4
1.2
1.0
0.8
0.6
16
ID = 13 A
12
TJ = 125 oC
8
4
TJ = 25 o
C
0
-75 -50 -25
0
25 50 75 100 125 150
2
4
6
8
10
TJ, JUNCTION TEMPERATURE (oC)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 3. Normalized On Resistance
vs Junction Temperature
Figure4. On-Resistance vs Gate to
Source Voltage
40
40
VGS = 0 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
10
30
20
10
0
VDS = 5 V
1
TJ = 150 o
C
TJ = 150 o
C
TJ = 25 oC
0.1
TJ = 25 o
C
TJ = -55 o
C
0.01
0.001
TJ = -55 o
C
1.5
2.0
2.5
3.0
3.5
4.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
VGS, GATE TO SOURCE VOLTAGE (V)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure6. Source to Drain Diode
Forward Voltage vs Source Current
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Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
10
8
2000
1000
ID = 13 A
VDD = 10 V
Ciss
VDD = 15 V
Coss
6
VDD = 20 V
100
4
Crss
2
f = 1 MHz
GS = 0 V
V
0
10
0
5
10
15
20
25
0.1
1
10
30
VDS, DRAIN TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics
Figure8. C a p a c i t a n c e v s D r a i n
to Source Voltage
20
100
80
60
40
20
0
RθJC = 3.5 oC/W
10
VGS = 10 V
TJ = 25 oC
TJ = 100 oC
VGS = 4.5 V
TJ = 125 o
C
Limited by Package
50
1
0.01
0.1
1
10
100
25
75
100
125
150
TC, CASE TEMPERATURE (oC)
t
AV, TIME IN AVALANCHE (ms)
Figure9. U n c l a m p e d I n d u c t i v e
Switching Capability
Figure 10. Maximum Continuous Drain
Current vs Case Temperature
100
10
1000
SINGLE PULSE
RθJA = 125 oC/W
TA = 25 oC
100us
1 ms
100
10
1
10 ms
1
THIS AREA IS
LIMITED BY r
100 ms
DS(on)
SINGLE PULSE
TJ = MAX RATED
1s
0.1
10s
R
θJA = 125 oC/W
A = 25 oC
DC
T
0.01
0.01
0.1
10-4
10-3
10-2
t, PULSE WIDTH (sec)
10-1
1
10
0.1
1
10
100
100 1000
200
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe
Operating Area
Figure 12. Single Pulse Maximum
Power Dissipation
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Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
0.1
0.05
0.02
0.1
P
DM
0.01
t
1
t
2
0.01
SINGLE PULSE
NOTES:
R
θJA = 125 oC/W
DUTY FACTOR: D = t /t
1 2
PEAK T = P
J
x Z
x R
+ T
DM
θJA
θJA A
(Note 1c)
0.001
10-4
10-3
10-2
10-1
t, RECTANGULAR PULSE DURATION (sec)
1
10
100
1000
Figure 13. Junction-to-Ambient Transient Thermal Response Curve
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Typical Characteristics (Q2 N-Channel) TJ = 25 oC unlenss otherwise noted
100
80
60
40
20
0
8
6
4
2
0
VGS = 3 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 10 V
VGS = 4.5 V
VGS = 3.5 V
VGS = 4 V
= 3.5 V
V
GS
VGS = 4.5 V
VGS = 4 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 3 V
VGS = 10 V
0
20
40
60
80
100
0.0
0.2
0.4
0.6
0.8
1.0
VDS, DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
Figure 14. On-Region Characteristics
Figure 15. Normalized on-Resistance vs Drain
Current and Gate Voltage
1.6
8
ID = 27 A
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 10 V
1.4
1.2
1.0
0.8
6
ID = 27 A
4
TJ = 125 oC
2
TJ = 25 o
C
0
2
4
6
8
10
-75 -50 -25
0
25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 17. On-Resistance vs Gate to
Source Voltage
Figure 16. Normalized On-Resistance
vs Junction Temperature
100
100
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 0 V
TJ = 125 o
80
60
40
20
0
10
1
C
VDS = 5 V
TJ = 125 o
C
TJ = 25 oC
TJ = 25 o
C
0.1
TJ = -55 o
C
0.01
0.001
TJ = -55 o
C
1.5
2.0
2.5
3.0
3.5
0.0
0.2
0.4
0.6
0.8
1.0
1.2
VGS, GATE TO SOURCE VOLTAGE (V)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 18. Transfer Characteristics
Figure 19. Source to Drain Diode
Forward Voltage vs Source Current
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Typical Characteristics (Q2 N-Channel) TJ = 25 oC unless otherwise noted
10
10000
1000
100
ID = 27A
Ciss
8
VDD = 10 V
Coss
6
VDD = 15 V
4
VDD = 20 V
Crss
2
f = 1 MHz
VGS = 0 V
0
10
0.1
1
10
30
0
10
20
30
40
50
60
VDS, DRAIN TO SOURCE VOLTAGE (V)
Q , GATE CHARGE (nC)
g
Figure 21. Capacitance vs Drain
to Source Voltage
Figure 20. Gate Charge Characteristics
200
150
100
50
50
R
θJC = 2 oC/W
VGS = 10 V
TJ = 25 oC
10
TJ = 100 oC
VGS = 4.5 V
TJ = 125 o
C
Limited by Package
1
0.01
0
25
50
75
100
125
150
0.1
1
10
100
1000
TC, CASE TEMPERATURE (oC)
tAV, TIME IN AVALANCHE (ms)
Figure 22. Unclamped Inductive
Switching Capability
Figure 23. Maximun Continuous Drain
Current vs Case Temperature
1000
200
100
SINGLE PULSE
θJA = 120 oC/W
A = 25 oC
R
100
10
1
1 ms
T
10
1
10 ms
THIS AREA IS
100 ms
1s
LIMITED BY r
DS(on)
SINGLE PULSE
TJ = MAX RATED
0.1
0.01
10s
DC
R
θJA = 120 oC/W
TA = 25 oC
0.1
10-3
10-2
10-1
t, PULSE WIDTH (sec)
1
10
0.01
0.1
1
10
100200
100
1000
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 24. Forward Bias Safe
Operating Area
Figure 25. Single Pulse Maximum
Power Dissipation
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Typical Characteristics (Q2 N-Channel) TJ = 25 oC unless otherwise noted
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
0.1
0.05
0.02
P
DM
0.1
0.01
t
1
t
2
SINGLE PULSE
RθJA = 120 oC/W
(Note 1d)
NOTES:
DUTY FACTOR: D = t /t
0.01
1
2
PEAK T = P
J
x Z
x R
+ T
θJA A
DM
θJA
0.001
10-3
10-2
10-1
1
10
100
1000
t, RECTANGULAR PULSE DURATION (sec)
Figure 26. Junction-to-Ambient Transient Thermal Response Curve
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Typical Characteristics (continued)
SyncFET Schottky body diode
Characteristics
Schottky barrier diodes exhibit significant leakage at high tem-
perature and high reverse voltage. This will increase the power
in the device.
ON Semiconductor’s SyncFET process embeds a Schottky
diode in parallel with PowerTrench MOSFET. This diode
exhibits
similar
characteristics to
a
discrete external
Schottky diode in parallel with
a
MOSFET. Figure 27
characteristic of the
shows
the
reverse
recovery
FDMS3606AS.
10-2
30
25
20
15
10
5
TJ = 125 o
C
10-3
10-4
10-5
10-6
TJ = 100 o
C
didt = 300 A/μs
TJ = 25 o
C
0
-5
0
50
100
150
200
250
300
0
5
10
15
20
25
30
TIME (ns)
VDS, REVERSE VOLTAGE (V)
Figure 28. SyncFET body diode reverse
leakage versus drain-source voltage
Figure 27. FDMS3606AS SyncFET body
diode reverse recovery characteristic
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Application Information
1. Switch Node Ringing Suppression
ON Semiconductor’s Power Stage products incorporate a proprietary design* that minimizes the peak overshoot, ringing voltage on
the switch node (PHASE) without the need of any external snubbing components in a buck converter. As shown in the figure 29, the
Power Stage solution rings significantly less than competitor solutions under the same set of test conditions.
Power Stage Device
Competitors solution
Figure 29. Power Stage phase node rising edge, High Side Turn on
*Patent Pending
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Figure 30. Shows the Power Stage in a buck converter topology
2. Recommended PCB Layout Guidelines
As a PCB designer, it is necessary to address critical issues in layout to minimize losses and optimize the performance of the power
train. Power Stage is a high power density solution and all high current flow paths, such as VIN (D1), PHASE (S1/D2) and GND (S2),
should be short and wide for better and stable current flow, heat radiation and system performance. A recommended layout proce-
dure is discussed below to maximize the electrical and thermal performance of the part.
Figure 31. Recommended PCB Layout
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Following is a guideline, not a requirement which the PCB designer should consider:
1. Input ceramic bypass capacitors C1 and C2 must be placed close to the D1 and S2 pins of Power Stage to help reduce parasitic
inductance and high frequency conduction loss induced by switching operation. C1 and C2 show the bypass capacitors placed close
to the part between D1 and S2. Input capacitors should be connected in parallel close to the part. Multiple input caps can be connected
depending upon the application.
2. The PHASE copper trace serves two purposes; In addition to being the current path from the Power Stage package to the output
inductor (L), it also serves as heat sink for the lower FET in the Power Stage package. The trace should be short and wide enough to
present a low resistance path for the high current flow between the Power Stage and the inductor. This is done to minimize conduction
losses and limit temperature rise. Please note that the PHASE node is a high voltage and high frequency switching node with high
noise potential. Care should be taken to minimize coupling to adjacent traces. The reference layout in figure 31 shows a good balance
between the thermal and electrical performance of Power Stage.
3. Output inductor location should be as close as possible to the Power Stage device for lower power loss due to copper trace
resistance. A shorter and wider PHASE trace to the inductor reduces the conduction loss. Preferably the Power Stage should be
directly in line (as shown in figure 31) with the inductor for space savings and compactness.
4. The PowerTrench® Technology MOSFETs used in the Power Stage are effective at minimizing phase node ringing. It allows the
part to operate well within the breakdown voltage limits. This eliminates the need to have an external snubber circuit in most cases. If
the designer chooses to use an RC snubber, it should be placed close to the part between the PHASE pad and S2 pins to dampen
the high-frequency ringing.
5. The driver IC should be placed close to the Power Stage part with the shortest possible paths for the High Side gate and Low Side
gates through a wide trace connection. This eliminates the effect of parasitic inductance and resistance between the driver and the
MOSFET and turns the devices on and off as efficiently as possible. At higher-frequency operation this impedance can limit the gate
current trying to charge the MOSFET input capacitance. This will result in slower rise and fall times and additional switching losses.
Power Stage has both the gate pins on the same side of the package which allows for back mounting of the driver IC to the board. This
provides a very compact path for the drive signals and improves efficiency of the part.
6. S2 pins should be connected to the GND plane with multiple vias for a low impedance grounding. Poor grounding can create a noise
transient offset voltage level between S2 and driver ground. This could lead to faulty operation of the gate driver and MOSFET.
7. Use multiple vias on each copper area to interconnect top, inner and bottom layers to help smooth current flow and heat conduction.
Vias should be relatively large, around 8 mils to 10 mils, and of reasonable inductance. Critical high frequency components such as
ceramic bypass caps should be located close to the part and on the same side of the PCB. If not feasible, they should be connected
from the backside via a network of low inductance vias.
www.onsemi.com
13
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
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