FDMS6673BZ [ONSEMI]
P 沟道 PowerTrench® MOSFET -30V，-82A，6.8mΩ;
| 型号： | FDMS6673BZ |
| 厂家： | 
ONSEMI |
| 描述： | P 沟道 PowerTrench® MOSFET -30V，-82A，6.8mΩ 开关 光电二极管 晶体管 |
| 文件： | 总8页 (文件大小：618K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA
Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended
or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out
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is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
May 2016
FDMS6673BZ
P-Channel PowerTrench® MOSFETꢀ
-30 V, -82 A, 6.8 m:
Features
General Description
The FDMS6673BZ has been designed to minimize losses in load
switch applications. Advancements in both silicon and package
technologies have been combined to offer the lowest rDS(on) and
ESD protection.
Max rDS(on) = 6.8 m: at VGS = -10 V, ID = -15.2 A
Max rDS(on) = 12.5 m: at VGS = -4.5 V, ID = -11.2 A
Advanced Package and Silicon Combination
for Low rDS(on)
Applications
HBM ESD Protection Level of 8 kV Typical(Note 3)
MSL1 Robust Package Design
RoHS Compliant
Load Switch in Notebook and Server
Notebook Battery Pack Power Management
MOSFET Maximum Ratings TC = 25 °C unless otherwise noted.
Symbol
VDS
VGS
Parameter
Ratings
-30
Units
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous
-Continuous
V
V
25
TC = 25 °C
TC = 100 °C
TA = 25 °C
-82
(Note 5)
(Note 5)
-52
ID
A
-Continuous
(Note 1a)
(Note 4)
-15.2
-422
73
-Pulsed
Power Dissipation
Power Dissipation
TC = 25 °C
TA = 25 °C
PD
W
(Note 1a)
(Note 1a)
2.5
TJ, TSTG
Operating and Storage Junction Temperature Range
-55 to +150
°C
Thermal Characteristics
RTJC
RTJA
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
1.7
50
°C/W
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
13 ’’
Tape Width
12 mm
Quantity
FDMS6673BZ
FDMS6673BZ
Power 56
3000 units
©2009 Fairchild Semiconductor Corporation
FDMS6673BZ Revꢀ1.7
www.fairchildsemi.com
1
Electrical Characteristics TJ = 25 °C unless otherwise noted.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
ID = -250 PA, VGS = 0 V
-30
V
'BVDSS
ꢀꢀꢀ'TJ
Breakdown Voltage Temperature
Coefficient
ID = -250 PA, referenced to 25 °C
VDS = -24 V, VGS = 0 V
-18
mV/°C
IDSS
IGSS
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
-1
PA
PA
VGS
=
25 V, VDS = 0 V
10
On Characteristics
VGS(th)
Gate to Source Threshold Voltage
V
GS = VDS, ID = -250 PA
-1.0
-1.8
7
-3.0
V
ꢀ'VGS(th)
ꢀꢀꢀ'TJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID = -250 PA, referenced to 25 °C
mV/°C
V
V
V
GS = -10 V, ID = -15.2 A
5.2
7.8
7.5
76
6.8
12.5
9.8
rDS(on)
Static Drain to Source On Resistance
Forward Transconductance
GS = -4.5 V, ID = -11.2 A
m:
GS = -10 V, ID = -15.2 A, TJ = 125 °C
gFS
VDS = -5 V, ID = -15.2 A
S
Dynamic Characteristics
Ciss
Coss
Crss
Rg
Input Capacitance
4444
781
695
4.5
5915
1040
1045
pF
pF
pF
:
VDS = -15 V, VGS = 0 V,
f = 1 MHz
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
Switching Characteristics
td(on)
tr
td(off)
tf
Turn-On Delay Time
Rise Time
14
28
97
79
93
52
13
26
26
45
ns
ns
V
DD = -15 V, ID = -15.2 A,
VGS = -10 V, RGEN = 6 :
Turn-Off Delay Time
Fall Time
156
127
130
73
ns
ns
Qg
Total Gate Charge
Total Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
V
GS = 0 V to -10 V
GS = 0 V to -5 V
nC
nC
nC
nC
Qg
V
VDD = -15 V,
ID = -15.2 A
Qgs
Qgd
Drain-Source Diode Characteristics
V
V
GS = 0 V, IS = -2.1 A
(Note 2)
0.7
0.8
33
1.20
1.25
53
VSD
Source to Drain Diode Forward Voltage
V
GS = 0 V, IS = -15.2 A
(Note 2)
trr
Reverse Recovery Time
ns
IF = -15.2 A, di/dt = 100 A/Ps
Qrr
Reverse Recovery Charge
20
32
nC
Notes:
1: R
2
is determined with the device mounted on a 1in pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
TJA
the user's board design.
is guaranteed by design while R is determined by
TCA
TJC
a. 50 °C/W when mounted on a
2
b. 125 °C/W when mounted on a
minimum pad of 2 oz copper.
1 in pad of 2 oz copper.
2: Pulse Test: Pulse Width < 300 Ps, Duty cycle < 2.0%.
3: The diode connected between the gate and source servers only as protection against ESD. No gate overvoltage rating is implied.
4: Pulsed Id please refer to Fig 11 SOA graph for more details.
5: Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal electro-mechanical application board design.
©2009 Fairchild Semiconductor Corporation
FDMS6673BZ Revꢀ1.7
www.fairchildsemi.com
2
Typical Characteristics TJ = 25 °C unless otherwise noted.
120
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
VGS = -10 V
VGS = -3 V
PULSE DURATION = 80 Ps
DUTY CYCLE = 0.5% MAX
VGS = -6 V
VGS = -4.5 V
PULSE DURATION = 80
100
80
VGS = -4 V
VGS = -3.5 V
Ps
VGS = -4 V
DUTY CYCLE = 0.5% MAX
60
40
20
0
VGS = -4.5 V
VGS = -3.5 V
VGS = -6 V
VGS = -3 V
VGS = -10 V
0
1
2
3
4
0
20
40
60
80
100
120
-VDS, DRAIN TO SOURCE VOLTAGE (V)
-ID, DRAIN CURRENT (A)
Figure 1. On Region Characteristics
Figure2. N o r m a l i z e d O n - R e s i s ta n c e
vs. Drain Current and Gate Voltage
1.6
25
ID = -15.2 A
VGS = -10 V
PULSE DURATION = 80 Ps
DUTY CYCLE = 0.5% MAX
ID = -15.2 A
1.4
1.2
1.0
0.8
0.6
20
15
10
5
TJ = 125 o
C
TJ = 25 o
C
0
-75 -50 -25
0
25 50 75 100 125 150
2
4
6
8
10
TJ,
JUNCTION TEMPERATURE ( )
oC
-VGS, GATE TO SOURCE VOLTAGE (V)
Figure 3. Normalized On Resistance
vs. Junction Temperature
Figure4. On-Resistance vs. Gate to
Source Voltage
120
100
80
60
40
20
0
200
100
PULSE DURATION = 80 Ps
DUTY CYCLE = 0.5% MAX
VGS = 0 V
VDS = -5 V
10
1
TJ = 150 oC
TJ = 25 oC
0.1
TJ = 150 oC
TJ = 25 o
TJ = -55 oC
0.01
0.001
TJ = -55 oC
4
C
0
1
2
3
5
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
-VGS, GATE TO SOURCE VOLTAGE (V)
-VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure6. Source to Drain Diode
Forward Voltage vs. Source Current
©2009 Fairchild Semiconductor Corporation
FDMS6673BZ Revꢀ1.7
www.fairchildsemi.com
3
Typical Characteristics TJ = 25 °C unless otherwise noted.
10
10000
ID = -15.2 A
8
Ciss
VDD = 10 V
6
VDD = 15 V
VDD = 20 V
4
2
0
Coss
1000
300
Crss
f = 1 MHz
= 0 V
V
GS
0
20
40
60
80
100
0.1
1
10
-VDS, DRAIN TO SOURCE VOLTAGE (V)
30
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics
Figure8. C a p a c i t a n c e v s. D r a i n
to Source Voltage
50
10
TJ = 25 oC
TJ = 100 oC
TJ = 125 o
C
1
0.01
200
100
0.1
1
10
tAV, TIME IN AVALANCHE (ms)
Figure9. U n c l a m p e d I n d u c t i v e
Switching Capability
Figure10. Maximum Continuous Drain
Current vs. Case Temperature
10-4
VGS = 0 V
10-5
10-6
10-7
10-8
10-9
TJ = 125 oC
TJ = 25 o
C
0
5
-VGS
10
15
20
25
30
,
GATE TO SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe
Operating Area
Figure 12. Igss vs. Vgss
©2009 Fairchild Semiconductor Corporation
FDMS6673BZ Revꢀ1.7
www.fairchildsemi.com
4
Typical Characteristics TJ = 25 °C unless otherwise noted.
Figure 13. Single Pulse Maximum Power Dissipation
Figure 14. Junction-to-Case Transient Thermal Response Curve
©2009 Fairchild Semiconductor Corporation
FDMS6673BZ Revꢀ1.7
www.fairchildsemi.com
5
PQFN8 5X6, 1.27P
CASE 483AE
ISSUE A
5.10
3.91
5.10
PKG
A
SEE
DETAIL B
1.27
6.61
C
L
B
8
7
6
5
8
5
0.77
4.52
3.75
5.85
5.65
C
PKG
6.15
L
KEEP OUT
AREA
1.27
1
4
1
2
3
4
TOP VIEW
0.61
1.27
3.81
LAND PATTERN
RECOMMENDATION
OPTIONAL DRAFT
ANGLE MAY APPEAR
ON FOUR SIDES
SEE
DETAIL C
5.00
4.80
OF THE PACKAGE
0.35
0.15
ꢀꢁꢂꢃ
0.10 C
0.30
0.05
0.05
0.00
SIDE VIEW
ꢀꢁꢂꢃ
8X
0.08 C
C
0.35
0.15
5.20
4.80
1.10
0.90
SEATING
PLANE
DETAIL C
DETAIL B
SCALE: 2:1
3.81
SCALE: 2:1
1.27
0.51
(8X)
0.31
NOTES: UNLESS OTHERWISE SPECIFIED
(0.34)
A. PACKAGE STANDARD REFERENCE: JEDEC MO-240,
ISSUE A, VAR. AA,.
0.10
C A B
1
2
3
4
B. DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH.
MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM.
C. ALL DIMENSIONS ARE IN MILLIMETERS.
0.76
0.51
(0.52)
D. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-2009.
E. IT IS RECOMMENDED TO HAVE NO TRACES OR
VIAS WITHIN THE KEEP OUT AREA.
6.25
5.90
+0.30
3.48
-0.10
(0.50)
(0.30)
(2X)
8
7
6
5
ꢀꢄꢅꢅꢀꢄꢂꢀ
+0.10
-0.15
0.20
(8X)
3.96
3.61
BOTTOM VIEW
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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