FDMS7700S [ONSEMI]
双 N 沟道，PowerTrench® MOSFET，30V;
| 型号： | FDMS7700S |
| 厂家： | 
ONSEMI |
| 描述： | 双 N 沟道，PowerTrench® MOSFET，30V 开关 脉冲 光电二极管 晶体管 |
| 文件： | 总13页 (文件大小：477K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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May 2014
FDMS7700S
Dual N-Channel PowerTrench® MOSFET
N-Channel: 30 V, 30 A, 7.5 mΩ N-Channel: 30 V, 40 A, 2.4 mΩ
Features
General Description
Q1: N-Channel
This device includes two specialized N-Channel MOSFETs in a
dual MLP package.The switch node has been internally
connected to enable easy placement and routing of synchronous
buck converters. The control MOSFET (Q1) and synchronous
SyncFETTM (Q2) have been designed to provide optimal power
efficiency.
Max rDS(on) = 7.5 mΩ at VGS = 10 V, ID = 12 A
Max rDS(on) = 12 mΩ at VGS = 4.5 V, ID = 10 A
Q2: N-Channel
Max rDS(on) = 2.4 mΩ at VGS = 10 V, ID = 20 A
Max rDS(on) = 2.9 mΩ at VGS = 4.5 V, ID = 18 A
Applications
RoHS Compliant
Computing
Communications
General Purpose Point of Load
Notebook VCORE
S2
S2
Q2
S2
D1
S2
5
6
7
8
4
3
2
1
G2
S1/D2
D1
D1
S2
S2
G2
D1
G1
D1
D1
D1
G1
Q1
Top
Bottom
Power 56
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
Parameter
Q1
30
Q2
30
Units
Drain to Source Voltage
Gate to Source Voltage
V
V
(Note 3)
TC = 25 °C
TA = 25 °C
±20
±20
Drain Current
-Continuous
30
40
ID
-Continuous
-Pulsed
121a
40
221b
60
A
Power Dissipation for Single Operation
TA = 25 °C
TA = 25 °C
2.21a
1.01c
2.51b
1.01d
PD
W
TJ, TSTG
Operating and Storage Junction Temperature Range
-55 to +150
°C
Thermal Characteristics
RθJA
RθJA
RθJC
Thermal Resistance, Junction to Ambient
571a
1251c
3.5
501b
1201d
2
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Case
°C/W
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
13 ”
Tape Width
Quantity
FDMS7700S
FDMS7700S
Power 56
12 mm
3000 units
1
©2009 Fairchild Semiconductor Corporation
FDMS7700S Rev.C1
www.fairchildsemi.com
Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Type
Min
Typ
Max
Units
Off Characteristics
ID = 250 μA, VGS = 0 V
ID = 1 mA, VGS = 0 V
Q1
Q2
30
30
BVDSS
Drain to Source Breakdown Voltage
V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID = 250 μA, referenced to 25 °C
Q1
Q2
15
14
mV/°C
I
D = 1 mA, referenced to 25 °C
Q1
Q2
1
500
μA
μA
IDSS
IGSS
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
VDS = 24 V, VGS = 0 V
VGS = 20 V, VDS= 0 V
Q1
Q2
100
100
nA
nA
On Characteristics
V
GS = VDS, ID = 250 μA
Q1
Q2
1
1
1.8
1.5
3
3
VGS(th)
Gate to Source Threshold Voltage
V
VGS = VDS, ID = 1 mA
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID = 250 μA, referenced to 25 °C
ID = 1 mA, referenced to 25 °C
Q1
Q2
-6
-4
mV/°C
V
V
GS = 10 V, ID = 12 A
GS = 4.5 V, ID = 10 A
6.0
8.5
8.3
7.5
12
12
Q1
Q2
VGS = 10 V, ID = 12 A , TJ = 125 °C
rDS(on)
Drain to Source On Resistance
mΩ
VGS = 10 V, ID = 20 A
VGS = 4.5 V, ID = 18 A
VGS = 10 V, ID = 20 A , TJ = 125 °C
1.9
2.2
2.1
2.4
2.9
3.4
VDS = 5 V, ID = 12 A
Q1
Q2
63
160
gFS
Forward Transconductance
S
V
DS = 5 V, ID = 20 A
Dynamic Characteristics
Q1
Q2
1315
7240
1750
9630
Q1:
Ciss
Coss
Crss
Rg
Input Capacitance
pF
pF
pF
Ω
VDS = 15 V, VGS = 0 V, f = 1 MHZ
Q1
Q2
445
2690
600
3580
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
Q2:
VDS = 15 V, VGS = 0 V, f = 1 MHZ
Q1
Q2
45
185
70
280
Q1
Q2
0.9
0.8
Switching Characteristics
Q1
Q2
8.6
21
18
34
td(on)
tr
td(off)
tf
Turn-On Delay Time
Rise Time
ns
ns
Q1:
Q1
Q2
2.5
9.2
10
18
VDD = 15 V, ID = 12 A, RGEN = 6 Ω
Q1
Q2
20
58
32
93
Q2:
Turn-Off Delay Time
Fall Time
ns
VDD = 15 V, ID = 20 A, RGEN = 6 Ω
Q1
Q2
2.3
6.8
10
14
ns
Q1
Q2
20
105
28
147
Qg
Total Gate Charge
Total Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
VGS = 0 V to 10 V
Q1
nC
nC
nC
nC
VDD = 15 V,
ID = 12 A
Q1
Q2
9.3
48
13
67
Qg
VGS = 0 V to 4.5 V
Q1
Q2
4.3
19
Q2
VDD = 15 V,
Qgs
Qgd
Q1
Q2
2.2
11
I
D = 20 A
©2009 Fairchild Semiconductor Corporation
FDMS7700S Rev.C1
www.fairchildsemi.com
Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Type
Min
Typ
Max
Units
Drain-Source Diode Characteristics
V
V
GS = 0 V, IS = 12 A
GS = 0 V, IS = 20 A
(Note 2) Q1
(Note 2) Q2
0.8
0.7
1.2
1.2
VSD
trr
Source to Drain Diode Forward Voltage
Reverse Recovery Time
V
Q1
Q2
27
53
43
85
Q1
ns
nC
IF = 12 A, di/dt = 100 A/μs
Q2
IF = 20 A, di/dt = 300 A/μs
Q1
Q2
10
100
18
160
Qrr
Reverse Recovery Charge
Notes:
2
1:
R
is determined with the device mounted on a 1 in pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
is guaranteed by design while R is determined
θCA
θJA
θJC
by the user's board design.
b. 50 °C/W when mounted on
a 1 in pad of 2 oz copper
a. 57 °C/W when mounted on
a 1 in pad of 2 oz copper
2
2
c. 125 °C/W when mounted on
minimum pad of 2 oz copper
a
d. 120 °C/W when mounted on
minimum pad of 2 oz copper
a
2: Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3: As an N-ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied.
©2009 Fairchild Semiconductor Corporation
FDMS7700S Rev.C1
www.fairchildsemi.com
Typical Characteristics (Q1 N-Channel)TJ = 25°C unless otherwise noted
40
30
20
10
0
4
3
2
1
0
VGS = 10 V
= 6 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
V
GS
VGS = 4.5 V
VGS = 4 V
VGS = 3.5 V
VGS = 4 V
VGS = 4.5 V
VGS = 3.5 V
0.5
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 6 V
VGS = 10 V
0.0
1.0
1.5
2.0
0
10
20
30
40
VDS, DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
Figure 1. On Region Characteristics
Figure2. No rma li zed O n-Re si stan ce
vs Drain Current and Gate Voltage
40
1.6
1.4
1.2
1.0
0.8
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
ID = 12 A
VGS = 10 V
30
ID = 12 A
20
TJ = 125 oC
10
TJ = 25 o
C
0
2
4
6
8
10
-75 -50 -25
0
25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 3. Normalized On Resistance
vs Junction Temperature
Figure4. On-Resistance vs Gate to
Source Voltage
40
40
VGS = 0 V
PULSE DURATION = 80 μs
10
DUTY CYCLE = 0.5% MAX
30
20
10
0
VDS = 5 V
1
TJ = 150 o
C
TJ = 150 o
C
TJ = 25 oC
0.1
TJ = 25 o
C
0.01
0.001
TJ = -55 o
C
TJ = -55 o
C
1.5
2.0
2.5
3.0
3.5
4.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
VGS, GATE TO SOURCE VOLTAGE (V)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure6. Source to Drain Diode
Forward Voltage vs Source Current
©2009 Fairchild Semiconductor Corporation
FDMS7700S Rev.C1
www.fairchildsemi.com
Typical Characteristics (Q1 N-Channel)TJ = 25°C unless otherwise noted
10
2000
1000
ID = 12 A
Ciss
8
VDD = 10 V
Coss
6
VDD = 15 V
100
4
VDD = 20 V
2
Crss
f = 1 MHz
= 0 V
V
GS
0
10
0.1
1
10
30
0
5
10
Q , GATE CHARGE (nC)
15
20
VDS, DRAIN TO SOURCE VOLTAGE (V)
g
Figure 7. Gate Charge Characteristics
Figure8. C a p a c i t a n c e v s D r a i n
to Source Voltage
60
100
10
RθJC = 3.5 oC/W
VGS = 10 V
100us
1 ms
40
20
0
VGS = 4.5 V
10 ms
1
THIS AREA IS
LIMITED BY r
100 ms
DS(on)
Limited by Package
SINGLE PULSE
TJ = MAX RATED
1s
0.1
10s
DC
R
θJA = 125 oC/W
TA = 25 oC
0.01
0.01
25
50
75
100
125
150
0.1
1
10
100
200
TC, CASE TEMPERATURE (oC)
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure9. Maximum Continuous Drain
Current vs Case Temperature
Figure10. Forward Bias Safe
Operating Area
1000
100
10
SINGLE PULSE
R
θJA = 125 oC/W
TA = 25 o
C
1
0.5
10-4
10-3
10-2
10-1
t, PULSE WIDTH (s)
1
10
100
1000
Figure 11. Single Pulse Maximum Power Dissipation
©2009 Fairchild Semiconductor Corporation
FDMS7700S Rev.C1
www.fairchildsemi.com
Typical Characteristics (Q1 N-Channel)TJ = 25°C unless otherwise noted
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
0.1
0.05
0.02
0.01
0.1
P
DM
t
1
0.01
t
SINGLE PULSE
2
R
θJA = 125 oC/W
NOTES:
DUTY FACTOR: D = t /t
1
2
x R
(Note 1c)
PEAK T = P
J
x Z
+ T
DM
θJA
θJA A
0.001
10-4
10-3
10-2
10-1
t, RECTANGULAR PULSE DURATION (sec)
1
10
100
1000
Figure 12. Junction-to-Ambient Transient Thermal Response Curve
©2009 Fairchild Semiconductor Corporation
FDMS7700S Rev.C1
www.fairchildsemi.com
Typical Characteristics (Q2 SyncFET)
60
6
5
4
3
2
1
0
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80 μs
50
DUTY CYCLE = 0.5% MAX
VGS = 2.5 V
VGS = 10 V
40
30
20
10
0
VGS = 4.5 V
VGS = 3.5 V
VGS = 3 V
VGS = 3 V
VGS = 2.5 V
VGS = 3.5 V
10
VGS = 4.5 V
VGS = 10 V
50
0
0.2
0.4
0.6
0.8
1.0
0
20
30
40
60
VDS, DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
Figure 13. On-Region Characteristics
Figure 14. Normalized on-Resistance vs Drain
Current and Gate Voltage
1.6
10
ID = 20 A
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
8
VGS = 10 V
1.4
1.2
1.0
0.8
0.6
ID = 20 A
6
4
TJ = 125 o
C
2
0
TJ = 25 o
C
-75 -50 -25
0
25 50 75 100 125 150
2
4
6
8
10
TJ, JUNCTION TEMPERATURE (oC)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 16. On-Resistance vs Gate to
Source Voltage
Figure 15. Normalized On-Resistance
vs Junction Temperature
60
60
VGS = 0 V
TJ = 125 o
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
10
1
50
40
30
20
10
0
C
VDS = 5 V
TJ = 25 oC
TJ = 125 o
C
0.1
TJ = 25 o
C
TJ = -55 o
C
0.01
0.001
TJ = -55 o
C
1.0
1.5
2.0
2.5
3.0
0
0.2
0.4
0.6
0.8
1.0
VGS, GATE TO SOURCE VOLTAGE (V)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 17. Transfer Characteristics
Figure 18. Source to Drain Diode
Forward Voltage vs Source Current
©2009 Fairchild Semiconductor Corporation
FDMS7700S Rev.C1
www.fairchildsemi.com
Typical Characteristics (Q2 SyncFET)
30000
10000
10
ID = 20 A
Ciss
8
VDD = 10 V
6
Coss
VDD = 15 V
1000
100
4
VDD = 20 V
Crss
2
0
f = 1 MHz
= 0 V
V
GS
30
0.1
1
10
0
40
80
120
VDS, DRAIN TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
Figure 20. Capacitance vs Drain
to Source Voltage
Figure 19. Gate Charge Characteristics
150
100
10
RθJC = 2 oC/W
VGS = 10 V
1 ms
100
50
0
10 ms
VGS = 4.5 V
THIS AREA IS
1
100 ms
LIMITED BY r
DS(on)
1 s
SINGLE PULSE
TJ = MAX RATED
0.1
10 s
DC
R
θJA = 120 oC/W
A = 25 oC
Limited by Package
T
0.01
25
50
75
100
125
150
0.01
0.1
1
10
100
TC, CASE TEMPERATURE (oC)
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 21. Maximum Continuous Drain
Current vs Case Temperature
Figure 22. Forward Bias Safe Operating Area
1000
100
10
SINGLE PULSE
R
θJA = 120 oC/W
T
A = 25 o
C
1
0.5
10-3
10-2
10-1
1
10
100
1000
t, PULSE WIDTH (s)
Figure 23. Single Pulse Maximum Power Dissipation
©2009 Fairchild Semiconductor Corporation
FDMS7700S Rev.C1
www.fairchildsemi.com
Typical Characteristics (Q2 SyncFET)
2
1
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
0.01
0.1
P
DM
t
1
0.01
0.001
t
2
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t /t
θJA = 120 oC/W
1
2
R
PEAK T = P
x Z
x R
+ T
J
DM
θJA
θJA A
(Note 1d)
10-3
10-2
10-1
1
10
100
1000
t, RECTANGULAR PULSE DURATION (s)
Figure 24. Junction-to-Ambient Transient Thermal Response Curve
©2009 Fairchild Semiconductor Corporation
FDMS7700S Rev.C1
www.fairchildsemi.com
Typical Characteristics (continued)
TM
SyncFET Schottky Body Diode
Characteristics
Fairchild’s SyncFETTM process embeds a Schottky diode in
parallel with PowerTrench MOSFET. This diode exhibits similar
characteristics to a discrete external Schottky diode in parallel
Schottky barrier diodes exhibit significant leakage at high tem-
perature and high reverse voltage. This will increase the power
in the device.
®
with
a MOSFET. Figure 25 shows the reverse recovery
characteristic of the FDMS7700S.
10-1
12
9
TJ = 125 o
C
C
10-2
10-3
10-4
10-5
6
didt = 300 A/μs
TJ = 100 o
3
0
-3
-6
TJ = 25 o
C
0
5
10
15
20
25
30
100
150
200
250
300
TIME (ns)
VDS, REVERSE VOLTAGE (V)
Figure 26. SyncFETTM Body Diode Reverse
Leakage vs. Drain-Source Voltage
Figure 25. FDMS7700S SyncFETTM Body
Diode Reverse Recovery Characteristic
©2009 Fairchild Semiconductor Corporation
FDMS7700S Rev.C1
www.fairchildsemi.com
0.05 C
B
5.00
A
2X
4.46
1.27
0.65
8
6
7
5
0.63(5X)
0.25
0.40
6.00
2.67
6.30
0.54
0.66
0.05 C
PIN#1 IDENT
2X
0.92
ꢀꢁꢄꢃꢀꢁꢀꢃ
0.10 C
ꢀꢁꢂꢀꢀꢁꢀꢃ
0.08 C
2
4
1
3
0.65 (5X)
ꢀꢁꢀꢂꢃꢀꢁꢀꢂꢃ
4.00
C
SIDE VIEW
SEATING
PLANE
RECOMMENDED LAND PATTERN
(OPTION 1 - FUSED LEADS 5,6,7)
ꢃꢁꢀꢀꢀꢁꢀꢃ
ꢅꢁꢆꢀꢀꢁꢀꢃ
(0.34)4X
ꢀꢁꢉꢅꢀꢁꢀꢃꢊꢃ;ꢋ
4.46
1.27
2
1
3
4
PIN#1 IDENT
0.65(8X)
8
6
7
5
0.63(8X)
ꢀꢁꢌꢂꢀꢁꢀꢃ
0.40
(0.66)
ꢀꢁꢃꢃꢀꢁꢀꢃ
ꢈꢁꢀꢀꢀꢁꢀꢃ
2.67
ꢂꢁꢈꢄꢀꢁꢀꢃ
6.30
0.54
0.66
0.45
0.92
5
8
6
7
ꢀꢁꢃꢇꢀꢁꢀꢃꢊꢃ;ꢋ
0.10 C A B
0.05 C
1.27
ꢅꢁꢆꢇꢀꢁꢀꢃ
2
4
1
3
4.00
BOTTOM VIEW
RECOMMENDED LAND PATTERN
(OPTION 2 - ISOLATED LEADS)
NOTES:
A. PACKAGE DOES NOT FULLY CONFORM TO
JEDEC STANDARD.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 2009.
D. LAND PATTERN RECOMMENDATION IS
EXISTING INDUSTRY LAND PATTERN.
E. DRAWING FILENAME: MKT-MLP08Prev2.
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