FDMS86102LZ [ONSEMI]
N 沟道屏蔽门极 PowerTrench® MOSFET 100 V，22A，25mΩ;
| 型号： | FDMS86102LZ |
| 厂家： | 
ONSEMI |
| 描述： | N 沟道屏蔽门极 PowerTrench® MOSFET 100 V，22A，25mΩ 开关 脉冲 光电二极管 晶体管 |
| 文件： | 总8页 (文件大小：443K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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October 2014
FDMS86102LZ
N-Channel Shielded Gate PowerTrench® MOSFET
100 V, 22 A, 25 mΩ
Features
General Description
Shielded Gate MOSFET Technology
Max rDS(on) = 25 mΩ at VGS = 10 V, ID = 7 A
Max rDS(on) = 37 mΩ at VGS = 4.5 V, ID = 5.8 A
HBM ESD protection level > 6 KV typical (Note 4)
100% UIL Tested
This N-Channel logic Level MOSFETs are produced using
Fairchild Semiconductor‘s advanced PowerTrench® process
that incorporates Shielded Gate technology. This process has
been optimized for the on-state resistance and yet maintain
superior switching performance. G-S zener has been added to
enhance ESD voltage level.
Applications
RoHS Compliant
DC - DC Conversion
Inverter
Synchronous Rectifier
Bottom
Top
Pin 1
D
S
S
S
S
S
G
D
D
S
D
D
D
G
D
D
Power 56
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
Parameter
Ratings
Units
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous
-Continuous
100
V
V
±20
TC = 25 °C
TA = 25 °C
22
ID
(Note 1a)
(Note 3)
7
A
-Pulsed
40
EAS
Single Pulse Avalanche Energy
Power Dissipation
84
69
mJ
W
TC = 25 °C
TA = 25 °C
PD
Power Dissipation
(Note 1a)
2.5
TJ, TSTG
Operating and Storage Junction Temperature Range
-55 to +150
°C
Thermal Characteristics
RθJC
RθJA
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
1.8
50
°C/W
(Note 1a)
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
13 ’’
Tape Width
12 mm
Quantity
FDMS86102Z
FDMS86102LZ
Power 56
3000 units
©2011 Fairchild Semiconductor Corporation
FDMS86102LZ Rev.C2
1
www.fairchildsemi.com
Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
ID = 250 μA, VGS = 0 V
100
V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
I
D = 250 μA, referenced to 25 °C
70
mV/°C
IDSS
IGSS
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
VDS = 80 V, VGS = 0 V
VGS = ±20 V, VDS = 0 V
1
μA
μA
±10
On Characteristics
VGS(th)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250 μA
1.0
1.5
-6
2.5
V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
I
D = 250 μA, referenced to 25 °C
mV/°C
V
GS = 10 V, ID = 7 A
18.6
23.5
31.2
26
25
37
42
rDS(on)
gFS
Static Drain to Source On Resistance
Forward Transconductance
VGS = 4.5 V, ID = 5.8 A
mΩ
VGS = 10 V, ID = 7 A, TJ = 125 °C
VDS = 5 V, ID = 7 A
S
Dynamic Characteristics
Ciss
Coss
Crss
Rg
Input Capacitance
979
175
8.9
1305
235
15
pF
pF
pF
Ω
VDS = 50 V, VGS = 0 V,
f = 1 MHz
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
0.9
Switching Characteristics
td(on)
tr
td(off)
tf
Turn-On Delay Time
Rise Time
6.7
2.6
19
14
10
35
10
22
11
ns
ns
VDD = 50 V, ID = 7 A,
V
GS = 10 V, RGEN = 6 Ω
Turn-Off Delay Time
Fall Time
ns
2.5
16
ns
Qg(TOT)
Qg(TOT)
Qgs
Total Gate Charge
Total Gate Charge
Total Gate Charge
Gate to Drain “Miller” Charge
VGS = 0 V to 10 V
VGS = 0 V to 4.5 V
nC
nC
nC
nC
VDD = 50 V,
D = 7 A
7.8
2.4
2.6
I
Qgd
Drain-Source Diode Characteristics
V
GS = 0 V, IS = 7 A
(Note 2)
(Note 2)
0.81
0.72
35
1.3
1.2
57
VSD
Source to Drain Diode Forward Voltage
V
VGS = 0 V, IS = 2 A
trr
Reverse Recovery Time
ns
IF = 7 A, di/dt = 100 A/μs
Qrr
Reverse Recovery Charge
25
40
nC
NOTES:
2
1. R
is determined with the device mounted on a 1 in pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
is guaranteed by design while R
is determined by
θJA
θJC
θCA
the user's board design.
125 °C/W when mounted on
a minimum pad of 2 oz copper
b.
a.
50 °C/W when mounted on a
1 in pad of 2 oz copper
2
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3. Starting T = 25 °C; N-ch: L = 1 mH, I = 13 A, V = 90 V, V = 10 V.
J
AS
DD
GS
4. The diode connected between gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
©2011 Fairchild Semiconductor Corporation
FDMS86102LZ Rev. C2
2
www.fairchildsemi.com
Typical Characteristics TJ = 25 °C unless otherwise noted
40
6
5
4
3
2
1
0
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 3.5 V
VGS = 2.5 V
30
VGS = 10 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 4.5 V
VGS = 3 V
20
VGS = 3.5 V
VGS = 3 V
VGS = 4.5 V
10
VGS = 2.5 V
VGS = 10 V
0
0
1
2
3
4
5
0
10
20
30
40
VDS, DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
Figure 1. On-Region Characteristics
Figure2. N o r m a l i z e d O n - R e s i s ta n c e
vs Drain Current and Gate Voltage
2.0
100
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
ID = 7 A
ID = 7 A
1.8
1.6
1.4
1.2
1.0
0.8
0.6
VGS = 10 V
80
60
40
20
0
TJ = 125 o
C
TJ = 25 oC
-75 -50 -25
0
25 50 75 100 125 150
2
4
6
8
10
TJ, JUNCTION TEMPERATURE (oC)
VGS, GATE TO SOURCE VOLTAGE (V)
F ig u re 3. No rmal i zed O n-Re si stan ce
vs Junction Temperature
Figure4. On-Resistance vs Gate to
Source Voltage
40
40
VGS = 0 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
10
30
20
10
0
TJ = 150 o
C
VDS = 5 V
1
TJ = 25 oC
0.1
TJ = 150 oC
TJ = 25 oC
TJ = -55 oC
0.01
0.001
TJ = -55 o
C
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
VGS, GATE TO SOURCE VOLTAGE (V)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure6. Source to Drain Diode
Forward Voltage vs Source Current
©2011 Fairchild Semiconductor Corporation
FDMS86102LZ Rev. C2
3
www.fairchildsemi.com
Typical Characteristics TJ = 25 °C unless otherwise noted
10
5000
1000
ID = 7 A
Ciss
VDD = 50 V
8
VDD = 25 V
VDD = 75 V
Coss
6
4
2
0
100
10
1
Crss
f = 1 MHz
= 0 V
V
GS
0
4
8
12
16
0.1
1
10
100
VDS, DRAIN TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics
Figure8. C a p a c i t a n c e v s D r a i n
to Source Voltage
40
32
24
16
8
50
10
TJ = 25 o
C
VGS = 10 V
TJ = 100 o
C
VGS = 4.5 V
Limited by Package
TJ = 125 o
C
RθJC = 1.8 oC/W
0
1
25
50
75
100
125
150
0.001
0.01
0.1
1
10 20
TC, CASE TEMPERATURE (oC)
tAV, TIME IN AVALANCHE (ms)
Figure9. U n c l a m p e d I n d u c t i v e
Switching Capability
Figure10. Maximum Continuous Drain
Current vs Case Temperature
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
50
VDS = 0 V
10
1
100 us
1 ms
TJ = 125 oC
10 ms
THIS AREA IS
LIMITED BY rDS(on)
100 ms
TJ = 25 o
C
SINGLE PULSE
TJ = MAX RATED
RθJA = 125 oC/W
0.1
1 s
10 s
DC
T
A = 25 oC
0.01
0.005
0
4
8
12
16
20
24
28
32
0.01
0.1
1
10
100
500
VDS, DRAIN to SOURCE VOLTAGE (V)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 11. Gate Leakage Current vs
Gate to Source Voltage
Figure12. Forward Bias Safe
Operating Area
©2011 Fairchild Semiconductor Corporation
FDMS86102LZ Rev. C2
4
www.fairchildsemi.com
Typical Characteristics TJ = 25 °C unless otherwise noted
1000
100
10
SINGLE PULSE
RθJA = 125 oC/W
T
A = 25 o
C
1
0.5
10-4
10-3
10-2
10-1
1
10
100
1000
t, PULSE WIDTH (sec)
Figure 13. Single Pulse Maximum Power Dissipation
2
1
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.01
0.1
P
DM
0.05
0.02
0.01
t
1
t
2
NOTES:
DUTY FACTOR: D = t /t
SINGLE PULSE
θJA = 125 oC/W
1
2
R
PEAK T = P
J
x Z
x R
+ T
θJA A
DM
θJA
0.001
10-4
10-3
10-2
10-1
t, RECTANGULAR PULSE DURATION (sec)
1
10
100
1000
Figure 14. Junction-to-Ambient Transient Thermal Response Curve
©2011 Fairchild Semiconductor Corporation
FDMS86102LZ Rev. C2
5
www.fairchildsemi.com
PQFN8 5X6, 1.27P
CASE 483AE
ISSUE A
5.10
3.91
5.10
PKG
A
SEE
DETAIL B
1.27
6.61
C
L
B
8
7
6
5
8
5
0.77
4.52
3.75
5.85
5.65
C
PKG
6.15
L
KEEP OUT
AREA
1.27
1
4
1
2
3
4
TOP VIEW
0.61
1.27
3.81
LAND PATTERN
RECOMMENDATION
OPTIONAL DRAFT
ANGLE MAY APPEAR
ON FOUR SIDES
SEE
DETAIL C
5.00
4.80
OF THE PACKAGE
0.35
0.15
ꢀꢁꢂꢃ
0.10 C
0.30
0.05
0.05
0.00
SIDE VIEW
ꢀꢁꢂꢃ
8X
0.08 C
C
0.35
0.15
5.20
4.80
1.10
0.90
SEATING
PLANE
DETAIL C
DETAIL B
SCALE: 2:1
3.81
SCALE: 2:1
1.27
0.51
(8X)
0.31
NOTES: UNLESS OTHERWISE SPECIFIED
(0.34)
A. PACKAGE STANDARD REFERENCE: JEDEC MO-240,
ISSUE A, VAR. AA,.
0.10
C A B
1
2
3
4
B. DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH.
MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM.
C. ALL DIMENSIONS ARE IN MILLIMETERS.
0.76
0.51
(0.52)
D. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-2009.
E. IT IS RECOMMENDED TO HAVE NO TRACES OR
VIAS WITHIN THE KEEP OUT AREA.
6.25
5.90
+0.30
3.48
-0.10
(0.50)
(0.30)
(2X)
8
7
6
5
ꢀꢄꢅꢅꢀꢄꢂꢀ
+0.10
-0.15
0.20
(8X)
3.96
3.61
BOTTOM VIEW
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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