FDMS86105 [ONSEMI]
N 沟道，屏蔽门极，PowerTrench® MOSFET，100V，26A，34mΩ;
| 型号： | FDMS86105 |
| 厂家： | 
ONSEMI |
| 描述： | N 沟道，屏蔽门极，PowerTrench® MOSFET，100V，26A，34mΩ PC 开关 脉冲 光电二极管 晶体管 |
| 文件： | 总8页 (文件大小：404K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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October 2014
FDMS86105
N-Channel Shielded Gate PowerTrench® MOSFET
100 V, 26 A, 34 mΩ
Features
General Description
This N-Channel MOSFET is produced using Fairchild
Shielded Gate MOSFET Technology
®
Semiconductor’s advanced PowerTrench
process that
Max rDS(on) = 34 mΩ at VGS = 10 V, ID = 6 A
Max rDS(on) = 54 mΩ at VGS = 6 V, ID = 4.5 A
incorporates Shielded Gate technology. This process has been
optimized for the on-state resistance and yet maintain superior
switching performance.
Advanced package and silicon combination for low rDS(on) and
high efficiency
Applications
MSL1 robust package design
100% UIL tested
Primary DC-DC
Secondary DC-DC
Load Switch
RoHS Compliant
Bottom
Top
Pin 1
S
S
D
D
D
D
S
S
G
S
S
G
D
D
D
D
Power 56
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
Parameter
Ratings
Units
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous
-Continuous
100
V
V
±20
TC = 25 °C
TA = 25 °C
26
ID
(Note 1a)
(Note 3)
(Note 1a)
6
A
-Pulsed
30
EAS
Single Pulse Avalanche Energy
Power Dissipation
50
48
mJ
W
TC = 25 °C
TA = 25 °C
PD
Power Dissipation
2.5
TJ, TSTG
Operating and Storage Junction Temperature Range
-55 to +150
°C
Thermal Characteristics
RθJC
RθJA
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
2.6
50
°C/W
(Note 1a)
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
13 ’’
Tape Width
12 mm
Quantity
FDMS86105
FDMS86105
Power 56
3000 units
1
©2011 Fairchild Semiconductor Corporation
FDMS86105 Rev.C2
www.fairchildsemi.com
Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
ID = 250 μA, VGS = 0 V
100
V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
I
D = 250 μA, referenced to 25 °C
70
mV/°C
IDSS
IGSS
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
VDS = 80 V, VGS = 0 V
VGS = ±20 V, VDS = 0 V
1
μA
±100
nA
On Characteristics
VGS(th)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250 μA
2.0
2.8
-9
4.0
V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
I
D = 250 μA, referenced to 25 °C
GS = 10 V, ID = 6 A
mV/°C
V
27
37
46
15
34
54
57
rDS(on)
gFS
Static Drain to Source On Resistance
Forward Transconductance
VGS = 6 V, ID = 4.5 A
mΩ
VGS = 10 V, ID = 6 A, TJ = 125 °C
VDS = 10 V, ID = 6 A
S
Dynamic Characteristics
Ciss
Coss
Crss
Rg
Input Capacitance
483
114
5
645
155
10
pF
pF
pF
Ω
VDS = 50 V, VGS = 0 V,
f = 1 MHz
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
0.9
Switching Characteristics
td(on)
tr
td(off)
tf
Turn-On Delay Time
Rise Time
6.7
2.1
12
14
10
22
10
11
6
ns
ns
VDD = 50 V, ID = 6 A,
V
GS = 10 V, RGEN = 6 Ω
Turn-Off Delay Time
Fall Time
ns
2.4
7.5
4.2
2.1
1.7
ns
Qg
Total Gate Charge
Total Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
VGS = 0 V to 10 V
VGS = 0 V to 5 V
nC
nC
nC
nC
Qg
VDD = 50 V,
D = 6 A
I
Qgs
Qgd
Drain-Source Diode Characteristics
V
GS = 0 V, IS = 2 A
(Note 2)
(Note 2)
0.76
0.82
38
1.2
1.3
61
VSD
Source-Drain Diode Forward Voltage
V
VGS = 0 V, IS = 6 A
trr
Reverse Recovery Time
ns
IF = 6 A, di/dt = 100 A/μs
Qrr
Reverse Recovery Charge
32
51
nC
Notes:
2
1. R
is determined with the device mounted on a 1 in pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
is guaranteed by design while R is determined by
θCA
θJA
θJC
the user's board design.
a. 50 °C/W when mounted on a
b. 125 °C/W when mounted on a
minimum pad of 2 oz copper.
2
1 in pad of 2 oz copper.
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3. Starting T = 25 °C, L = 1 mH, I = 10 A, V = 90 V, V = 10 V.
J
AS
DD
GS
©2011 Fairchild Semiconductor Corporation
FDMS86105 Rev.C2
www.fairchildsemi.com
2
Typical Characteristics TJ = 25 °C unless otherwise noted
30
4
3
2
1
0
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 5 V
25
VGS = 10 V
VGS = 7 V
20
VGS = 6 V
VGS = 6 V
VGS = 7 V
15
10
5
VGS = 5 V
VGS = 10 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0
0
1
2
3
4
5
0
5
10
15
20
25
30
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 1. On Region Characteristics
Figure2. N o r m a l i z e d O n - R e s i s ta n c e
vs Drain Current and Gate Voltage
2.0
160
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
ID = 6 A
ID = 6 A
1.8
1.6
1.4
1.2
1.0
0.8
0.6
VGS = 10 V
120
80
40
0
TJ = 125 o
C
TJ = 25 o
C
-75 -50 -25
0
25 50 75 100 125 150
4
5
6
7
8
9
10
TJ, JUNCTION TEMPERATURE (oC)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure4. On-Resistance vs Gate to
Source Voltage
Figure 3. Normalized On Resistance
vs Junction Temperature
30
30
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 0 V
10
25
20
15
10
5
VDS = 5 V
1
TJ = 150 o
C
TJ = 150 o
C
TJ = 25 o
C
0.1
TJ = 25 o
C
TJ = -55 o
C
TJ = -55 o
C
0.01
0.001
0
2
3
4
5
6
7
0.0
0.2
0.4
0.6
0.8
1.0
1.2
VGS, GATE TO SOURCE VOLTAGE (V)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure6. Source to Drain Diode
Forward Voltage vs Source Current
©2011 Fairchild Semiconductor Corporation
FDMS86105 Rev.C2
www.fairchildsemi.com
3
Typical Characteristics TJ = 25 °C unless otherwise noted
10
1000
100
10
ID = 6 A
VDD = 50 V
Ciss
8
VDD = 25 V
VDD = 75 V
6
4
2
0
Coss
Crss
f = 1 MHz
= 0 V
V
GS
1
0.1
0
2
4
Q , GATE CHARGE (nC)
6
8
1
10
100
VDS, DRAIN TO SOURCE VOLTAGE (V)
g
Figure 7. Gate Charge Characteristics
Figure8. C a p a c i t a n c e v s D r a i n
to Source Voltage
30
30
25
20
15
10
5
TJ = 25 oC
10
VGS = 10 V
TJ = 100 oC
VGS = 6 V
TJ = 125 o
C
RθJC = 2.6 oC/W
50
1
0.001
0
25
0.01
0.1
1
10
75
100
125
150
TC, CASE TEMPERATURE (oC)
tAV, TIME IN AVALANCHE (ms)
Figure9. U n c l a m p e d I n d u c t i v e
Switching Capability
Figure10. Maximum Continuous Drain
Current vs Case Temperature
40
10
1000
VGS = 10 V
100 μs
100
10
1 ms
1
0.1
10 ms
THIS AREA IS
LIMITED BY r
DS(on)
100 ms
SINGLE PULSE
TJ = MAX RATED
SINGLE PULSE
θJA = 125 oC/W
1 s
R
R
θJA = 125 oC/W
A = 25 oC
10 s
DC
A = 25 oC
1
T
T
0.01
0.5
10-4
10-3
10-2
t, PULSE WIDTH (sec)
10-1
1
10
0.01
0.1
1
10
100
500
100 1000
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe
Operating Area
Figure12. Single Pulse Maximum
Power Dissipation
©2011 Fairchild Semiconductor Corporation
FDMS86105 Rev.C2
www.fairchildsemi.com
4
Typical Characteristics TJ = 25 °C unless otherwise noted
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
0.1
0.05
0.02
0.01
0.1
P
DM
t
1
t
2
0.01
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t /t
R
θJA = 125 oC/W
1
2
PEAK T = P
J
x Z
x R
+ T
DM
θJA
θJA A
0.001
10-4
10-3
10-2
10-1
t, RECTANGULAR PULSE DURATION (sec)
1
10
100
1000
Figure 13. Junction-to-Ambient Transient Thermal Response Curve
©2011 Fairchild Semiconductor Corporation
FDMS86105 Rev.C2
www.fairchildsemi.com
5
PQFN8 5X6, 1.27P
CASE 483AE
ISSUE A
5.10
3.91
5.10
PKG
A
SEE
DETAIL B
1.27
6.61
C
L
B
8
7
6
5
8
5
0.77
4.52
3.75
5.85
5.65
C
PKG
6.15
L
KEEP OUT
AREA
1.27
1
4
1
2
3
4
TOP VIEW
0.61
1.27
3.81
LAND PATTERN
RECOMMENDATION
OPTIONAL DRAFT
ANGLE MAY APPEAR
ON FOUR SIDES
SEE
DETAIL C
5.00
4.80
OF THE PACKAGE
0.35
0.15
ꢀꢁꢂꢃ
0.10 C
0.30
0.05
0.05
0.00
SIDE VIEW
ꢀꢁꢂꢃ
8X
0.08 C
C
0.35
0.15
5.20
4.80
1.10
0.90
SEATING
PLANE
DETAIL C
DETAIL B
SCALE: 2:1
3.81
SCALE: 2:1
1.27
0.51
(8X)
0.31
NOTES: UNLESS OTHERWISE SPECIFIED
(0.34)
A. PACKAGE STANDARD REFERENCE: JEDEC MO-240,
ISSUE A, VAR. AA,.
0.10
C A B
1
2
3
4
B. DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH.
MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM.
C. ALL DIMENSIONS ARE IN MILLIMETERS.
0.76
0.51
(0.52)
D. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-2009.
E. IT IS RECOMMENDED TO HAVE NO TRACES OR
VIAS WITHIN THE KEEP OUT AREA.
6.25
5.90
+0.30
3.48
-0.10
(0.50)
(0.30)
(2X)
8
7
6
5
ꢀꢄꢅꢅꢀꢄꢂꢀ
+0.10
-0.15
0.20
(8X)
3.96
3.61
BOTTOM VIEW
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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相关型号：
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