FDP3652 [ONSEMI]
N-Channel PowerTrench® MOSFET, 100V, 61A, 16mΩ;
| 型号： | FDP3652 |
| 厂家： | 
ONSEMI |
| 描述： | N-Channel PowerTrench® MOSFET, 100V, 61A, 16mΩ 局域网 开关 晶体管 |
| 文件： | 总15页 (文件大小：765K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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October 2013
FDP3652 / FDB3652
N-Channel PowerTrench MOSFET
100 V, 61 A, 16 mΩ
®
Applications
Features
• Synchronous Rectification for ATX / Server / Telecom PSU
•
•
•
•
•
rDS(on) = 14 mΩ ( Typ.), VGS = 10 V, ID = 61 A
Qg(tot) = 41 nC ( Typ.), VGS = 10 V
Low Miller Charge
•
•
Battery Protection Circuit
Motor drives and Uninterruptible Power Supplies
Low QRR Body Diode
• Micro Solar Inverter
UIS Capability (Single Pulse and Repetitive Pulse)
Formerly developmental type 82769
D
D
G
G
D2-PAK
G
D
S
S
TO-220
S
MOSFET Maximum Ratings TC = 25°C unless otherwise noted
Symbol
VDSS
VGS
Parameter
FDP3652 / FDB3652
Unit
V
Drain to Source Voltage
Gate to Source Voltage
Drain Current
100
±20
V
Continuous (TC = 25oC, VGS = 10V)
Continuous (TC = 100oC, VGS = 10V)
Continuous (Tamb = 25oC, VGS = 10V) with RθJA = 43oC/W)
Pulsed
61
A
ID
43
9
A
A
Figure 4
182
A
EAS
Single Pulse Avalanche Energy (Note 1)
Power dissipation
mJ
W
150
PD
Derate above 25oC
W/oC
oC
1.0
TJ, TSTG
Operating and Storage Temperature
-55 to 175
Thermal Characteristics
RθJC
RθJA
RθJA
Thermal Resistance Junction to Case TO-220, D2-PAK
Thermal Resistance Junction to Ambient TO-220, D2-PAK (Note 2)
Thermal Resistance Junction to Ambient D2-PAK, 1in2 copper pad area
1.0
62
43
oC/W
oC/W
oC/W
©2003 Fairchild Semiconductor Corporation
FDP3652 / FDB3652 Rev. C0
www.fairchildsemi.com
1
Package Marking and Ordering Information
Device Marking
Device
FDB3652
FDP3652
Package
D2-PAK
TO-220
Reel Size
330 mm
Tube
Tape Width
24 mm
Quantity
800 units
50 units
FDB3652
FDP3652
N/A
Electrical Characteristics TC = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
ID = 250µA, VGS = 0V
100
-
-
-
-
-
V
V
DS = 80V
-
-
-
1
IDSS
µA
nA
VGS = 0V
TC= 150oC
250
±100
IGSS
VGS = ±20V
On Characteristics
VGS(TH)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250µA
D = 61A, VGS = 10V
ID = 30A, VGS = 6V
2
-
-
4
V
I
0.014 0.016
0.018 0.026
-
rDS(ON)
Drain to Source On Resistance
Ω
I
D = 61A, VGS = 10V,
-
0.035 0.043
TJ = 175oC
Dynamic Characteristics
CISS
Input Capacitance
-
-
-
2880
390
100
41
-
-
pF
pF
pF
nC
nC
nC
nC
nC
VDS = 25V, VGS = 0V,
f = 1MHz
COSS
CRSS
Qg(TOT)
Qg(TH)
Qgs
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge at 10V
Threshold Gate Charge
-
VGS = 0V to 10V
53
6.5
-
VGS = 0V to 2V
-
-
-
-
5
VDD = 50V
ID = 61A
Gate to Source Gate Charge
Gate Charge Threshold to Plateau
Gate to Drain “Miller” Charge
15
Ig = 1.0mA
Qgs2
10
-
Qgd
10
-
Switching Characteristics (VGS = 10V)
tON
td(ON)
tr
Turn-On Time
Turn-On Delay Time
Rise Time
-
-
-
-
-
-
-
146
ns
ns
ns
ns
ns
ns
12
85
26
45
-
-
-
VDD = 50V, ID = 61A
VGS = 10V, RGS = 6.8Ω
td(OFF)
tf
Turn-Off Delay Time
Fall Time
-
-
tOFF
Turn-Off Time
107
Drain-Source Diode Characteristics
I
I
SD = 61A
SD = 30A
-
-
-
-
-
-
-
-
1.25
1.0
62
V
V
VSD
Source to Drain Diode Voltage
trr
Reverse Recovery Time
ISD = 61A, dISD/dt = 100A/µs
ISD = 61A, dISD/dt = 100A/µs
ns
nC
QRR
Reverse Recovered Charge
45
Notes:
1: Starting T = 25°C, L = 0.228mH, I = 40A.
J
AS
2: Pulse Width = 100s
©2003 Fairchild Semiconductor Corporation
FDP3652 / FDB3652 Rev. C0
www.fairchildsemi.com
2
Typical Characteristics T = 25°C unless otherwise noted
C
1.2
75
1.0
0.8
50
0.6
0.4
25
0.2
0
0
150
0
25
50
75
100
175
125
o
25
50
75
100
125
150
175
o
T
, CASE TEMPERATURE ( C)
C
T , CASE TEMPERATURE ( C)
C
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
1
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t /t
1
2
SINGLE PULSE
PEAK T = P x Z
x R
+ T
J
DM
θJC
θJC C
0.01
-5
-4
-3
-2
-1
0
1
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
10
10
10
Figure 3. Normalized Maximum Transient Thermal Impedance
1000
o
T
= 25 C
C
FOR TEMPERATURES
o
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
175 - T
150
C
I = I
25
V
= 10V
GS
100
50
-5
-4
-3
-2
-1
0
1
10
10
10
10
t, PULSE WIDTH (s)
10
10
10
Figure 4. Peak Current Capability
©2003 Fairchild Semiconductor Corporation
FDP3652 / FDB3652 Rev. C0
www.fairchildsemi.com
3
Typical Characteristics T = 25°C unless otherwise noted
C
1000
100
10
500
If R = 0
= (L)(I )/(1.3*RATED BV
If R ¼ 0
t
- V
)
AV
AS
DSS
DD
10µs
t
AV
= (L/R)ln[(I *R)/(1.3*RATED BV
- V ) +1]
DSS DD
AS
100
100µs
o
STARTING T = 25 C
J
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
DS(ON)
10
1ms
1
10ms
o
SINGLE PULSE
STARTING T = 150 C
J
T
T
= MAX RATED
J
o
= 25 C
DC
C
0.1
1
1
10
, DRAIN TO SOURCE VOLTAGE (V)
100
200
0.1
1
10
0.01
V
t
, TIME IN AVALANCHE (ms)
DS
AV
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching
Capability
Figure 5. Forward Bias Safe Operating Area
125
125
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
= 10V
V
= 7V
GS
GS
V
= 15V
DD
100
75
50
25
0
100
75
50
25
0
V
= 6V
GS
o
T
= 175 C
J
o
T
= 25 C
C
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
o
o
T
= 25 C
T
= -55 C
J
J
V
= 5V
GS
3
4
5
6
0
1
V , DRAIN TO SOURCE VOLTAGE (V)
DS
V
, GATE TO SOURCE VOLTAGE (V)
GS
Figure 7. Transfer Characteristics
Figure 8. Saturation Characteristics
20
18
16
14
12
3.0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
2.5
V
= 6V
GS
2.0
1.5
1.0
0.5
0
V
= 10V
GS
V
= 10V, I = 61A
D
GS
0
20
40
60
-80
-40
0
40
80
120
160
200
o
I
, DRAIN CURRENT (A)
T , JUNCTION TEMPERATURE ( C)
D
J
Figure 9. Drain to Source On Resistance vs Drain
Current
Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
©2003 Fairchild Semiconductor Corporation
FDP3652 / FDB3652 Rev. C0
www.fairchildsemi.com
4
Typical Characteristics T = 25°C unless otherwise noted
C
1.4
1.2
1.0
0.8
0.6
0.4
1.2
1.1
1.0
0.9
V
= V , I = 250µA
DS D
I
= 250µA
GS
D
-80
-40
0
40
80
120
160
200
-80
-40
0
40
80
120
160
200
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
Figure 11. Normalized Gate Threshold Voltage vs
Junction Temperature
Figure 12. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
10
5000
V
= 50V
DD
C
= C + C
GS GD
ISS
8
6
4
2
0
C
C
+ C
OSS
DS GD
1000
C
= C
RSS
GD
WAVEFORMS IN
100
40
DESCENDING ORDER:
I
= 61A
= 30A
D
I
D
V
= 0V, f = 1MHz
1
GS
0.1
10
100
0
10
20
30
40
50
V
, DRAIN TO SOURCE VOLTAGE (V)
Q , GATE CHARGE (nC)
g
DS
Figure 13. Capacitance vs Drain to Source
Voltage
Figure 14. Gate Charge Waveforms for Constant
Gate Currents
©2003 Fairchild Semiconductor Corporation
FDP3652 / FDB3652 Rev. C0
www.fairchildsemi.com
5
Test Circuits and Waveforms
V
DS
BV
DSS
t
P
L
V
DS
I
VARY t TO OBTAIN
P
AS
+
-
V
DD
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
0V
AS
0
0.01Ω
t
AV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
V
DS
V
Q
DD
g(TOT)
V
L
DS
V
GS
V
= 10V
GS
V
GS
+
-
Q
gs2
V
DD
DUT
V
= 2V
GS
I
g(REF)
0
Q
g(TH)
Q
Q
gs
gd
I
g(REF)
0
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
V
DS
t
t
ON
OFF
t
d(OFF)
t
d(ON)
R
L
t
t
f
r
V
DS
90%
90%
+
-
V
GS
V
DD
10%
10%
0
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
V
10%
GS
0
Figure 19. Switching Time Test Circuit
Figure 20. Switching Time Waveforms
©2003 Fairchild Semiconductor Corporation
FDP3652 / FDB3652 Rev. C0
www.fairchildsemi.com
6
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in an
80
60
40
20
R
= 26.51+ 19.84/(0.262+Area) EQ.2
θJA
R
= 26.51+ 128/(1.69+Area) EQ.3
θJA
application.
Therefore the application’s ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
(T
– T )
JM
A
-----------------------------
=
(EQ. 1)
P
DM
Rθ JA
In using surface mount devices such as the TO-263
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of PDM is
complex and influenced by many factors:
0.1
(0.645)
1
10
(6.45)
(64.5)
2
2
AREA, TOP COPPER AREA in (cm )
Figure 21. Thermal Resistance vs Mounting
Pad Area
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inches square and equation 3 is for area in centimeter
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.
19.84
(0.262 + Area)
------------------------------------
R
= 26.51 +
(EQ. 2)
θ JA
θ JA
Area in Iches Squared
128
---------------------------------
R
= 26.51 +
(EQ. 3)
(1.69 + Area)
Area in Centimeter Squared
©2003 Fairchild Semiconductor Corporation
FDP3652 / FDB3652 Rev. C0
www.fairchildsemi.com
7
PSPICE Electrical Model
.SUBCKT FDP3652 2 1 3 rev March 2002
Ca 12 8 1.1e-9
Cb 15 14 1.1e-9
Cin 6 8 2.8e-9
LDRAIN
DPLCAP
DRAIN
2
5
10
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
RLDRAIN
RSLC1
51
DBREAK
+
RSLC2
5
ESLC
11
51
Ebreak 11 7 17 18 108.2
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
-
+
50
-
17
DBODY
RDRAIN
6
8
EBREAK 18
-
ESG
EVTHRES
+
16
21
+
-
19
8
MWEAK
Evtemp 20 6 18 22 1
LGATE
EVTEMP
RGATE
GATE
1
6
+
-
18
22
MMED
It 8 17 1
9
20
MSTRO
8
RLGATE
Lgate 1 9 7.16e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 2.29e-9
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RLSOURCE
RLgate 1 9 71.6
RLdrain 2 5 10
RLsource 3 7 22.9
S1A
S2A
RBREAK
12
15
13
14
13
17
18
8
RVTEMP
19
-
S1B
S2B
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
13
CB
CA
IT
14
+
+
VBAT
6
8
5
8
EGS
EDS
+
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 5.7e-3
Rgate 9 20 1.06
-
-
8
22
RVTHRES
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 6.5e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*150),7))}
.MODEL DbodyMOD D (IS=1.5E-11 N=1.06 RS=2.5e-3 TRS1=2.4e-3 TRS2=1.1e-6
+ CJO=1.9e-9 M=5.8e-1 TT=2.5e-8 XTI=3.9)
.MODEL DbreakMOD D (RS=2.7e-1 TRS1=1e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=7e-10 IS=1e-30 N=10 M=0.58)
.MODEL MmedMOD NMOS (VTO=3.6 KP=5.5 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.06)
.MODEL MstroMOD NMOS (VTO=4.3 KP=110 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=3 KP=0.03 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.06e1 RS=.1)
.MODEL RbreakMOD RES (TC1=1.05e-3 TC2=1e-6)
.MODEL RdrainMOD RES (TC1=1.7e-2 TC2=3.2e-5)
.MODEL RSLCMOD RES (TC1=1e-3 TC2=1e-7)
.MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-5.3e-3 TC2=-1.2e-5)
.MODEL RvtempMOD RES (TC1=-3.3e-3 TC2=1.3e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-8 VOFF=-5)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-5 VOFF=-8)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1 VOFF=0.5)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.5 VOFF=-1)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2003 Fairchild Semiconductor Corporation
FDP3652 / FDB3652 Rev. C0
www.fairchildsemi.com
8
SABER Electrical Model
REV March 2002
template FDP3652 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=1.5e-11,nl=1.06,rs=2.5e-3,trs1=2.4e-3,trs2=1.1e-6,cjo=1.9e-9,m=5.8e-1,tt=2.5e-8,xti=3.9)
dp..model dbreakmod = (rs=2.7e-1,trs1=1e-3,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=7e-10,isl=10e-30,nl=10,m=0.58)
m..model mmedmod = (type=_n,vto=3.6,kp=5.5,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=4.3,kp=110,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=3,kp=0.03,is=1e-30, tox=1,rs=.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-8,voff=-5)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-5,voff=-8)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1,voff=0.5)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.5,voff=-1)
c.ca n12 n8 = 1.1e-9
LDRAIN
DPLCAP
DRAIN
2
5
10
RLDRAIN
RSLC1
51
c.cb n15 n14 = 1.1e-9
c.cin n6 n8 = 2.8e-9
RSLC2
ISCL
DBREAK
11
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
50
-
RDRAIN
6
8
ESG
DBODY
EVTHRES
+
16
21
+
-
19
8
spe.ebreak n11 n7 n17 n18 = 108.2
MWEAK
LGATE
EVTEMP
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
RGATE
GATE
1
6
+
-
18
22
EBREAK
+
MMED
9
20
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
MSTRO
8
17
18
-
RLGATE
LSOURCE
CIN
SOURCE
3
7
RSOURCE
i.it n8 n17 = 1
RLSOURCE
S1A
S2A
RBREAK
l.lgate n1 n9 = 7.16e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 2.29e-9
12
15
13
8
14
13
17
18
RVTEMP
19
S1B
S2B
13
CB
CA
res.rlgate n1 n9 = 71.6
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 22.9
IT
14
-
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
22
RVTHRES
res.rbreak n17 n18 = 1, tc1=1.05e-3,tc2=1e-6
res.rdrain n50 n16 = 5.7e-3, tc1=1.7e-2,tc2=3.2e-5
res.rgate n9 n20 = 1.06
res.rslc1 n5 n51 = 1e-6, tc1=1e-3,tc2=1e-7
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 6.5e-3, tc1=1e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-5.3e-3,tc2=-1.2e-5
res.rvtemp n18 n19 = 1, tc1=-3.3e-3,tc2=1.3e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/150))** 7))
}
}
©2003 Fairchild Semiconductor Corporation
FDP3652 / FDB3652 Rev. C0
www.fairchildsemi.com
9
SPICE Thermal Model
JUNCTION
th
REV 23 March 2002
FDP3652
CTHERM1 TH 6 1e-2
CTHERM2 6 5 1.5e-2
CTHERM3 5 4 2e-2
CTHERM4 4 3 2.1e-2
CTHERM5 3 2 2.2e-2
CTHERM6 2 TL 9e-2
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
CTHERM1
6
RTHERM1 TH 6 2.7e-2
RTHERM2 6 5 2.8e-2
RTHERM3 5 4 7.8e-2
RTHERM4 4 3 9e-2
RTHERM5 3 2 2.7e-1
RTHERM6 2 TL 2.87e-1
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
5
SABER Thermal Model
SABER thermal model FDP3652
template thermal_model th tl
thermal_c th, tl
{
4
3
2
ctherm.ctherm1 th 6 =1e-2
ctherm.ctherm2 6 5 =1.5e-2
ctherm.ctherm3 5 4 =2e-2
ctherm.ctherm4 4 3 =2.1e-2
ctherm.ctherm5 3 2 =2.2e-2
ctherm.ctherm6 2 tl =9e-2
rtherm.rtherm1 th 6 =2.7e-2
rtherm.rtherm2 6 5 =2.8e-2
rtherm.rtherm3 5 4 =7.8e-2
rtherm.rtherm4 4 3 =9e-2
rtherm.rtherm5 3 2 =2.7e-1
rtherm.rtherm6 2 tl =2.87e-1
}
tl
CASE
©2003 Fairchild Semiconductor Corporation
FDP3652 / FDB3652 Rev. C0
www.fairchildsemi.com
10
Mechanical Dimensions
TO-220 3L
Figure 22. TO-220, Molded, 3Lead, Jedec Variation AB
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without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specif-
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Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
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Dimension in Millimeters
©2003 Fairchild Semiconductor Corporation
FDP3652 / FDB3652 Rev. C0
www.fairchildsemi.com
11
Mechanical Dimensions
TO-263 2L (D2PAK)
Figure 23. 2LD, TO263, Surface Mount
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specif-
ically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/package/packageDetails.html?id=PN_TT263-002
Dimension in Millimeters
©2003 Fairchild Semiconductor Corporation
FDP3652 / FDB3652 Rev. C0
www.fairchildsemi.com
12
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Rev. I66
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©2003 Fairchild Semiconductor Corporation
FDP3652 / FDB3652 Rev. C0
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