FDS3572 [ONSEMI]
N 沟道，PowerTrench® MOSFET，80V，8.9A，16mΩ;
| 型号： | FDS3572 |
| 厂家： | 
ONSEMI |
| 描述： | N 沟道，PowerTrench® MOSFET，80V，8.9A，16mΩ PC 开关 光电二极管 晶体管 |
| 文件： | 总13页 (文件大小：677K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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November 2003
FDS3572
N-Channel PowerTrench® MOSFET
80V, 8.9A, 16mΩ
Features
Applications
•
•
•
•
•
•
r
= 14mΩ (Typ.), V = 10V, I = 8.9A
•
•
•
Primary switch for Isolated DC/DC converters
DS(ON)
GS
D
Q
= 31nC (Typ.), V = 10V
GS
g(tot)
Distributed Power and Intermediate Bus Architectures
Low Miller Charge
High Voltage Synchronous Rectifier for DC Bus
Converters
Low Q Body Diode
RR
Optimized efficiency at high frequencies
UIS Capability (Single Pulse and Repetitive Pulse)
Formerly developmental type 82663
Branding Dash
5
6
7
8
4
3
2
1
5
1
2
3
4
SO-8
MOSFET Maximum Ratings T = 25°C unless otherwise noted
A
Symbol
Parameter
Ratings
80
Units
V
V
Drain to Source Voltage
Gate to Source Voltage
V
V
DSS
GS
20
Drain Current
o
o
8.9
5.6
A
A
Continuous (T = 25 C, V = 10V, R
= 50 C/W)
A
GS
θJA
I
D
o
o
Continuous (T = 100 C, V = 10V, R
= 50 C/W)
A
GS
θJA
Pulsed
Figure 4
515
A
E
P
Single Pulse Avalanche Energy (Note 1)
Power dissipation
mJ
W
AS
2.5
D
o
o
Derate above 25 C
20
mW/ C
o
T , T
Operating and Storage Temperature
-55 to 150
C
J
STG
Thermal Characteristics
o
R
R
R
Thermal Resistance, Junction to Case (Note 2)
25
50
85
C/W
θJC
θJA
θJA
o
Thermal Resistance, Junction to Ambient at 10 seconds (Note 3)
Thermal Resistance, Junction to Ambient at 1000 seconds (Note 3)
C/W
o
C/W
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
Tape Width
Quantity
2500 units
FDS3572
FDS3572
SO-8
330mm
12mm
©2003 Fairchild Semiconductor Corporation
FDS3572 Rev. A
Electrical Characteristics T = 25°C unless otherwise noted
A
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
B
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I
= 250µA, V = 0V
80
-
-
-
-
-
-
V
VDSS
D
GS
V
V
= 60V
= 0V
1
DS
GS
I
µA
nA
DSS
GSS
o
T = 150 C
-
250
100
A
I
V
= 20V
-
GS
On Characteristics
V
Gate to Source Threshold Voltage
V
= V , I = 250µA
2
-
-
4
V
GS(TH)
GS
DS
D
I
I
I
= 8.9A, V = 10V
0.014 0.016
0.019 0.029
D
D
D
GS
= 5.6A, V = 6V
-
GS
r
Drain to Source On Resistance
Ω
DS(ON)
= 8.9A, V = 10V,
GS
-
0.027 0.032
o
T = 150 C
A
Dynamic Characteristics
C
C
C
Input Capacitance
-
-
-
-
-
-
-
-
1990
320
85
31
4
-
-
pF
pF
pF
nC
nC
nC
nC
nC
ISS
V
= 25V, V = 0V,
GS
DS
Output Capacitance
OSS
RSS
f = 1MHz
Reverse Transfer Capacitance
Total Gate Charge at 10V
Threshold Gate Charge
-
Q
Q
Q
Q
Q
V
= 0V to 10V
= 0V to 2V
41
5.2
-
g(tot)
g(TH)
gs
GS
V
GS
V
= 40V
DD
Gate to Source Gate Charge
Gate Charge Threshold to Plateau
Gate to Drain “Miller” Charge
I
= 8.9A
9
D
I = 1.0mA
g
5
-
gs2
gd
7.5
-
Switching Characteristics (V = 10V)
GS
t
t
t
t
t
t
Turn-On Time
Turn-On Delay Time
Rise Time
-
-
-
-
-
-
-
40
-
ns
ns
ns
ns
ns
ns
ON
13
14
31
13
-
d(ON)
-
V
V
= 40V, I = 8.9A
r
DD
GS
D
= 10V, R = 10Ω
Turn-Off Delay Time
Fall Time
-
GS
d(OFF)
-
f
Turn-Off Time
67
OFF
Drain-Source Diode Characteristics
I
I
I
I
= 8.9A
= 4.3A
-
-
-
-
-
-
-
-
1.25
1.0
50
V
V
SD
SD
SD
SD
V
Source to Drain Diode Voltage
SD
t
Reverse Recovery Time
= 8.9A, dI /dt= 100A/µs
= 8.9A, dI /dt= 100A/µs
ns
nC
rr
SD
Q
Reverse Recovered Charge
70
RR
SD
Notes:
1: Starting T = 25°C, L = 21mH, I = 7A.
J
AS
2: R
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the
drain pins. R
θJA
is guaranteed by design while R
is determined by the user’s board design.
θJC
θJA
2
3: R
is measured with 1.0 in copper on FR-4 board
θJA
©2003 Fairchild Semiconductor Corporation
FDS3572 Rev. A
Typical Characteristics T = 25°C unless otherwise noted
A
1.2
1.0
0.8
0.6
0.4
0.2
0
10
V
= 10V
GS
8
6
4
2
o
R
=50 C/W
θJA
0
0
25
50
75
100
125
150
25
50
75
, AMBIENT TEMPERATURE ( C)
A
100
125
150
o
o
T , AMBIENT TEMPERATURE ( C)
T
A
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs
Ambient Temperature
2
DUTY CYCLE - DESCENDING ORDER
1
0.5
o
R
=50 C/W
0.2
θJA
0.1
0.05
0.02
0.01
0.1
P
DM
t
1
0.01
t
2
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t /t
1
2
PEAK T = P
x Z
x R
+ T
θJA A
J
DM
θJA
0.001
-5
-4
-3
-2
-1
0
1
2
3
10
10
10
10
10
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
1000
o
T
= 25 C
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
A
FOR TEMPERATURES
ABOVE 25 C DERATE PEAK
o
CURRENT AS FOLLOWS:
150 - T
A
I = I
25
V
= 10V
GS
125
100
10
5
-5
-4
-3
-2
-1
0
1
2
3
10
10
10
10
10
t, PULSE WIDTH (s)
10
10
10
10
Figure 4. Peak Current Capability
©2003 Fairchild Semiconductor Corporation
FDS3572 Rev. A
Typical Characteristics T = 25°C unless otherwise noted
A
50
20
15
10
5
If R = 0
= (L)(I )/(1.3*RATED BV
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
t
- V
)
AV
AS
DSS
DD
If R ≠ 0
V
= 15V
DD
t
= (L/R)ln[(I *R)/(1.3*RATED BV
- V ) +1]
DSS DD
AV
AS
o
T
= 150 C
J
10
o
STARTING T = 25 C
J
o
T
= -55 C
o
J
T
= 25 C
J
o
STARTING T = 150 C
J
1
0
3.0
3.5
4.0
4.5
5.0
5.5
0.1
1
10
100
t
, TIME IN AVALANCHE (ms)
V
, GATE TO SOURCE VOLTAGE (V)
AV
GS
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 5. Unclamped Inductive Switching
Capability
Figure 6. Transfer Characteristics
20
20
18
16
14
12
V
= 10V
V
= 6V
V
= 6V
GS
GS
GS
V
= 5V
GS
15
10
5
V
= 4.5V
GS
V
= 10V
GS
o
T
= 25 C
A
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0
0
0.25
0.5
0.75
1.0
0
2
4
6
8
10
V
, DRAIN TO SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
D
DS
Figure 7. Saturation Characteristics
Figure 8. Drain to Source On Resistance vs Drain
Current
2.0
1.5
1.0
0.5
1.2
PULSE DURATION = 80µs
V
= V , I = 250µA
GS
DS
D
DUTY CYCLE = 0.5% MAX
1.1
1.0
0.9
0.8
0.7
0.6
V
= 10V, I = 8.9A
D
GS
-80
-40
0
40
80
120
160
-80
-40
0
40
80
120
o
160
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
Figure 9. Normalized Drain to Source On
Resistance vs Junction Temperature
Figure 10. Normalized Gate Threshold Voltage vs
Junction Temperature
©2003 Fairchild Semiconductor Corporation
FDS3572 Rev. A
Typical Characteristics T = 25°C unless otherwise noted
A
1.2
1.1
1.0
0.9
5000
C
C
= C + C
GS GD
I
= 250µA
ISS
D
1000
≅ C + C
GD
OSS
DS
C
= C
RSS
GD
100
10
V
= 0V, f = 1MHz
GS
-80
-40
0
40
80
120
160
0.1
1
10
, DRAIN TO SOURCE VOLTAGE (V)
DS
80
o
T , JUNCTION TEMPERATURE ( C)
V
J
Figure 11. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
Figure 12. Capacitance vs Drain to Source
Voltage
10
V
= 40V
DD
8
6
4
2
0
WAVEFORMS IN
DESCENDING ORDER:
I
= 8.9A
= 1A
D
I
D
40
0
10
20
Q , GATE CHARGE (nC)
30
g
Figure 13. Gate Charge Waveforms for Constant Gate Currents
©2003 Fairchild Semiconductor Corporation
FDS3572 Rev. A
Test Circuits and Waveforms
V
BV
DSS
DS
t
P
V
DS
L
I
AS
V
DD
VARY t TO OBTAIN
P
+
-
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
0V
AS
0
0.01Ω
t
AV
Figure 14. Unclamped Energy Test Circuit
Figure 15. Unclamped Energy Waveforms
V
DS
V
Q
DD
g(TOT)
V
L
DS
V
GS
V
= 10V
GS
V
GS
+
-
Q
gs2
V
DD
DUT
V
= 2V
GS
I
g(REF)
0
Q
g(TH)
Q
Q
gs
gd
I
g(REF)
0
Figure 16. Gate Charge Test Circuit
Figure 17. Gate Charge Waveforms
V
DS
t
t
ON
OFF
t
d(OFF)
t
d(ON)
R
t
t
f
L
r
V
DS
90%
90%
+
-
V
GS
V
DD
10%
10%
0
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
Figure 18. Switching Time Test Circuit
Figure 19. Switching Time Waveforms
©2003 Fairchild Semiconductor Corporation
FDS3572 Rev. A
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, T , and the
maximum transient thermal impedance curve.
JM
thermal resistance of the heat dissipating path determines
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2. The area, in square inches is the top copper
area including the gate and source pads.
the maximum allowable device power dissipation, P , in an
DM
application.
Therefore the application’s ambient
o
o
temperature, T ( C), and thermal resistance R
must be reviewed to ensure that T
( C/W)
A
θJA
is never exceeded.
JM
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
26
R
= 64 + -------------------------------
(EQ. 2)
θJA
0.23 + Area
(T
– T )
A
JM
(EQ. 1)
P
= ------------------------------
DM
RθJA
The transient thermal impedance (Z ) is also effected by
θJA
varied top copper board area. Figure 22 shows the effect of
copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.
In using surface mount devices such as the SO8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power
dissipation ratings. Precise determination of P
and influenced by many factors:
is complex
DM
Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package.
Therefore, CTHERM1 through CTHERM5 and RTHERM1
through RTHERM5 remain constant for each of the thermal
models. A listing of the model component values is available
in Table 1.
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
200
5. Air flow and board orientation.
R
= 64 + 26/(0.23+Area)
θJA
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
150
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
100
50
defines the R
for the device as a function of the top
θJA
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
0.001
0.01
0.1
1
10
2
AREA, TOP COPPER AREA (in )
Figure 21. Thermal Resistance vs Mounting
Pad Area
150
COPPER BOARD AREA - DESCENDING ORDER
2
0.04 in
2
0.28 in
0.52 in
0.76 in
1.00 in
120
90
60
30
0
2
2
2
-1
0
1
2
3
10
10
10
t, RECTANGULAR PULSE DURATION (s)
10
10
Figure 22. Thermal Impedance vs Mounting Pad Area
©2003 Fairchild Semiconductor Corporation
FDS3572 Rev. A
PSPICE Electrical Model
.SUBCKT FDS3572 2 1 3 ;
rev November 2003
Ca 12 8 7e-10
Cb 15 14 7e-10
Cin 6 8 1.9e-9
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
LDRAIN
DPLCAP
5
DRAIN
2
10
Ebreak 11 7 17 18 86.6
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
RLDRAIN
RSLC1
51
DBREAK
11
+
RSLC2
5
ESLC
51
-
+
50
-
17
DBODY
RDRAIN
6
8
EBREAK 18
-
ESG
It 8 17 1
EVTHRES
+
16
21
+
-
19
8
MWEAK
Lgate 1 9 1e-9
Ldrain 2 5 1e-9
Lsource 3 7 0.1e-9
LGATE
EVTEMP
RGATE
GATE
1
6
+
-
18
22
MMED
9
20
MSTRO
8
RLGATE
RLgate 1 9 10
RLdrain 2 5 10
RLsource 3 7 1
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RLSOURCE
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
S1A
S2A
RBREAK
12
15
13
8
14
13
17
18
RVTEMP
19
S1B
S2B
13
CB
CA
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 5.5e-3
Rgate 9 20 1.3
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 5.5e-3
Rvthres 22 8 Rvthresmod 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
IT
14
-
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
RVTHRES
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*250),2.5))}
.MODEL DbodyMOD D (IS=4.5E-12 RS=4.7e-3 TRS1=1.5e-3 TRS2=2e-5 XTI=3 CJO=1.4e-9 TT=3e-08 M=0.55)
.MODEL DbreakMOD D (RS=2.5 TRS1=1e-4 TRS2=1e-6)
.MODEL DplcapMOD D (CJO=4.6e-10 IS=1e-30 N=10 M=0.5)
.MODEL MmedMOD NMOS (VTO=3.35 KP=3 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.3 T_ABS=25)
.MODEL MstroMOD NMOS (VTO=3.9 KP=60 IS=1e-30 N=10 TOX=1 L=1u W=1u T_ABS=25)
.MODEL MweakMOD NMOS (VTO=2.88 kp=0.04 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=13 RS=0.1 T_ABS=25)
.MODEL RbreakMOD RES (TC1=1e-3 TC2=-7.5e-7)
.MODEL RdrainMOD RES (TC1=4.8e-3 TC2=3e-5)
.MODEL RSLCMOD RES (TC1=2.4e-2 TC2=1e-7)
.MODEL RsourceMOD RES (TC1=1e-2 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-4.4e-3 TC2=-1.4e-5)
.MODEL RvtempMOD RES (TC1=-4e-3 TC2=2e-7)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4.0 VOFF=-2.0)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.0 VOFF=-4.0)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=0)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0 VOFF=-0.5)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2003 Fairchild Semiconductor Corporation
FDS3572 Rev. A
SABER Electrical Model
REV November 2003
template FDS3572 n2,n1,n3 =m_temp
electrical n2,n1,n3
number m_temp=25
{
var i iscl
dp..model dbodymod = (isl=4.5e-12,rs=4.7e-3,trs1=1.5e-3,trs2=2e-5,xti=3,cjo=1.4e-9,tt=3e-08,m=0.55)
dp..model dbreakmod = (rs=2.5,trs1=1e-4,trs2=1e-6)
dp..model dplcapmod = (cjo=4.6e-10,isl=10e-30,nl=10,m=0.5)
m..model mmedmod = (type=_n,vto=3.35,kp=3,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=3.9,kp=60,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=2.88,kp=0.04,is=1e-30, tox=1,rs=0.1)
LDRAIN
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4.0,voff=-2.0)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2.0,voff=-4.0)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.5,voff=0)
DPLCAP
5
DRAIN
2
10
RLDRAIN
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0,voff=-0.5)
c.ca n12 n8 = 7e-10
c.cb n15 n14 = 7e-10
RSLC1
51
RSLC2
ISCL
c.cin n6 n8 = 1.9e-9
DBREAK
11
50
-
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
RDRAIN
6
8
ESG
DBODY
EVTHRES
+
16
21
+
-
19
8
MWEAK
LGATE
EVTEMP
spe.ebreak n11 n7 n17 n18 = 86.6
spe.eds n14 n8 n5 n8 = 1
RGATE
GATE
1
+
6
-
18
22
EBREAK
+
MMED
9
20
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
MSTRO
8
17
18
-
RLGATE
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RLSOURCE
i.it n8 n17 = 1
S1A
S2A
RBREAK
12
15
13
8
14
13
l.lgate n1 n9 = 1e-9
l.ldrain n2 n5 = 1e-9
l.lsource n3 n7 = 0.1e-9
17
18
RVTEMP
19
S1B
S2B
13
CB
CA
IT
14
-
+
+
res.rlgate n1 n9 = 10
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 1
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u, temp=m_temp
RVTHRES
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u, temp=m_temp
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u, temp=m_temp
res.rbreak n17 n18 = 1, tc1=1e-3,tc2=-7.5e-7
res.rdrain n50 n16 = 5.5e-3, tc1=4.8e-3,tc2=3e-5
res.rgate n9 n20 = 1.3
res.rslc1 n5 n51 = 1e-6, tc1=2.4e-2,tc2=1e-7
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 5.5e-3, tc1=1e-2,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-4.4e-3,tc2=-1.4e-5
res.rvtemp n18 n19 = 1, tc1=-4e-3,tc2=2e-7
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/250))** 2.5))
}
}
©2003 Fairchild Semiconductor Corporation
FDS3572 Rev. A
SPICE Thermal Model
JUNCTION
th
REV Nov 2003
FDS3572
Copper Area =1.0 in2
CTHERM1 TH 8 2.0e-3
CTHERM2 8 7 5.0e-3
CTHERM3 7 6 1.0e-2
CTHERM4 6 5 4.0e-2
CTHERM5 5 4 9.0e-2
CTHERM6 4 3 2e-1
CTHERM7 3 2 1
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
RTHERM7
RTHERM8
CTHERM1
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
CTHERM7
CTHERM8
8
7
CTHERM8 2 TL 3
RTHERM1 TH 8 1e-1
RTHERM2 8 7 5e-1
RTHERM3 7 6 1
RTHERM4 6 5 5
RTHERM5 5 4 8
RTHERM6 4 3 12
RTHERM7 3 2 18
RTHERM8 2 TL 25
6
5
SABER Thermal Model
Copper Area = 1.0 in2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 =2.0e-3
ctherm.ctherm2 8 7 =5.0e-3
ctherm.ctherm3 7 6 =1.0e-2
ctherm.ctherm4 6 5 =4.0e-2
ctherm.ctherm5 5 4 =9.0e-2
ctherm.ctherm6 4 3 =2e-1
ctherm.ctherm7 3 2 1
ctherm.ctherm8 2 tl 3
4
3
2
rtherm.rtherm1 th 8 =1e-1
rtherm.rtherm2 8 7 =5e-1
rtherm.rtherm3 7 6 =1
rtherm.rtherm4 6 5 =5
rtherm.rtherm5 5 4 =8
rtherm.rtherm6 4 3 =12
rtherm.rtherm7 3 2 =18
rtherm.rtherm8 2 tl =25
}
tl
CASE
TABLE 1. THERMAL MODELS
2
2
2
2
2
COMPONANT
CTHERM6
CTHERM7
CTHERM8
RTHERM6
RTHERM7
RTHERM8
0.04 in
1.2e-1
0.5
0.28 in
0.52 in
0.76 in
1.0 in
1.5e-1
1.0
2.0e-1
1.0
2.0e-1
1.0
2.0e-1
1.0
3.0
12
1.3
2.8
3.0
3.0
26
20
15
13
39
24
21
19
18
55
38.7
31.3
29.7
25
©2003 Fairchild Semiconductor Corporation
FDS3572 Rev. A
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