FDZ1323NZ [ONSEMI]
共漏极,N 沟道 2.5 V PowerTrench® WL-CSP MOSFET 20V,10A,13mΩ;型号: | FDZ1323NZ |
厂家: | ONSEMI |
描述: | 共漏极,N 沟道 2.5 V PowerTrench® WL-CSP MOSFET 20V,10A,13mΩ |
文件: | 总9页 (文件大小:460K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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September 2014
FDZ1323NZ
Common Drain N-Channel 2.5 V PowerTrench® WL-CSP MOSFET
20 V, 10 A, 13 mΩ
Features
General Description
This device is designed specifically as a single package solution
for Li-Ion battery pack protection circuit and other ultra-portable
applications. It features two common drain N-channel
MOSFETs, which enables bidirectional current flow, on
Max rS1S2(on) = 13 mΩ at VGS = 4.5 V, IS1S2 = 1 A
Max rS1S2(on) = 13 mΩ at VGS = 3.8 V, IS1S2 = 1 A
Max rS1S2(on) = 16 mΩ at VGS = 3.1 V, IS1S2 = 1 A
Max rS1S2(on) = 18 mΩ at VGS = 2.5 V, IS1S2 = 1 A
Occupies only 3 mm2 of PCB area
®
Fairchild’s advanced PowerTrench process with state of the art
“low pitch” WLCSP packaging process, the FDZ1323NZ
minimizes both PCB space and rS1S2(on). This advanced
WLCSP MOSFET embodies a breakthrough in packaging
technology which enables the device to combine excellent
thermal transfer characteristics, ultra-low profile packaging, low
Ultra-thin package: less than 0.35 mm height when mounted
to PCB
gate charge and low rS1S2(on)
.
High power and current handling capability
HBM ESD protection level > 3.6 kV (Note 3)
RoHS Compliant
Applications
Battery management
Load switch
Battery protection
S1
PIN1
PIN1
G1
G2
S1
G1
S2
S1
G2
S2
BOTTOM
TOP
WL-CSP 1.3X2.3
S2
MOSFET Maximum Ratings TA = 25°C unless otherwise noted
Symbol
VS1S2
Parameter
Ratings
Units
Source1 to Source2 Voltage
Gate to Source Voltage
20
V
V
VGS
±12
Source1 to Source2 Current -Continuous TA = 25°C
-Pulsed
(Note 1a)
10
IS1S2
A
40
Power Dissipation
Power Dissipation
TA = 25°C
TA = 25°C
(Note 1a)
(Note 1b)
2
0.5
PD
W
TJ, TSTG
Operating and Storage Junction Temperature Range
-55 to +150
°C
Thermal Characteristics
RθJA
RθJA
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
(Note 1a)
(Note 1b)
62
°C/W
257
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
7 ’’
Tape Width
8 mm
Quantity
5000 units
EC
FDZ1323NZ
WL-CSP 1.3X2.3
1
©2013 Fairchild Semiconductor Corporation
FDZ1323NZ Rev.C7
www.fairchildsemi.com
Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
Zero Gate Voltage Source1 to Source2
Current
IS1S2
IGSS
V
S1S2 = 16 V, VGS = 0 V
1
μA
μA
Gate to Source Leakage Current
VGS = ±12 V, VS1S2 = 0 V
±10
On Characteristics
VGS(th)
rS1S2(on)
gFS
Gate to Source Threshold Voltage
VGS = VS1S2, IS1S2 = 250 μA
0.4
4.5
5.5
7
0.9
9.7
10
11
13
13
9
1.2
13
13
16
18
20
V
mΩ
S
VGS = 4.5 V, IS1S2 = 1 A
V
GS = 3.8 V, IS1S2 = 1 A
Static Source1 to Source2 On Resistance VGS = 3.1 V, IS1S2 = 1 A
VGS = 2.5 V, IS1S2 = 1 A
8
VGS = 4.5 V, IS1S2 = 1 A,TJ = 125 oC
Forward Transconductance
VS1S2 = 5 V, IS1S2 = 1 A
Dynamic Characteristics
Ciss
Coss
Crss
Input Capacitance
1545
269
2055
405
pF
pF
pF
VS1S2 = 10 V, VGS = 0 V,
f = 1 MHz
Output Capacitance
Reverse Transfer Capacitance
252
380
Switching Characteristics
td(on)
tr
td(off)
tf
Turn-On Delay Time
Rise Time
12
13
34
13
17
1.9
5.4
22
23
54
23
24
ns
ns
VS1S2 = 10 V, IS1S2 = 1 A,
V
GS = 4.5 V, RGEN = 6 Ω
Turn-Off Delay Time
Fall Time
ns
ns
Qg
Total Gate Charge
Gate to Source1 Gate Charge
Gate to Source2 “Miller” Charge
nC
nC
nC
VS1S2 = 10 V, IS1S2 = 1 A,
G1S1 = 4.5 V, VG2S2 = 0 V
Qgs
Qgd
V
Source1 to Source2 Diode Characteristics
Ifss
Maximum Continuous Source1 to Source2 Diode Forward Current
1
A
V
Source1 to Source2 Diode Forward
Voltage
VG1S1 = 0 V, VG2S2 = 4.5 V,
fss = 1 A (Note 2)
Vfss
0.6
1.2
I
Notes:
2
1. R
is determined with the device mounted on a 1 in pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
is guaranteed by design while R is determined by
θCA
θJA
θJC
the user's board design.
b. 257 °C/W when mounted on a
minimum pad of 2 oz copper.
a. 62 °C/W when mounted on
a 1 in pad of 2 oz copper.
2
2. Pulse Test: Pulse Width < 300 us, Duty cycle < 2.0%.
3. The diode connected between the gate and source serves only protection against ESD. No gate overvoltage rating is implied.
2
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©2013 Fairchild Semiconductor Corporation
FDZ1323NZ Rev.C7
Typical Characteristics TJ = 25°C unless otherwise noted
40
40
30
20
10
0
VGS = 4.5 V
VGS = 3.8 V
VG1S1 = 4.5 V
VGS = 2.5 V
VG1S1 = 3.8 V
30
VG1S1 = 3.1 V
VGS = 3.1 V
20
VG1S1 = 2.5 V
VGS = 2 V
VG1S1 = 2 V
10
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VG2S2 = 4.5 V
0.4
VS1S2, SOURCE1 TO SOURCE2 VOLTAGE (V)
0
0.0
0.2
0.6
0.0
0.2
0.4
0.6
0.8
1.0
VS1S2, SOURCE1 TO SOURCE2 VOLTAGE (V)
Figure 1. On-Region Characteristics
Figure2. On -Reg io n Ch ara cteri sti cs
2.0
2.0
1.5
1.0
0.5
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VG2S2 = 4.5 V
VGS = 2 V
1.5
1.0
0.5
VGS = 2.5 V
VG1S1 = 2 V
VGS = 3.1 V
VG1S1 = 2.5 V
VGS = 4.5 V
VGS = 3.8 V
VG1S1 = 3.1 V
VG1S1 = 3.8 V
VG1S1 = 4.5 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0
10
20
30
40
0
10
20
30
40
IS1S2, SOURCE1 TO SOURCE2 CURRENT (A)
IS1S2, SOURCE1 TO SOURCE2 CURRENT (A)
Figure 3. Normalized On-Resistance vs Source1
to Source2 Current and Gate Voltage
Figure 4. Normalized On-Resistance vs Source1
to Source2 Current and Gate Voltage
1.6
60
IS1S2 = 1 A
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 4.5 V
1.4
50
40
30
20
10
0
IS1S2 = 1 A
1.2
1.0
0.8
0.6
TJ = 125 o
C
TJ = 25 o
C
-75 -50 -25
0
25 50 75 100 125 150
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
TJ, JUNCTION TEMPERATURE (oC)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 5. Normalized On Resistance
vs Junction Temperature
Figure6. On Resistance vs Gate to
Source Voltage
3
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©2013 Fairchild Semiconductor Corporation
FDZ1323NZ Rev.C7
Typical Characteristics TJ = 25°C unless otherwise noted
40
100
10
1
VG1S1 = 0 V, VG2S2 = 4.5 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
30
VS1S2 = 5 V
TJ = 150 o
C
TJ = 150 o
C
20
10
0
TJ = 25 oC
TJ = 25 o
C
TJ = -55 o
C
TJ = -55 o
C
0.1
0.0
0.5
1.0
1.5
2.0
0.2
0.4
0.6
0.8
1.0
1.2
VGS, GATE TO SOURCE VOLTAGE (V)
Vfss, BODY DIODE FORWARD VOLTAGE (V)
Figure 7. Transfer Characteristics
Figure8. Source1 to Source2 Diode
Forward Voltage vs Source Current
5000
4.5
3.0
1.5
0.0
VG2S2 = 0 V
IS1S2 = 1 A
VS1S2 = 8 V
Ciss
VS1S2 = 10 V
1000
Coss
VS1S2 = 12 V
Crss
f = 1 MHz
= 0 V
V
GS
100
0.1
1
10
20
0
4
8
12
16
20
VS1S2, SOURCE1 TO SOURCE2 VOLTAGE (V)
Q , GATE CHARGE (nC)
g
Figure 9. Gate Charge Characteristics
Figure10. C a p a c i t a n c e v s S o u r c e 1
to Source2 Voltage
10-1
50
10
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
VS1S2 = 0 V
TJ = 125 oC
1 ms
1
0.1
THIS AREA IS
LIMITED BY r
10 ms
DS(on)
SINGLE PULSE
TJ = MAX RATED
100 ms
TJ = 25 o
C
1 s
10 s
DC
R
θJA = 257 oC/W
A = 25 oC
CURVE BENT TO
MEASURED DATA
T
0.01
0.01
0
3
6
9
12
15
0.1
1
10
100
VGS, GATE TO SOURCE VOLTAGE (V)
VS1S2, SOURCE1 TO SOURCE2 VOLTAGE (V)
Figure11. Gate Leakage Current
vs Gate to Source Voltage
Figure 12. Forward Bias Safe
Operating Area
4
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©2013 Fairchild Semiconductor Corporation
FDZ1323NZ Rev.C7
Typical Characteristics TJ = 25°C unless otherwise noted
100
10
SINGLE PULSE
R
θJA = 257 oC/W
A = 25 oC
1
T
0.4
10-3
10-2
10-1
100
101
100
1000
t, PULSE WIDTH (sec)
Figure 13. Single Pulse Maximum Power Dissipation
2
1
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
0.01
0.1
0.01
P
DM
t
1
t
2
NOTES:
DUTY FACTOR: D = t /t
SINGLE PULSE
RθJA = 257 oC/W
1
2
PEAK T = P
J
x Z
x R
+ T
DM
θJA
θJA A
(Note 1b)
0.001
10-4
10-3
10-2
10-1
t, RECTANGULAR PULSE DURATION (sec)
1
10
100
1000
Figure 14. Junction-to-Ambient Transient Thermal Response Curve
5
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©2013 Fairchild Semiconductor Corporation
FDZ1323NZ Rev.C7
Dimensional Outline and Pad Layout
Pin Definations:
Gate
Source1
A1, C1
Source2
A2, C2
B1, B2
Product Specific Dimensions:
D
E
X
Y
2.3 mm
1.3 mm
0.315 mm
0.49 mm
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/package/packageDetails.html?id=PN_UCBEA-006
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©2013 Fairchild Semiconductor Corporation
FDZ1323NZ Rev.C7
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™
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®
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Datasheet contains the design specifications for product development. Specifications
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Not In Production
Rev. I71
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