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April 2013

FIN1049

LVDS Dual-Line Driver with Dual-Line Receiver

Features

Description

.

Greater than 400 Mbps Data Rate

This dual driver-receiver is designed for high-speed

interconnects utilizing Low Voltage Differential

Signaling (LVDS) technology. The driver accepts

LVTTL inputs and translates them to LVDS outputs.

The receiver accepts LVDS inputs and translates them

to LVTTL outputs. The LVDS levels have a typical

differential output swing of 350 mV, which provides for

low EMI at ultra-low power dissipation even at high

frequencies. The FIN1049 can accept LVPECL inputs

for translating from LVPECL to LVDS. The En and Enb

inputs are AND-ed together to enable / disable the

outputs. The enables are common to all four outputs. A

single-line driver and single-line receiver function is

also available in the FIN1019.

3.3 V Power Supply Operation

Low Power Dissipation

Fail-Safe Protection for Open-Circuit Conditions

Meets or Exceeds TIA/EIA-644-A LVDS Standard

16-pin TSSOP Package Saves Space

Flow-Through Pinout Simplifies PCB Layout

Enable/Disable for all Outputs

Industrial Operating Temperature Range:

-40°C to +85°C

Ordering Information

Operating

Temperature Range

Packing

Part Number

Package

Method

16-Lead Thin Shrink Small Outline Package

Tape and Reel

FIN1049MTCX

-40 to +85°C

(TSSOP), JEDEC MO-153, 4.4mm Wide

www.fairchildsemi.com

FIN1049 • Rev. 1.0.3

Pin Configuration

Functional Diagram

Figure 1. Pin Configuration

Figure 2. Functional Diagram

Pin Definitions

Pin #

2, 3

Name

R_IN1+, R_IN2+

R_IN1-, R_IN2-

D_OUT1+, D_OUT2+

D_OUT1-, D_OUT2-

EN, ENb

Description

Non-Inverting LVDS Inputs

Inverting LVDS Inputs

1, 4

7, 6

Non-Inverting Driver Outputs

Inverting Driver Outputs

8, 5

16, 9

15, 14

10, 11

12

Driver Enable Pins for All Outputs

LVTTL Output Pins for R_OUT1and R_OUT2

LVTTL Input Pins for D_IN1and D_IN2

Power Supply (3.3 V)

R_OUT1, R_OUT2

D_IN1, D_IN2

V_CC

13

GND

Ground

Function Table

Inputs

Outputs (LVTTL)

Inputs (LVDS)⁽¹⁾

R_INn+R_INn-

Outputs (LVDS)

EN

H

ENb

R_OUT1

R_OUT2

D_OUTn+

D_OUTn-

L

H

L

ON

Z

ON

Z

ON

Z

ON

Z

H

L

Z

L

Z

Open Current

Fail-Safe Condition

H

L

H

Legend:

H=HIGH Logic Level

L=LOW Logic Level or OPEN

X=Don't Care

Z=High Impedance

Note:

1. Any unused receiver Inputs should be left open.

www.fairchildsemi.com

FIN1049 • Rev. 1.0.3

2

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Symbol

V_CC

Parameter

Min.

-0.5

Max.

+4.6

Unit

V

Supply Voltage

V_IN

LVDS DC Input Voltage

V

V_OUT

I_OSD

T_STG

T_J

LVDS DC Output Voltage

V

Driver Short-Circuit Current (Continuous)

Storage Temperature Range

10

mA

°C

-65

+150

Max Junction Temperature

T_L

Lead Temperature (Soldering, 10 Seconds)

Human Body Model, JESD22-A114

Machine Model, JESD22-A115

+260

7000

250

ESD

V

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol

V_CC

Parameter

Min.

3.0

Max.

3.6

Unit

V

Supply Voltage

|V_ID|

Magnitude of Differential Voltage

Operating Temperature

100

-40

V_CC

mV

°C

T_A

+85

www.fairchildsemi.com

FIN1049 • Rev. 1.0.3

3

DC Electrical Characteristics

Over-supply voltage and operating temperature ranges, unless otherwise specified. All typical values are at T_A=25°C

and with V_CC=3.3 V.

Symbol

Parameter

Conditions

Min. Typ. Max. Units

LVDS Input DC Specifications (R_IN1+, R_IN1-, R_IN2+, R_IN2-) See Figure 3 and Table 1

V_CM=1.2 V, 0.05 V,

2.35 V

V_TH

V_TL

V_IC

Differential Input Threshold HIGH

Differential Input Threshold LOW

Common Mode Voltage Range

0

35

mV

V

-100

V_ID/2

V_CC

(V_ID/2)

-

V_ID=100 mV, V_CC=3.3 V

V_CC=0 V or 3.6 V,

V_IN=0 V or 2.8 V

I_IN

Input Current

±20

mA

CMOS/ LVTTL Input DC Specifications (EN, ENb, D_IN1, D_IN2

)

V_IH

V_IL

Input High Voltage (LVTTL)

2.0

V_CC

0.8

V

Input Low Voltage (LVTTL)

GND

Input Current (EN, ENb, D_IN1, D_IN2, R_INx+

,

I_IN

V_IN=0 V or V_CC

V_IK=-18 mA

±20

µA

V

R_INx-

)

V_IK

Input Clamp Voltage

-1.5

250

-0.7

350

LVDS Output DC Specifications (D_OUT1+, D_OUT1-, D_OUT2+, D_OUT2-

)

V_OD

Output Differential Voltage

V_ODMagnitude Change from

Differential LOW-to-HIGH

Offset Voltage

See Figure 4

R_L=100 

450

35

mV

V_OD

Driver Enabled

See Figure 4

V_OS

1.125 1.250 1.375

25

V

Offset Magnitude Change from Differential

LOW-to-HIGH

mV

V_OS

D_OUT+=0V & D_OUT-=0 V,

Driver Enabled

I_OS

I_OSD

I_OFF

-9

mA

Short-Circuit Output Current

V_OD=0 V, Driver Enabled

V_CC=0 V, V_OUT=0 V or

V_CC

Power-Off Input or Output Current

Disabled Output Leakage Current

±20

Driver Disabled,

D_OUT+=0 V or V_CCor

D_OUT-=0V or V_CC

I_OZD

±10

mA

CMOS/LVTTL Output DC Specifications (R_OUT1, R_OUT2

)

V_OH

V_OL

Output High Voltage

Output Low Voltage

I_OH=-2 mA, V_ID=200 mV

I_OL=2 mA, V_ID=200 mV

2.7

V

0.25

Driver Disabled,

R_OUTn=0 V or V_CC

I_OZ

I_CC

Disabled Output Leakage Current

Power Supply Current⁽²⁾

±10

25

mA

Drivers Enabled, Any

Valid Input Condition

I_CCZ

C_IND

C_OUT

C_INT

Power Supply Current

Input Capacitance

Output Capacitance

Input Capacitance

Drivers Disabled

LVDS Input

10

mA

pF

3.0

4.0

3.5

LVDS Output

LVTTL Input

Note:

2. Both driver and receiver inputs are static. All LVDS outputs have 100  load. None of the outputs have any

lumped capacitive load.

www.fairchildsemi.com

FIN1049 • Rev. 1.0.3

4

AC Electrical Characteristics

Over-supply voltage and operating temperature ranges, unless otherwise specified. All typical values are at T_A=25°C

and with V_CC=3.3 V.

Symbol

Parameter

Conditions

Min. Typ. Max. Units

Switching Characteristics - LVDS Outputs

t_PLHD

t_PHLD

t_TLHD

t_THLD

t_SK(P)

Differential Propagation Delay LOW-to-HIGH See Figure 5, Figure 6

Differential Propagation Delay HIGH-to-LOW

2

ns

Differential Output Rise Time (20% to 80%)

0.2

1.0

0.35

Differential Output Fall Time (80% to 20%)

Pulse Skew |t_PLH- t_PHL

|

t_SK(LH),

t_SK(HL)

Channel-to-Channel Skew⁽³⁾

0.35

ns

t_SK(PP)

t_PZHD

t_PZLD

t_PHZD

t_PLZD

f_MAXD

Part-to-Part Skew⁽⁴⁾

1

6

3

ns

Differential Output Enable Time, Z-to-HIGH

Differential Output Enable Time, A-to-LOW

Differential Output Disable Time, HIGH-to-Z

Differential Output Disable Time, LOW-to-Z

Maximum Frequency⁽⁵⁾

See Figure 7, Figure 8

See Figure 5

ns

200

0.5

MHz

Switching Characteristics - LVTTL Outputs

Measured from 20% to

80% Signal

t_PHL

Propagation Delay HIGH-to-LOW

1.0

3.5

ns

t_PLH

t_SK1

Propagation Delay LOW-to-HIGH

Pulse Skew

V_ID=200 mV

0.5

0

1.0

35

50

3.5

400

500

1

ns

ps

Distributed Load

C_L=15 pF and 50 

R_L=1 k

t_SK2

Channel-to-Channel Skew

Part-to-Part Skew

0

ps

t_SK3

0

ns

t_LHR

Transition Time LOW-to-HIGH

Transition Time HIGH-to-LOW

Disable Time HIGH-to-Z

Disable Time LOW-to-Z

Enable Time Z-to-HIGH

Enable Time Z-to-LOW

Maximum Frequency⁽⁶⁾

V_OS=1.2 V

0.10

2.2

1.3

1.8

0.9

200

0.25

0.18

4.5

1.40

8.0

7.0

ns

t_HLR

See Figure 9, Figure 10

See Figure 11, Figure 12

ns

t_PHZ

ns

t_PLZ

3.5

ns

t_PZH

3.0

ns

t_PZL

1.4

ns

f_MAXT

Notes:

See Figure 9

MHz

3. t_SK(LH), t_SK(HL)is the skew between specified outputs of a single device when the outputs have identical loads and

are switching in the same direction.

4. t_SK(PP)is the magnitude of the difference in propagation delay times between any specified terminals of two

devices switching in the same direction (either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with

the same supply voltage, same temperature, and have identical test circuits.

5. f_MAXDgenerator input conditions: t_r=t_f< 1 ns (10% to 90%), 50% duty cycle, 0 V to 3 V. Output criteria: duty

cycle=45% / 55%, V_OD> 250 mV, all channels switch.

6. f_MAXTgenerator input conditions: t_r=t_f< 1 ns (10% to 90%), 50% duty cycle, V_ID=200 mV, V_CM=1.2 V. Output

criteria: duty cycle=45% / 55%, V_OH> 2.7 V. V_OL< 0.25 V, all channels switching.

www.fairchildsemi.com

FIN1049 • Rev. 1.0.3

5

Required Specifications and Test Diagrams

Notes:

7. Electrostatic Discharge Capability: Human Body Model and Machine Model ESD should be measured using MIL-

STD-883C method 3015.7 standard.

8. Latch-up immunity should be tested to the EIA/JEDEC Standard Number 78 (EIA/JESD78).

Figure 3. Differential Receiver Voltage Definitions Test Circuit

Note:

9. C_L=15 pF, includes all probe and jig capacitances.

Table 1.

Receiver Minimum and Maximum Input Threshold Test Voltages

Resulting Differential

Applied Voltages (V)

Resulting Common

Mode Input Voltage (V)

Input Voltage (mV)

V_IA

1.25

1.15

V_CC

V_IB

1.15

1.25

V_CC- 0.1

V_CC

V_ID

100

V_IC

1.2

-100

100

1.2

V_CC- 0.05

0.05

V_CC- 0.1

0.1

-100

100

0.0

0.1

-100

1100

-1100

1100

-1100

1100

-1100

0.05

1.75

0.65

V_CC

0.65

1.75

V_CC- 1.1

V_CC

1.2

V_CC- 0.55

0.55

V_CC- 1.1

1.1

0.0

1.1

0.55

Figure 4. LVDS Output Circuit for DC Test

Note:

10. R_L=100 

www.fairchildsemi.com

FIN1049 • Rev. 1.0.3

6

Required Specifications and Test Diagrams (Continued)

Figure 5. LVDS Output Propagation Delay and Transition Time Test Circuit

Notes:

11. A: R_L=100 

12. B: Z_O=50  and C_T=15 pF distributed.

Figure 6. LVTTL Input to LVDS Output AC Waveform

www.fairchildsemi.com

FIN1049 • Rev. 1.0.3

7

Required Specifications and Test Diagrams (Continued)

Figure 7. LVDS Output Enable / Disable Delay Test Circuit

Notes:

13. A: R_L=100 

14. B: Z_O=50  and C_T=15 pF distributed.

15. R1=1000 , R_S=950 

16. V_TST=2.4 V.

Figure 8. LVDS Output Enable / Disable Timing Waveforms

www.fairchildsemi.com

FIN1049 • Rev. 1.0.3

8

Required Specifications and Test Diagrams (Continued)

Figure 9. LVTTL Output Propagation Delay and Transition Time Test Circuit

Notes:

17. A: Z_O=50  and C_T=15 pF distributed.

18. R_L=100  and R_S=950 

Figure 10.LVDS Input to LVTTL Output Propagation Delay and Transition Time Waveforms

www.fairchildsemi.com

FIN1049 • Rev. 1.0.3

9

Required Specifications and Test Diagrams (Continued)

Figure 11.LVTTL Output Enable / Disable Test Circuit

Notes:

19. A: Z_O=50  and C_T=15 pF distributed.

20. R_L=100 , R1=1000 , and R_S=950 

Figure 12.LVTTL Output Enable / Disable Timing Waveforms

www.fairchildsemi.com

FIN1049 • Rev. 1.0.3

10

Physical Dimensions

5.00±0.10

4.55

5.90

4.45 7.35

0.65

4.4±0.1

1.45

5.00

0.11

12°

MTC16rev4

Figure 13.16-Lead, Thin-Shrink Small-Outline Package (TSSOP), JEDEC MO-153, 4.4 mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the

warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

www.fairchildsemi.com

FIN1049 • Rev. 1.0.3

11

www.fairchildsemi.com

FIN1049 • Rev. 1.0.3

12

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent

coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.

ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer

application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not

designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification

in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized

application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and

expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such

claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This

literature is subject to all applicable copyright laws and is not for resale in any manner.

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1


型号：	FIN1049MTCX
厂家：	ONSEMI
描述：	带双线路接收器的 LVDS 双线路驱动器驱动驱动器
文件：	总14页 (文件大小：1129K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FIN1049MTCX [ONSEMI]

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