FIN1216MTDX [ONSEMI]
LVDS 21位串并/并串转换器;
| 型号： | FIN1216MTDX |
| 厂家： | 
ONSEMI |
| 描述： | LVDS 21位串并/并串转换器 光电二极管 接口集成电路 转换器 |
| 文件： | 总22页 (文件大小：814K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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September 2009
FIN1215 / FIN1216 / FIN1217/ FIN1218
LVDS 21-Bit Serializers / De-Serializers
Features
Description
The FIN1217 and FIN1215 transform 21-bit wide
parallel LVTTL (Low-Voltage TTL) data into three serial
LVDS (Low-Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in
parallel with the data stream over a separate LVDS link.
Every cycle of transmit clock, 21 bits of input LVTTL
data are sampled and transmitted.
Low Power Consumption
20MHz to 85MHz Shift Clock Support
50% Duty Cycle on the Clock Output of Receiver
±1V Common-mode Range ~1.2V
Narrow Bus Reduces Cable Size and Cost
High Throughput: 1.785Gbps
The FIN1216 and FIN1218 receives and converts the
three serial LVDS data streams back into 21 bits of
LVTTL data. Table 1 provides a matrix summary of the
serializers and de-serializers available. For the
FIN1217, at a transmit clock frequency of 85MHz, 21
bits of LVTTL data are transmitted at a rate of 595Mbps
per LVDS channel.
Up to 595Mbps per Channel
Internal PLL with No External Components
Compatible with TIA/EIA-644 Specification
Offered in 48-lead TSSOP Packages
These chipsets solve EMI and cable size problems
associated with wide and high-speed TTL interfaces.
Ordering Information
Operating
Part Number Temperature
Range
Packing
Eco
Status
Package
Method
FIN1215MTDX
FIN1216MTDX
-40 to + 85°C
RoHS
48-Lead Thin Shrink Small Outline Package (TSSOP) Tape and Reel
FIN1217MTDX
FIN1218MTDX
(Preliminary)
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
© 2003 Fairchild Semiconductor Corporation
FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3
www.fairchildsemi.com
Block Diagrams
Figure 1. FIN1217 / FIN1215 Transmitter Functional Diagram
Figure 2. FIN1218 / FIN1216 Receiver Functional Diagram
Table 1. Serializers / De-Serializers Chip Matrix
CLK
LVTTL
OUT
Part
LVTTL IN
LVDS OUT
LVDS IN
Package
Frequency
FIN1215
FIN1216
FIN1217
FIN1218
66
66
85
85
21
3
48-Lead TSSOP
48-Lead TSSOP
48-Lead TSSOP
48-Lead TSSOP
3
3
21
21
21
3
© 2003 Fairchild Semiconductor Corporation
FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3
www.fairchildsemi.com
2
Transmitters
Pin Configuration
Figure 3. FIN1217 / FIN1215 (21:3 Transmitter)
Description of Signals
Pin Definitions
I/O
# of
Pin Names
Type Pins
TxIn
I
21
1
LVTTL Level Inputs
TxCKLIn
TxOut+
I
LVTTL Level Clock Input; the rising edge is for data strobe
Positive LVDS Differential Data Output
Negative LVDS Differential Data Output
Positive LVDS Differential Clock Output
Negative LVDS Differential Clock Output
O
O
O
O
3
TxOut
3
TxCLKOut+
TxCLKOut-
1
1
LVTTL Level Power-Down Input; assertion (LOW) puts the outputs in high-
impedance state
/PwrDn
I
1
PLL VCC
PLL GND
LVDS VCC
LVDS GND
VCC
I
I
I
I
I
I
1
2
1
3
4
5
Power Supply Pin for LVDS Outputs
Ground Pins for PLL
Power Supply Pins for LVDS Outputs
Ground Pin for LVDS Outputs
Power Supply Pins for LVTTL Inputs
Ground Pins for LVTTL Inputs
No Connect
GND
NC
© 2003 Fairchild Semiconductor Corporation
FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3
www.fairchildsemi.com
3
Receivers
Pin Configuration
Figure 4. FIN1216 / FIN1218 (3:21 Receiver)
Description of Signals
Pin Definitions
I/O
# of
Pin Names
Type Pins
RxIn
I
I
3
3
Negative LVDS Differential Data Output
Positive LVDS Differential Data Output
Negative LVDS Differential Clock Output
Positive LVDS Differential Clock Output
LVTTL Level Data Outputs Goes HIGH for /PwrDn LOW
LVTTL Level Clock Output
RxIn+
RxCLKIn-
RxCLKIn+
RxOut-
I
1
I
1
O
O
21
1
RxCLKOut
LVTTL Level Input; Refer to Transmitter and Receiver Power-up and Power-down
Operation Truth Table
/PwrDn
I
1
PLL VCC
PLL GND
LVDS VCC
LVDS GND
VCC
I
I
I
I
I
I
1
2
1
3
4
5
Power Supply Pin for PLL
Ground Pins for PLL
Power Supply Pins for LVDS Inputs
Ground Pin for LVDS Inputs
Power Supply Pins for LVTTL Outputs
Ground Pins for LVTTL Outputs
No Connect
GND
NC
© 2003 Fairchild Semiconductor Corporation
FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3
www.fairchildsemi.com
4
Truth Tables
Transmitter
Inputs
Outputs
TxIn
TxCLKIn
PwrDn(1)
TxOut±
TxCLKOut±
Active
Active
HIGH
LOW / HIGH
LOW / HIGH
LOW / HIGH
High Impedance
Active
HIGH
LOW / HIGH
Don’t Care(2)
Floating
Floating
Active
Floating
HIGH
HIGH
LOW
LOW
LOW
LOW / HIGH
Don’t Care(2)
Don’t Care
Don’t Care
High Impedance
High Impedance
Notes:
1. The outputs of the transmitter or receiver remain in a high-impedance state until VCC reaches 2V.
2. TxCLKOut± settles at a free running frequency when the part is powered up, PwrDn is HIGH and the TxCLKIn is
a steady logic level LOW / HIGH / high-impedance.
Receiver
Inputs
Outputs
RxIn±
Active
RxCLKIn±
Active
Failsafe Condition(4)
/PwrDn(3)
HIGH
RxOut
RxCLKOut
LOW / HIGH
HIGH
LOW / HIGH
Active
HIGH
Last Valid State
Failsafe Condition(4)
Failsafe Condition(4)
Don’t Care
Active
HIGH
HIGH
LOW / HIGH
HIGH
Failsafe Condition(4)
Don’t Care
HIGH
Last Valid State(5)
LOW
LOW
HIGH
Notes:
3. The outputs of the transmitter or receiver remain in a high-impedance state until VCC reaches 2V.
4. Failsafe condition is defined as the input being terminated and un-driven, shorted, or open.
5. If RxCLKIn± is removed prior to the RxIn± date being removed, RxOut is the last valid state. If RxIn± data is
removed prior to RxCLKIn± being removed, RxOut is HIGH.
© 2003 Fairchild Semiconductor Corporation
FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3
www.fairchildsemi.com
5
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
VCC
Parameter
Min.
-0.3
-0.5
-0.3
Max.
+4.6
Unit
V
Power Supply Voltage
VTTL
VLVDS
IOSD
TTL/CMOS Input/Output Voltage
LVDS Input/Output Voltage
+4.6
V
+4.6
V
LVDS Output Short-Circuit Current
Storage Temperature Range
Continuous
+150
TSTG
TJ
-65
°C
°C
°C
Maximum Junction Temperature, Soldering 4 seconds
Lead Temperature
+150
TL
+260
LVDS I/O to Ground
10.0
6.5
Human Body Model,
JESD22-A114
(1.5kΩ, 100pF)
kV
V
All Pins (FIN1215, FIN1217)
FIN1215, FIN1217 Only
ESD
Machine Model,
JESD22-A115, 0Ω, 200pF
>400
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VCC
Parameter
Min.
3.0
Max.
3.6
Unit
V
Supply Voltage
TA
Operating Temperature
Maximum Supply Noise Voltage(6)
-40
+85
100
°C
VCCNPP
mVPP
Note:
6. 100mV VCC noise should be tested for frequency at least up to 2MHz. All the specifications should be met under
such a noise level.
© 2003 Fairchild Semiconductor Corporation
FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3
www.fairchildsemi.com
6
Transmitter DC Electrical Characteristics
Typical values are at TA=25°C and with VCC=3.3V; minimum and maximum are at over supply voltages and operating
temperatures ranges, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min. Typ. Max. Units
Transmitter LVTTL Input Characteristics
VIH
VIL
VIK
Input High Voltage
Input Low Voltage
Input Clamp Voltage
2.0
VCC
0.8
V
V
V
GND
IIK=-18mA
-0.79 -1.50
VIN=0.4V to 4.6V
VIN=GND
1.8
0
10.0
IIN
Input Current
μA
-10.0
250
Transmitter LVDS Output Characteristics(7)
VOD
ΔVOD
VOS
ΔVOS
IOS
Output Differential Voltage
450
35
mV
mV
V
VOD Magnitude Change from
Differential LOW-to-HIGH
RL=100Ω, Figure 4
Offset Voltage
1.125 1.250 1.375
25
Offset Magnitude Change from
Differential LOW-to-HIGH
mV
mA
μA
Short-Circuit Output Current
VOUT=0V
-3.5
-5.0
DO=0V to 4.6V,
/PwrDn=0V
IOZ
Disabled Output Leakage Current
±1.0
±10.0
Transmitter Supply Current
33MHz
28.0
29.0
34.0
39.0
10.0
46.2
51.7
57.2
62.7
55.0
40MHz
21:3 Transmitter Power Supply Current
RL=100Ω,
Figure 7
ICCWT
mA
for Worst-Case Pattern with Load(8, 9)
65MHz
85MHz(10)
ICCPDT
Powered-Down Supply Current
/PwrDn=0.8V
μA
Notes:
7. Positive current values refer to the current flowing into device and negative values means current flowing out of
pins. Voltages are referenced to ground unless otherwise specified (except ΔVOD and VOD).
8. The power supply current for both transmitter and receiver can be different with the number of active I/O
channels.
9. The 16-grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test
pattern approximates signal switching needed to produce groups of 16 vertical strips across the display.
10. FIN1217 only.
© 2003 Fairchild Semiconductor Corporation
FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3
www.fairchildsemi.com
7
Transmitter AC Electrical Characteristics
Typical values are at over supply voltages and operating temperatures ranges, unless otherwise specified.
Symbol
tTCP
Parameter
Transmit Clock Period
Conditions
Figure 10
Min.
11.76
0.35
Typ.
T
Max.
50.00
0.65
Units
ns
T
tTCH
Transmit Clock (TxCLKIn) HIGH Time
Transmit Clock LOW Time
0.50
0.50
tTCL
0.35
0.65
T
TxCLKIn Transition Time (Rising and
Falling)
10% to 90%
Figure 11
tCLKT
1.0
1.5
6.0
ns
tJIT
tXIT
TxCLKIn Cycle-to-Cycle Jitter
TxIn Transition Time
3.0
6.0
ns
ns
LVDS Transmitter Timing Characteristics
tTLH
tTHL
tSTC
Differential Output Rise Time (20% to 80%)
Differential Output Fall Time (80% to 20%)
TxIn Setup to TxCLNIn
0.75
0.75
1.50
1.50
ns
ns
ns
Figure 8
Figure 10
f=85MHz FIN1217
only
Figure 17(11)
2.5
0
tHTC
TxIn Holds to TCLKIn
ns
ns
tTPDD
Transmitter Power-Down Delay
100
6.8
Transmitter Clock Input to Clock Output
Delay
Figure 13
TA=25°C, VCC=3.3V
tTCCD
2.8
5.5
ns
Transmitter Output Data Jitter (f=40 MHz)(12)
tTPPB0
tTPPB1
tTPPB2
tTPPB3
tTPPB4
tTPPB5
tTPPB6
Transmitter Output Pulse Position of Bit 0
Transmitter Output Pulse Position of Bit 1
Transmitter Output Pulse Position of Bit 2
Transmitter Output Pulse Position of Bit 3
Transmitter Output Pulse Position of Bit 4
Transmitter Output Pulse Position of Bit 5
Transmitter Output Pulse Position of Bit 6
-0.25
0
0.25
ns
ns
ns
ns
ns
ns
ns
a-0.25
a
a+0.25
2a-0.25
3a-0.25
4a-0.25
5a-0.25
6a-0.25
2a
3a
4a
5a
6a
2a+0.25
3a+0.25
4a+0.25
5a+0.25
6a+0.25
Figure 20
1
a =
f ×7
Transmitter Output Data Jitter (f=65 MHz)(12)
tTPPB0
tTPPB1
tTPPB2
Transmitter Output Pulse Position of Bit 0
Transmitter Output Pulse Position of Bit 1
Transmitter Output Pulse Position of Bit 2
-0.2
a-0.2
2a-0.2
0
a
0.2
ns
ns
ns
a+0.2
2a+0.2
2a
Figure 20
1
tTPPB3
Transmitter Output Pulse Position of Bit 3
3a-0.2
3a
3a+0.2
ns
a =
f × 7
tTPPB4
tTPPB5
tTPPB6
Transmitter Output Pulse Position of Bit 4
Transmitter Output Pulse Position of Bit 5
Transmitter Output Pulse Position of Bit 6
4a-0.2
5a-0.2
6a-0.2
4a
5a
6a
4a+0.2
5a+0.2
6a+0.2
ns
ns
ns
Continued on following page…
© 2003 Fairchild Semiconductor Corporation
FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3
www.fairchildsemi.com
8
Transmitter AC Electrical Characteristics (Continued)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Transmitter Output Data Jitter (f=85 MHz, FIN1217 only)(12)
tTPPB0
tTPPB1
tTPPB2
tTPPB3
tTPPB4
tTPPB5
tTPPB6
Transmitter Output Pulse Position of Bit 0
Transmitter Output Pulse Position of Bit 1
Transmitter Output Pulse Position of Bit 2
Transmitter Output Pulse Position of Bit 3
Transmitter Output Pulse Position of Bit 4
Transmitter Output Pulse Position of Bit 5
Transmitter Output Pulse Position of Bit 6
-0.2
0
a
0.2
ns
ns
ns
ns
ns
ns
ns
a-0.2
a+0.2
2a+0.2
3a+0.2
4a+0.2
5a+0.2
6a+0.2
370
2a-0.2
3a-0.2
4a-0.2
5a-0.2
6a-0.2
2a
3a
4a
5a
6a
350
210
Figure 20
1
a =
f × 7
f=40MHz
f=65MHz
Transmitter Clock Out Jitter, Cycle-to cycle
Figure 23
230
tJCC
ps
f=85MHz
FIN1217 only
110
150
tTPLLS
Transmitter Phase Lock Loop Set Time(13)
Figure 15(12)
10.0
ms
Notes:
11. Outputs of all transmitters stay in 3-STATE until power reaches 2V. Clock and data output begins to toggle
10ms after VCC reaches 3V and /PwrDn pin is above 1.5V.
12. This output data pulse position works for both transmitters with 21 TTL inputs, except the LVDS output bit
mapping difference (see Figure 19). Figure 20 shows the skew between the first data bit and clock output. A
two-bit cycle delay is guaranteed when the MSB is output from transmitter.
13. This jitter specification is based on the assumption that PLL has a reference clock with cycle-to-cycle input jitter
of less than 2ns.
© 2003 Fairchild Semiconductor Corporation
FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3
www.fairchildsemi.com
9
Receiver DC Electrical Characteristics
Typical values are at TA=25°C and with VCC=3.3V. Positive current values refer to the current flowing into device and
negative values means current flowing out of pins. Voltages are referenced to ground unless otherwise specified
(except ΔVOD and VOD). Minimum and maximum values are at over supply voltage and operating temperature ranges
unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ.
Max. Units
LVTTL/CMOS DC Characteristics
VIH
VIL
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Clamp Voltage
Input Current
2.0
GND
2.7
VCC
0.8
V
V
VOH
VOL
VIK
IIN
IOH=-0.4mA
3.3
V
IOL=2mA
0.3
-1.5
10
V
IIK=-18mA
V
VIN=0V to 4.6V
-10
μA
Input/Output Power-Off
Leakage Current
VCC=0V, All LVTTL Inputs/Outputs
0V to 4.6V
IOFF
IOS
±10
μA
μA
Output Short-Circuit Current VOUT=0V
-60
-120
Receiver LVDS Input Characteristics
Differential Input Threshold
HIGH
VTH
Figure 6, Table 2
Figure 6, Table 2
100
mV
Differential Input Threshold
LOW
VTL
-100
0.05
mV
V
VICM
IIN
Input Common Mode Range Figure 6, Table 2
VIN=2.4V, VCC=3.6V or 0V
VIN=0V, VCC=3.6V or 0V
2.35
±10.0
±10.0
Input Current
μA
Receiver Supply Current
33MHz
66
74
3:21 Receiver Power Supply
40MHz
56
75
92
ICCWR
Current for Worst Case
Pattern with Load(14)
CL=8pF, Figure 7
mA
65MHz
85MHz(15)
102
125
Powered Down Supply
Current
ICCPDR
/PwrDn=0.8V (RxOut stays LOW)
NA
400
μA
Notes:
14. The power supply current for the receiver can be different due to the number of active I/O channels.
15. 85MHz specification for FIN1218 only.
© 2003 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3
10
Receiver AC Electrical Characteristics
Values are at over supply voltages and operating temperatures, unless otherwise specified.
Symbol
tRCOL
Parameter
RxCLKOut LOW Time
Conditions
Min.
10.0
10.0
6.5
Typ.
11.0
12.2
11.6
11.6
Max. Units
ns
ns
ns
ns
Figure 12
Rising Edge Strobe
f=40MHz
tRCOH
RxCLKOut HIGH Time
tRSRC
RxOut Valid Prior to RxCLKOut
RxOut Valid After RxCLKOut
tRHRC
6.0
Receiver Clock Output (RxCLKOut)
Period
tRCOP
15.0
T
50.0
ns
Figure 12
Rising Edge Strobe
f=65MHz
tRCOL
tRCOH
tRSRC
tRHRC
RxCLKOut LOW Time
5.0
5.0
4.5
4.0
7.8
7.3
7.7
8.4
9.0
9.0
ns
ns
ns
ns
RxCLKOut HIGH Time
RxOut Valid Prior to RxCLKOut
RxOut Valid After RxCLKOut
Receiver Clock Output (RxCLKOut)
Period
tRCOP
11.76
T
50.00
ns
Figure 12
Rising Edge Strobe
f=85MHz
tRCOL
tRCOH
tRSRC
tRHRC
tROLH
tROHL
RxCLKOut LOW Time
4.0
4.5
3.5
3.5
6.3
5.4
6.3
6.5
2.2
2.1
6.0
6.5
ns
ns
ns
ns
ns
ns
RxCLKOut HIGH Time
FIN1218 only
RxOut Valid Prior to RxCLKOut
RxOut Valid After RxCLKOut
Output Rise Time (20% to 80%)
Output Fall Time (80% to 20%)
5.0
5.0
CL=8pF, Figure 9
TA=25°C, VCC=3.3V
Receiver Clock Input to Clock Output
Delay
Figure 14(Error!
tRCCD
3.5
6.9
7.5
ns
Reference source not found.)
tRPDD
tRSPB0
tRSPB1
tRSPB2
tRSPB3
tRSPB4
tRSPB5
tRSPB6
Receiver Power-Down Delay
Figure 18
1.0
ms
ns
ns
ns
ns
ns
ns
ns
Receiver Input Strobe Position of Bit 0
Receiver Input Strobe Position of Bit 1
Receiver Input Strobe Position of Bit 2
Receiver Input Strobe Position of Bit 3
Receiver Input Strobe Position of Bit 4
Receiver Input Strobe Position of Bit 5
Receiver Input Strobe Position of Bit 6
1.00
4.5
2.15
5.8
8.10
11.6
15.1
18.8
22.5
9.15
12.6
16.3
19.9
23.6
Figure 21
f=40MHz
Continued on following page…
© 2003 Fairchild Semiconductor Corporation
FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3
www.fairchildsemi.com
11
Receiver AC Electrical Characteristics (Continued)
Symbol
tRSPB0
tRSPB1
tRSPB2
tRSPB3
tRSPB4
tRSPB5
tRSPB6
tRSPB0
tRSPB1
tRSPB2
tRSPB3
tRSPB4
tRSPB5
tRSPB6
Parameter
Conditions
Min.
0.7
Typ.
Max. Units
Receiver Input Strobe Position of Bit 0
Receiver Input Strobe Position of Bit 1
Receiver Input Strobe Position of Bit 2
Receiver Input Strobe Position of Bit 3
Receiver Input Strobe Position of Bit 4
Receiver Input Strobe Position of Bit 5
Receiver Input Strobe Position of Bit 6
Receiver Input Strobe Position of Bit 0
Receiver Input Strobe Position of Bit 1
Receiver Input Strobe Position of Bit 2
Receiver Input Strobe Position of Bit 3
Receiver Input Strobe Position of Bit 4
Receiver Input Strobe Position of Bit 5
Receiver Input Strobe Position of Bit 6
1.4
3.6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
2.9
5.1
5.8
Figure 21
f=65MHz
7.3
8.0
9.5
10.2
12.4
14.6
1.19
2.87
4.55
6.23
7.91
9.59
11.27
11.7
13.9
0.49
2.17
3.85
5.53
7.21
8.89
10.57
490
400
Figure 21
f=85MHz
FIN1218 only
f=40MHz, Figure 22
f=65MHz, Figure 22
RxIn Skew Margin(Error! Reference source not
tRSKM
found.)
f=85MHz
FIN1218 only
Figure 22
252
tRPLLS
Notes:
16. Total channel latency from serializer to deserializer is (T + tTCCD) + (2•T + tRCCD).
Receiver Phase Lock Loop Set Time
Figure 16
10.0
ms
17. Receiver skew margin is defined as the valid sampling window after considering potential setup/hold time and
minimum/maximum bit position.
© 2003 Fairchild Semiconductor Corporation
FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3
www.fairchildsemi.com
12
Test Circuits
Figure 5. Differential LVDS Output DC Test Circuit
Notes: For all input pulses, tR or tF<=1ns.
CL includes all probe and jig capacitance.
Figure 6. Differential Receiver Voltage Definitions, Propagation Delay, and Transition Time Test Circuit
Table 2.
Receiver Minimum and Maximum Input Threshold Test Voltages
Resulting Differential
Applied Voltages (V)
Resulting Common
Mode Input Voltage (V)
Input Voltage (mV)
VIA
1.25
1.15
2.40
2.30
0.10
0
VIB
1.15
1.25
2.30
2.40
0
VID
100
-100
100
-100
100
-100
600
-600
600
-600
600
-600
VIC
1.20
1.20
2.35
2.35
0.05
0.05
1.20
1.20
2.10
2.10
0.30
0.30
0.10
0.90
1.50
1.80
2.40
0
1.50
0.90
2.40
1.80
0.60
0
0.60
© 2003 Fairchild Semiconductor Corporation
FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3
www.fairchildsemi.com
13
AC Loadings and Waveforms
Note: The worst-case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVTTL/CMOS I/O.
Depending on the valid strobe edge of transmitter, the TxCLKIn can be either rising or failing edge data strobe.
Figure 7. Worst-Case Test Pattern
Figure 8. Transmitter LVDS Output Load and Transition Times
Figure 9. Receiver LVTTL/CMOS Output Load and Transition Times
Figure 10. Transmitter Set-up/Hold and HIGH/LOW Times (Rising Edge Strobe)
Figure 11. Transmitter Input Clock Transition Time
© 2003 Fairchild Semiconductor Corporation
FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3
www.fairchildsemi.com
14
AC Loadings and Waveforms (Continued)
Figure 12. Receiver Set-up/Hold and HIGH/LOW Times
Figure 13. Transmitter Clock-In to Clock-Out Delay (Rising Edge Strobe)
Figure 14. Receiver Clock-In to Clock-Out Delay (Rising Edge Strobe)
Figure 15. Transmitter Phase-Lock-Loop Set Time
© 2003 Fairchild Semiconductor Corporation
FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3
www.fairchildsemi.com
15
AC Loadings and Waveforms (Continued)
Figure 16. Receiver Phase Lock Loop Set Time
Figure 17. Transmitter Power-down Delay
Figure 18. Receiver Power-down Delay
Note: This output date pulse position works for both transmitters with 21 TTL inputs, except the LVDS output bit
mapping difference. Two-bit cycle delay is guaranteed with the MSB is output from transmitter.
Figure 19. Parallel LVTTL Inputs Mapped to Three Serial LVDS Outputs
© 2003 Fairchild Semiconductor Corporation
FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3
www.fairchildsemi.com
16
AC Loadings and Waveforms (Continued)]
Figure 20. Transmitter Output Pulse Bit Position
Figure 21. Receiver Strobe Bit Position
© 2003 Fairchild Semiconductor Corporation
FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3
www.fairchildsemi.com
17
AC Loadings and Waveforms (Continued)
Note: tRSKM is the budget for the cable skew and source clock skew plus Inter-Symbol Interference (ISI).
The minimum and maximum pulse position values are based on the bit position of each of the seven bits within
the LVDS data stream across PVT (Process, Voltage Supply, and Temperature).
Figure 22. Receiver LVDS Input Skew Margin
Note: This jitter pattern is used to test the jitter response (clock out) of the device over the power supply range with
worst jitter ±ns (cycle-to-cycle) clock input. The specific test methodology is as follows:
Switching input data TxIn0 to TxIn20 at 0.5MHz and the input clock is shifted to left -3ns and to
the right +3ns when data is HIGH (by switching between CLK1 and CLK2 in Figure 11).
The ±3ns cycle-to-cycle input jitter is the static phase error between the two clock sources.
Jumping between two clock sources to simulate the worst-case of clock edge jump (3ns) from
graphical controllers. Cycle-to-cycle jitter at TxCLK out pin should be measured cross VCC range
with 100mV noise (VCC noise frequency <2MHz).
Figure 23.
Jitter Pattern
© 2003 Fairchild Semiconductor Corporation
FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3
www.fairchildsemi.com
18
Physical Dimensions
Figure 24. 48-Lead Thin Shrink Small Outline Package (TSSOP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2003 Fairchild Semiconductor Corporation
FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3
www.fairchildsemi.com
19
© 2003 Fairchild Semiconductor Corporation
FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3
www.fairchildsemi.com
20
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