FL7930CMX-G [ONSEMI]
Single-Stage Flyback and Boundary-Mode PFC Controller for Lighting;
| 型号： | FL7930CMX-G |
| 厂家： | 
ONSEMI |
| 描述： | Single-Stage Flyback and Boundary-Mode PFC Controller for Lighting 功率因数校正 |
| 文件： | 总22页 (文件大小：2093K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FL7930C
Single-Stage Flyback and Boundary-Mode PFC
Controller for Lighting
Features
Description
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PFC-Ready Signal
The FL7930C is an active power factor correction (PFC)
controller for boost PFC applications that operate in
critical conduction mode (CRM). It uses a voltage-mode
PWM that compares an internal ramp signal with the
error amplifier output to generate a MOSFET turn-off
signal. Because the voltage-mode CRM PFC controller
does not need rectified AC line voltage information, it
saves the power loss of an input voltage-sensing network
necessary for a current-mode CRM PFC controller.
VIN-Absent Detection
Maximum Switching Frequency Limitation
Internal Soft-Start and Startup without Overshoot
Internal Total Harmonic Distortion (THD) Optimizer
Precise Adjustable Output Over-Voltage Protection
Open-Feedback Protection and Disable Function
Zero-Current Detector (ZCD)
FL7930C provides over-voltage protection (OVP), open-
feedback protection, over-current protection (OCP),
input-voltage-absent detection, and under-voltage
lockout protection (UVLO). The PFC-ready pin can be
used to trigger other power stages when PFC output
voltage reaches the proper level with hysteresis. The
FL7930C can be disabled if the INV pin voltage is lower
than 0.45 V and the operating current decreases to a
very low level. Using a new variable on-time control
method, total harmonic distortion (THD) is lower than in
conventional CRM boost PFC ICs.
150 µs Internal Startup Timer
MOSFET Over-Current Protection (OCP)
Under-Voltage Lockout with 3.5 V Hysteresis
Low Startup and Operating Current
Totem-Pole Output with High State Clamp
+500/-800 mA Peak Gate Drive Current
8-Pin, Small Outline Package (SOP)
Applications
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Ballast
General LED Lighting
Industrial, Commercial, and Residential Fixtures
Outdoor Lighting: Street, Roadway, Parking,
Construction, Ornamental LED Lighting Fixtures
Ordering Information
Operating
Temperature Range
Packing
Part Number
Top Mark
Package
Method
FL7930CMX-G
-40 to +125°C
FL7930CG 8-Lead, Small Outline Package (SOP)
Tape & Reel
© 2013 ON Semiconductor Components Industries, LLC
August-2017 Rev 2
Publication Order Number
FL7930CMX-G/D
Application Diagram
DC OUTPUT
Vcc
FL7930C
line filter
8
5
VCC
Out
7
4
1
ZCD
CS
COMP
3
2
AC INPUT
INV
RDY
GND
6
PFC
ready
Figure 1.
Typical Boost PFC Application
Internal Block Diagram
VCC
H:open
2.5VREF
VREF
8
VCC
VCC
-
VZ
Internal
Bias
VBIAS
reset
+
VTH(S/S)
8.5
12
5
-
ZCD
VCC
+
Restart
Timer
Gate
VTH(ZCD)
7
OUT
Driver
fMAX
limit
VO(MAX)
THD
Optimized
Sawtooth
Generator
S
R
Q
Q
Control Range
Compensation
+
-
40kW
8pF
Overshoot-less
Control
4
6
+
CS
-
1
-
VCS_LIM
INV
VREF
VREF
Stair
Step
GND
+
Clamp
Circuit
reset
VIN Absent
3
COMP
RDY
disable
disable
Thermal
Shutdown
-
0.35 0.45
2.5 2.675
+
2
INV_open
OVP
VBIAS
UVLO
2.051 2.240
Figure 2.
Functional Block Diagram
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Pin Configuration
VCC
OUT GND ZCD
FL7930CG
8-SOP
INV RDY COMP CS
Figure 3. Pin Configuration (Top View)
Pin Definitions
Pin # Name Description
This pin is the inverting input of the error amplifier. The output voltage of the boost PFC converter
should be resistively divided to 2.5 V.
1
2
3
4
INV
RDY
COMP
CS
This pin is used to detect PFC output voltage reaching a pre-determined value. When output
voltage reaches 89% of rated output voltage, this pin is pulled HIGH, which is an (open-drain)
output type.
This pin is the output of the transconductance error amplifier. Components for the output voltage
compensation should be connected between this pin and GND.
This pin is the input of the over-current protection comparator. The MOSFET current is sensed
using a sensing resistor and the resulting voltage is applied to this pin. An internal RC filter is
included to filter switching noise.
This pin is the input of the zero-current detection (ZCD) block. If the voltage of this pin goes
higher than 1.5 V, then goes lower than 1.4 V, the MOSFET is turned on.
5
6
ZCD
GND
This pin is used for the ground potential of all the pins. For proper operation, the signal ground
and the power ground should be separated.
This pin is the gate drive output. The peak sourcing and sinking current levels are +500 mA and
-800 mA, respectively. For proper operation, the stray inductance in the gate driving path must be
minimized.
7
8
OUT
VCC
This is the IC supply pin. IC current and MOSFET drive current are supplied using this pin.
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Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VCC
Parameter
Min.
Max.
VZ
Unit
V
Supply Voltage
IOH, IOL
ICLAMP
IDET
Peak Drive Output Current
-800
-10
+500
+10
+10
VZ
mA
mA
mA
V
Driver Output Clamping Diodes VO>VCC or VO<-0.3 V
Detector Clamping Diodes
RDY Pin(1)
-10
VIN
Error Amplifier Input, Output and ZCD(1)
CS Input Voltage(2)
-0.3
8.0
VIN
V
-10.0
6.0
TJ
TA
Operating Junction Temperature
Operating Temperature Range
Storage Temperature Range
+150
+125
+150
2.5
°C
°C
°C
-40
-65
TSTG
Human Body Model, JESD22-A114
Charged Device Model, JESD22-C101
Electrostatic Discharge
Capability
ESD
kV
2.0
Notes:
1. When this pin is supplied by external power sources by accident, its maximum allowable current is 50 mA.
2. In case of DC input, the acceptable input range is -0.3 V~6 V: within 100 ns -10 V~6 V is acceptable, but
electrical specifications are not guaranteed during such a short time.
Thermal Impedance
Symbol
Parameter
Min.
Max.
Unit
Thermal Resistance, Junction-to-Ambient(3)
150
°C/W
ΘJA
Note:
3. Regarding the test environment and PCB type, please refer to JESD51-2 and JESD51-10.
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Electrical Characteristics
VCC = 14 V and TA = -40°C~+125°C, unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
VCC Section
VSTART
VSTOP
Start Threshold Voltage
Stop Threshold Voltage
UVLO Hysteresis
VCC Increasing
VCC Decreasing
11
7.5
3.0
20
12
8.5
3.5
22
13
9.5
4.0
24
V
V
V
V
V
HYUVLO
VZ
Zener Voltage
ICC=20 mA
VOP
Recommended Operating Range
13
20
Supply Current Section
ISTART Startup Supply Current
IOP Operating Supply Current
VCC=VSTART-0.2 V
120
1.5
190
3.0
µA
mA
mA
µA
Output Not Switching
IDOP
Dynamic Operating Supply Current 50 kHz, CI=1 nF
Operating Current at Disable VINV=0 V
2.5
4.0
IOPDIS
90
160
230
Error Amplifier Section
VREF1
ΔVREF1
ΔVREF2
IEA,BS
IEAS,SR
IEAS,SK
VEAH
Voltage Feedback Input Threshold1 TA=25°C
2.465
2.500
0.1
2.535
10.0
V
mV
mV
µA
µA
µA
V
Line Regulation
VCC=14 V~20 V
Temperature Stability of VREF1(4)
20
Input Bias Current
VINV=1 V~4 V
-0.5
0.5
Output Source Current
Output Sink Current
VINV=VREF -0.1 V
VINV=VREF +0.1 V
VINV=1 V, VCS=0 V
-12
12
Output Upper Clamp Voltage
Zero-Duty Cycle Output Voltage
Transconductance(4)
6.0
0.9
90
6.5
1.0
115
7.0
1.1
VEAZ
V
gm
140
µmho
Maximum On-Time Section
tON,MAX1
tON,MAX2
Maximum On-Time Programming 1 TA=25°C, VZCD=1 V
35.5
11.2
41.5
13.0
47.5
14.8
µs
µs
TA=25°C,
Maximum On-Time Programming 2
IZCD=0.469 mA
Current-Sense Section
Current-Sense Input Threshold
Voltage Limit
VCS
ICS,BS
tCS,D
0.7
0.8
-0.1
350
0.9
1.0
V
Input Bias Current
VCS=0 V~1 V
-1.0
µA
ns
dV/dt=1 V/100 ns,
from 0 V to 5 V
Current-Sense Delay to Output(4)
500
Continued on the following page…
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Electrical Characteristics
VCC = 14 V and TA = -40°C~+125°C, unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ. Max.
Unit
Zero-Current Detect Section
VZCD
Input Voltage Threshold(4)
1.35
0.05
5.5
0
1.50
0.10
6.2
1.65
0.15
7.5
1.00
1.0
-4
V
V
HYZCD Detect Hysteresis(4)
VCLAMPH Input High Clamp Voltage
VCLAMPL Input Low Clamp Voltage
IZCD,BS Input Bias Current
IZCD,SR Source Current Capability(4)
IZCD,SK Sink Current Capability(4)
IDET=3 mA
V
IDET= -3 mA
VZCD=1 V~5 V
TA=25°C
0.65
-0.1
V
-1.0
µA
mA
mA
TA=25°C
10
Maximum Delay From ZCD to Output
dV/dt=-1 V/100 ns, from
5 V to 0 V
tZCD,D
100
9.2
200
ns
Turn-On(4)
Output Section
VOH
VOL
Output Voltage High
Output Voltage Low
Rising Time(4)
IO=-100 mA, TA=25°C
IO=200 mA, TA=25°C
CIN=1 nF
11.0
1.0
50
12.8
2.5
V
V
tRISE
tFALL
100
100
14.5
1
ns
ns
V
Falling Time(4)
CIN=1 nF
50
VO,MAX Maximum Output Voltage
VCC=20 V, IO=100 µA
VCC=5 V, IO=100 µA
11.5
13.0
VO,UVLO Output Voltage with UVLO Activated
V
Restart / Maximum Switching Frequency Limit Section
tRST
fMAX
Restart Timer Delay
Maximum Switching Frequency(4)
50
150
300
300
350
µs
250
kHz
RDY Pin
IRDY,SK Output Sink Current
VRDY,SAT Output Saturation Voltage
IRDY,LK Output Leakage Current
Soft-Start Timer Section
1
2
4
500
1
mA
mV
µA
IRDY,SK=2 mA
320
Output High Impedance
tSS
UVLO Section
Internal Soft-Soft(4)
3
5
7
ms
VRDY
Output Ready Voltage
2.166 2.240 2.314
0.189
V
V
HYRDY Output Ready Hysteresis
Protections
VOVP
OVP Threshold Voltage
TA=25°C
TA=25°C
2.620 2.675 2.730
0.120 0.175 0.230
V
V
HYOVP OVP Hysteresis
VEN
HYEN
TSD
Enable Threshold Voltage
0.40
0.050
125
0.45
0.10
140
60
0.50
0.15
155
V
Enable Hysteresis
V
Thermal Shutdown Temperature(4)
Hysteresis Temperature of TSD(4)
°C
°C
THYS
Note:
4. These parameters, although guaranteed by design, are not production tested.
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Comparison of FL6961 and FL7930C
Function
FL6961
FL7930C
FL7930C Advantages
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No External Circuit for PFC Output UVLO
Reduce Power Loss and BOM Cost Caused by
PFC Out UVLO Circuit
PFC Ready Pin
None
Integrated
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Versatile Open-Drain Pin
Abnormal CCM Operation Prohibited
Frequency Limit
None
None
None
Integrated
Integrated
Abnormal Inductor Current Accumulation Can Be
Prohibited
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Increase System Reliability by Testing for Input
Supply Voltage
VIN-Absent Detection
Guarantee Stable Operation at Short Electric
Power Failure
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Reduce Voltage and Current Stress at Startup
Soft-Start and
Startup without
Overshoot
Integrated
Internal
Eliminate Audible Noise due to Unwanted OVP
Triggering
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No External Resistor Needed
THD Optimizer
TSD
External
None
Stable and Reliable TSD Operation
Converter Temperature Range Limited Range
140°C with 60°C
Hysteresis
Control Range
Compensation
None
Integrated
Comparison of FL7930B and FL7930C
Function
FL7930B
FL7930C
FL7930C Remark
!
If PFC Rated Output Voltage is Assumed 390 V:
VRDY_HIGH Trigger Voltage = 349 V,
VRDY_LOW Trigger Voltage = 320 V
RDY Pin
OVP Pin
None
Integrated
None
Integrated
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Typical Performance Characteristics
Figure 4.
Voltage Feedback Input Threshold 1
(VREF1) vs. TA
Figure 5.
Start Threshold Voltage (VSTART) vs. TA
Figure 6.
Stop Threshold Voltage (VSTOP) vs. TA
Figure 7.
Startup Supply Current (ISTART) vs. TA
Figure 8.
Operating Supply Current (IOP) vs. TA Figure 9.
Output Upper Clamp Voltage (VEAH) vs. TA
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Typical Performance Characteristics
Figure 10. Zero Duty Cycle Output Voltage (VEAZ
vs. TA
)
Figure 11. Maximum On-Time Program 1 (tON,MAX1
vs. TA
)
Figure 12. Maximum On-Time Program 2 (tON,MAX2
vs. TA
)
Figure 13. Current-Sense Input Threshold Voltage
Limit (VCS) vs. TA
Figure 14. Input High Clamp Voltage (VCLAMPH) vs. TA Figure 15. Input Low Clamp Voltage (VCLAMPL) vs. TA
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Typical Performance Characteristics
Figure 16. Output Voltage High (VOH) vs. TA
Figure 17. Output Voltage Low (VOL) vs. TA
Figure 18. Restart Timer Delay (tRST) vs. TA
Figure 19. Output Ready Voltage (VRDY) vs. TA
Figure 20. Output Saturation Voltage (VRDY,SAT
vs. TA
)
Figure 21. OVP Threshold Voltage (VOVP) vs. TA
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Applications Information
PFC
VOUT
1. Startup: Normally, supply voltage (VCC) of a PFC
block is fed from the additional power supply, which can
be called standby power. Without this standby power,
auxiliary winding for zero current detection can be used
as a supply source. Once the supply voltage of the PFC
block exceeds 12 V, internal operation is enabled until
the voltage drops to 8.5 V. If VCC exceeds VZ, 20 mA
+
2.240V/2.051V
2.675V/2.5V
UVLO
OVP
-
-
disable
2.5 2.675
+
-
disable
INV open
0.35 0.45
current is sinking from VCC
.
+
+
0.45V/0.35V
2.5V
PFC Inductor
PFC
PFC
VIN
VOUT
high
INV
-
1
Aux. Winding
2.051 2.240
disable
2
3
FL7930 Rev.00
RDY
COMP
VCC
’
External VCC circuit
when no standby power exists
Figure 23. Circuit Around INV Pin
FL7930 Rev.00
PFC
VOUT
413V
390V
390Vdc
VCC
H:open
VCC
’
2.5VREF
8
VREF
VBIAS
349V
320V
-
VZ
Internal
Bias
reset
+
70V
VTH(S/S)
20mA
55V
8.5
12
VINV
2.50V
2.65V
2.50V
2.24V
2.051V
0.45V
Figure 22. Startup Circuit
0.35V
VCC
15V
2. INV Block: Scaled-down voltage from the output is
the input for the INV pin. Many functions are embedded
based on the INV pin: transconductance amplifier,
output OVP comparator, disable comparator, and output
UVLO comparator.
2.0V
COMP
IOUT
Current sourcing
Current sourcing
Disable
I sinking
For the output voltage control, a transconductance
amplifier is used instead of the conventional voltage
amplifier. The transconductance amplifier (voltage-
controlled current source) aids the implementation of
the OVP and disable functions. The output current of
the amplifier changes according to the voltage
difference of the inverting and non-inverting input of
the amplifier. To cancel down the line input voltage
effect on power factor correction, the effective control
response of the PFC block should be slower than the
line frequency and this conflicts with the transient
response of controller. Two-pole one-zero type
compensation can meet both requirements.
VRDY
OVP
Voltage is decided by pull-up voltage.
Vcc<2V, internal logic is not alive.
- RDY pin is floating, so pull up voltage is shown.
- Internal signals are unknown.
t
Figure 24. Timing Chart for INV Block
3. RDY Output: When the INV voltage is higher than
2.24 V, RDY output is triggered HIGH and lasts until the
INV voltage is lower than 2.051 V. When input AC
voltage is quite high, for example 240 VAC, PFC output
voltage is always higher than RDY threshold, regardless
of boost converter operation. In this case, the INV
voltage is already higher than 2.24 V before PFC VCC
touches VSTART; however, RDY output is not triggered to
HIGH until VCC touches VSTART. After boost converter
operation stops, RDY is not pulled LOW because the
INV voltage is higher than the RDY threshold. When VCC
of the PFC drops below 5 V, RDY is pulled LOW even
though PFC output voltage is higher than threshold. The
RDY pin output is open drain, so needs an external pull-
up resistor to supply the proper power source. The RDY
pin output remains floating until VCC is higher than 2 V.
The OVP comparator shuts down the output drive block
when the voltage of the INV pin is higher than 2.675 V
and there is 0.175 V hysteresis. The disable comparator
disables operation when the voltage of the inverting input
is lower than 0.35 V and there is 100 mV hysteresis. An
external small-signal MOSFET can be used to disable the
IC, as shown in Figure 23. The IC operating current
decreases to reduce power consumption if the IC is
disabled. Figure 24 is the timing chart of the internal
circuit near the INV pin when rated PFC output voltage
is 390 VDC and VCC supply voltage is 15 V.
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VCC
4. Zero-Current Detection: Zero-current detection
(ZCD) generates the turn-on signal of the MOSFET
when the boost inductor current reaches zero using an
auxiliary winding coupled with the inductor. When the
power switch turns on, negative voltage is induced at the
auxiliary winding due to the opposite winding direction
(see Equation 1). Positive voltage is induced (see
Equation 2) when the power switch turns off.
VSTART
VSTOP
PFC operation
5V
VINV(=VPFCOUT
)
2.500V
2.240V
2.051V
T
AUX
V
= −
⋅ V
AC
AUX
(1)
(2)
T
IND
T
VRDY
AUX
V
=
⋅
(V
− V
)
AUX
PFCOUT
AC
T
IND
FL7930C Rev0.0
t
where:
VAUX is the auxiliary winding voltage;
TIND is boost inductor turns;
TIND auxiliary winding turns;
VAC is input voltage for PFC converter; and
VOUT_PFC is output voltage from the PFC converter.
VCC
VSTART
VSTOP
PFC operation
5V
PFC inductor
PFC
VIN
PFC
VOUT
VINV(=VPFCOUT
)
Aux winding
2.500V
2.240V
2.051V
FL7930 Rev.00
VCC
RZCD
Negative Clamp
circuit
VRDY
ZCD
5
-
+
FL7930C Rev0.0
CZCD
restart
timer
VTH(ZCD)
t
Positive Clamp
circuit
optional
Figure 25. Two Cases of RDY Triggered HIGH
gate
driver
fMAX
limit
S
R
Q
Q
THD optimized
saw-tooth
generator
VCC
VSTART
VSTOP
Figure 27. Circuit Near ZCD
PFC operation
5V
Because auxiliary winding voltage can swing from
negative to positive voltage, the internal block in ZCD
pin has both positive and negative voltage clamping
circuits. When the auxiliary voltage is negative, an
internal circuit clamps the negative voltage at the ZCD
pin around 0.65 V by sourcing current to the serial
resistor between the ZCD pin and the auxiliary
winding. When the auxiliary voltage is higher than
6.5 V, current is sinked through a resistor from the
auxiliary winding to the ZCD pin.
VINV(=VPFCOUT
)
2.500V
2.240V
2.051V
VRDY
FL7930C Rev0.0
t
ISW
FL7930 Rev.00
VCC
IDIODE
VACIN
IMOSFET
VSTART
VSTOP
PFC operation
5V
VAUX & VZCD
VAUX
VINV(=VPFCOUT
)
VZCD
2.500V
2.240V
2.051V
6.2V
0.65V
t
VRDY
Figure 28. Auxiliary Voltage Depends on
MOSFET Switching
FL7930C Rev0.0
t
Figure 26. Two Cases of RDY Triggered LOW
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The auxiliary winding voltage is used to check the boost
inductor current zero instance. When boost inductor
current becomes zero, there is a resonance between
boost inductor and all capacitors at the MOSFET drain
pin: including COSS of the MOSFET; an external
capacitor at the D-S pin to reduce the voltage rising and
falling slope of the MOSFET; a parasitic capacitor at
inductor; and so on to improve performance. Resonated
voltage is reflected to the auxiliary winding and can be
used for detecting zero current of boost inductor and
valley position of MOSFET voltage stress. For valley
detection, a minor delay by the resistor and capacitor is
needed. A capacitor increases the noise immunity at the
ZCD pin. If ZCD voltage is higher than 1.5 V, an internal
ZCD comparator output becomes HIGH and LOW when
the ZCD goes below 1.4 V. At the falling edge of
comparator output, internal logic turns on the MOSFET
Figure 30. Restart Timer at Startup
Because the MOSFET turn-on depends on the ZCD
input, switching frequency may increase to higher than
several megahertz due to the mis-triggering or noise on
the nearby ZCD pin. If the switching frequency is higher
than needed for critical conduction mode (CRM),
operation mode shifts to continuous conduction mode
(CCM). In CCM, unlike CRM where the boost inductor
current is reset to zero at the next switch on; inductor
current builds up at every switching cycle and can be
raised to very high current that exceeds the current
rating of the power switch or diode. This can seriously
damage the power switch. To avoid this, maximum
switching frequency limitation is embedded. If ZCD
signal is applied again within 3.3 µs after the previous
rising edge of gate signal, this signal is ignored
internally and FL7930C waits for another ZCD signal.
This slightly degrades the power factor performance at
light load and high input voltage.
VDS
VOUTPFC - VIN
ZCD after COMPARATOR
Ignores ZCD noise
VOUTPFC - VIN
VIN
MOSFET Gate
Max. fSW Limit
Error occurs!
IINDUCTOR
IDIODE
IMOSFET
FL7930 Rev.00
t
Inhibit Region
VZCD
Figure 31. Maximum Switching Frequency
Limit Operation
5. Control: The scaled output is compared with the
internal reference voltage and sinking or sourcing
current is generated from the COMP pin by the
transconductance amplifier. The error amplifier output is
compared with the internal sawtooth waveform to give
proper turn-on time based on the controller.
1.5V
1.4V
MOSFET gate
ON
150ns Delay
ON
PFC
FL7930 Rev.00
VOUT
t
Figure 29. Auxiliary Voltage Threshold
6.2V
When no ZCD signal is available, the PFC controller
cannot turn on the MOSFET, so the controller checks
every switching off time and forces MOSFET turn on
when the off time is longer than 150 µs. This restart
timer triggers MOSFET turn-on at startup and may be
used at the input voltage zero-cross period.
THD-Optimized
Sawtooth
Generator
1V
+
-
MOSFET Off
Sawtooth
INV
1
3
-
VREF
Stair
Step
+
Clamp
Circuit
COMP
VOUT
VIN
R1
C1
C2
FL7930 Rev.00
Figure 32. Control Circuit
VCC
Unlike a conventional voltage-mode PWM controller,
FL7930C turns on the MOSFET at the falling edge of
ZCD signal. The “ON” instant is determined by the
external signal and the turn-on time lasts until the error
amplifier output (VCOMP) and sawtooth waveform meet.
When load is heavy, output voltage decreases, scaled
output decreases, COMP voltage increases to
compensate low output, turn-on time lengthens to give
more inductor turn-on time, and increased inductor
tRESTART
150µs
MOSFET gate
ZCD after COMPARATOR
FL7930 Rev.00
t
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13
current raises the output voltage. This is how a PFC
negative feedback controller regulates output.
ICOMP
Powering
The maximum of VCOMP is limited to 6.5 V, which
dictates the maximum turn-on time. Switching stops
when VCOMP is lower than 1.0 V.
250µmho
ZCD after COMPARATOR
115µmho
VCOMP & Sawtooth
0.155 V / µs
Braking
MOSFET gate
Figure 35. Gain Characteristic
FL7930 Rev.00
t
6. Soft-Start: When VCC reaches VSTART, the internal
reference voltage is increased like a stair step for 5 ms.
As a result, VCOMP is also raised gradually and MOSFET
turn-on time increases smoothly. This reduces voltage
and current stress on the power switch during startup.
Figure 33. Turn-On Time Determination
The roles of PFC controller are regulating output voltage
and input current shaping to increase power factor. Duty
control based on the output voltage should be fast
enough to compensate output voltage dip or overshoot.
For the power factor, however, the control loop must not
react to the fluctuating AC input voltage. These two
VCC
VSTART=12V
requirements conflict; therefore, when designing
a
feedback loop, the feedback loop should be least ten
times slower than AC line frequency. That slow
response is made by C1 at the compensator. R1 makes
gain boost around operation region and C2 attenuates
gain at higher frequency. Boost gain by R1 helps raise
the response time and improves phase margin.
SS
VREF
VREFEND=2.5V
5ms
VINV=0.4V
gM
Gain
Integrator
C1
Proportional
gain
COMP
ISOURCE
COMP
(VREFSS-VINV
)
gM=ISOURCE
R1
Freq.
FL7930 Rev.00
C2
High-Frequency
Noise Filter
COMP
VCOMP
ISOURCE
RCOMP=VCOMP
Figure 34. Compensators Gain Curve
For the transconductance error amplifier side, gain
changes based on differential input. When the error is
large, gain is large to suppress the output dip or peak
quickly. When the error is small, low gain is used to
improve power factor performance.
FL7930 Rev.00
t
Figure 36. Soft-Start Sequence
7. Startup without Overshoot: Feedback control speed
of PFC is quite slow. Due to the slow response, there is
a gap between output voltage and feedback control.
That is why over-voltage protection (OVP) is critical at
the PFC controller and voltage dip caused by fast load
changes from light to heavy is diminished by a bulk
capacitor. OVP is triggered during startup phase.
Operation on and off by OVP at startup may cause
audible noise and can increase voltage stress at startup,
which is normally higher than in normal operation. This
operation is improved when soft-start time is very long.
However, too much startup time enlarges the output
voltage building time at light load. FL7930C has
overshoot protection at startup. During startup, the
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14
IIN
feedback loop is controlled by an internal proportional
gain controller and, when the output voltage reaches the
rated value, it switches to an external compensator after
a transition time of 30 ms. This internal proportional gain
controller eliminates overshoot at startup and an
external conventional compensator takes over
successfully afterward.
IINDUCTOR
VOUT
IDIODE
IMOSFET
Conventional Controller
Startup Overshoot
VZCD
INEGATIVE
Startup Overshoot Control
Control Transition
1.5V
1.4V
150ns
MOSFET gate
VCOMP
ON
ON
Depends on Load
t
FL7930 Rev.00
Figure 38. Input and Output Current Near Input
Voltage Peak
Internal Controller
IIN
t
Figure 37. Startup without Overshoot
IINDUCTOR
8. THD Optimization: Total harmonic distortion
(THD) is the factor that dictates how closely input
current shape matches sinusoidal form. The turn-on
time of the PFC controller is almost constant over one
AC line period due to the extremely low feedback
control response. The turn-off time is determined by the
current decrease slope of the boost inductor made by
the input voltage and output voltage. Once inductor
current becomes zero, resonance between COSS and the
boost inductor makes oscillating waveforms at the drain
pin and auxiliary winding. By checking the auxiliary
winding voltage through the ZCD pin, the controller can
check the zero current of boost inductor. At the same
time, a minor delay is inserted to determine the valley
position of drain voltage. The input and output voltage
difference is at its maximum at the zero cross point of
AC input voltage. The current decrease slope is steep
near the zero cross region and more negative inductor
current flows during a drain voltage valley detection
time. Such a negative inductor current cancels down the
positive current flows and input current becomes zero,
called “zero-cross distortion” in PFC.
VZCD
INEGATIVE
1.5V
1.4V
150ns
MOSFET gate
ON
ON
ON
ON
t
FL7930 Rev.00
Figure 39. Input and Output Current Near Input
Voltage Peak Zero Cross
To improve this, lengthened turn-on time near the zero
cross region is a well-known technique, though the
method may vary and may be proprietary. FL7930C
optimizes this by sourcing current through the ZCD pin.
Auxiliary winding voltage becomes negative when the
MOSFET turns on and is proportional to input voltage.
The negative clamping circuit of ZCD outputs the
current to maintain the ZCD voltage at a fixed value.
The sourcing current from the ZCD is directly
proportional to the input voltage. Some portion of this
current is applied to the internal sawtooth generator,
together with a fixed-current source. Theoretically, the
fixed-current source and the capacitor at sawtooth
generator determine the maximum turn-on time when no
current is sourcing at ZCD clamp circuit and available
turn-on time gets shorter proportional to the ZCD
sourcing current.
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15
operation when it detects AC input is applied again and
applies less voltage and current stress on startup.
VAUX
VOUT
VIN
RZCD
Vcc
THD Optimizer
Though VIN is
eliminated, operation of
controller is normal due
to the large bypass
capacitor.
N
1
VAUX
ZCD
5
Zero-Current
Detect
DMAX
MOSFET gate
VCOMP
fMIN
VREF
IMOT
CMOT
reset
IDS
High drain
current!
Sawtooth Generator
Figure 40. Circuit of THD Optimizer
t
tON is typically constant over 1 AC line frequency,
but tON is changed by ZCD voltage.
Figure 42. Without VIN-Absent Circuit
VZCD
tON
VOUT
VIN
Though VIN is
eliminated, operation of
controller is normal due
to the large bypass
capacitor.
t
tON not shorter
tON get shorter
VZCD at FET on
VAUX
Figure 41. Effect of THD Optimizer
By THD optimizer, turn-on time over one AC line period
is proportionally changed, depending on input voltage.
Near zero cross, lengthened turn-on time improves
THD performance.
DMAX
fMIN
DMIN
MOSFET gate
NewVCOMP
fMIN
9. VIN-Absent Detection: To save power loss
caused by input voltage sensing resistors and to
optimize THD, the FL7930C omits AC input voltage
detection. Therefore, no information about AC input is
available from the internal controller. In many cases, the
VCC of PFC controller is supplied by an independent
power source, like standby power. In this scheme, some
mismatch may exist. For example, when the electric
power is suddenly interrupted during two or three AC
line periods; VCC is still live during that time, but output
voltage drops because there is no input power source.
Consequently, the control loop tries to compensate for
the output voltage drop and VCOMP reaches its
maximum. This lasts until AC input voltage is live again.
When AC input voltage is live again, high VCOMP allows
high switching current and more stress is put on the
MOSFET and diode. To protect against this, FL7930C
checks if the input AC voltage exists. If input does not
exist, soft-start is reset and waits until AC input is live
again. Soft-start manages the turn-on time for smooth
VIN Absence Detected
IDS
Smooth
Soft-Start
t
Figure 43. With VIN-Absent Circuit
10. Current Sense: The MOSFET current is sensed
using an external sensing resistor for over-current
protection. If the CS pin voltage is higher than 0.8 V, the
over-current protection comparator generates
protection signal. An internal RC filter of 40 kΩ and 8 pF
a
is included to filter switching noise.
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16
11. Gate Driver Output: FL7930C contains a single
totem-pole output stage designed for a direct drive of
the power MOSFET. The drive output is capable of up
to +500 / -800 mA peak current with a typical rise and
fall time of 50 ns with 1 nF load. The output voltage is
clamped to 13 V to protect the MOSFET gate even if the
VCC voltage is higher than 13 V.
PCB Layout Guide
PFC block normally handles high switching current and
the voltage low energy signal path can be affected by
the high energy path. Cautious PCB layout is mandatory
for stable operation.
5. A stabilizing capacitor for VCC is recommended as
close as possible to the VCC and ground pins. If it is
difficult, place the SMD capacitor as close to the
corresponding pins as possible.
1. The gate drive path should be as short as possible.
The closed-loop that starts from the gate driver,
MOSFET gate, and MOSFET source to ground of
PFC controller should be as close as possible. This
is also crossing point between power ground and
signal ground. Power ground path from the bridge
diode to the output bulk capacitor should be short
and wide. The sharing position between power
ground and signal ground should be only at one
position to avoid ground loop noise. Signal path of
the PFC controller should be short and wide for
external components to contact.
2. The PFC output voltage sensing resistor is normally
high to reduce current consumption. This path can
be affected by external noise. To reduce noise
potential at the INV pin, a shorter path for output
sensing is recommended. If a shorter path is not
possible, place some dividing resistors between
PFC output and the INV pin — closer to the INV pin
is better. Relative high voltage close to the INV pin
can be helpful.
3. The ZCD path is recommended close to auxiliary
winding from boost inductor and to the ZCD pin. If
that is difficult, place a small capacitor (below
50 pF) to reduce noise.
Figure 44. Recommended PCB Layout
4. The switching current sense path should not share
with another path to avoid interference. Some
additional components may be needed to reduce
the noise level applied to the CS pin.
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17
Typical Application Circuit
Input Voltage
Range
Rated Output
Power
Output Voltage
(Maximum Current)
Application
Device
LED Lighting
FL7930C
90-265 VAC
195 W
390 V (0.5 A)
Features
!
!
!
Average efficiency of 25%, 50%, 75%, and 100% load conditions is higher than 95% at universal input.
Power factor at rated load is higher than 0.98 at universal input.
Total Harmonic Distortion (THD) at rated load is lower than 15% at universal input.
Key Design Notes
!
When auxiliary VCC supply is not available, VCC power can be supplied through Zero Current Detect (ZCD)
winding. The power consumption of R103 is quite high, so its power rating needs checking.
!
Because the input bias current of INV pin is almost zero, output voltage sensing resistors (R112~R115) should
be as high as possible. However, too-high resistance makes the node susceptible to noise. Resistor values need
to strike a balance between power consumption and noise immunity.
!
Quick-charge diode D106 can be eliminated. Without D106, system operation is normal due to the controller’s
highly reliable protection features.
Schematic
Optional
D106
600V 3A
D105
600V 8A
230mH,
49:6
DC OUTPUT
LP101,EER3124N
BD101,
600V,15A
VAUX
R103,
10k,1W
C104,
12nF
R109
47
Q101
FCPF
20N60
D102,
UF4004
FL7930C
D103,1N414
8
R108
4.7
8
7
VCC
ZC
Out
C102,
680nF
5
3
2
4
1
D
CS
Com
p
INV
RD
Y
GND
6
C114 C115
,2.2n ,2.2n
F
F
C101,
220nF
R101,1M-
J
VCC for another power stage
ZNR101
,10D471
Circuit for VCC. If external VCC is used, this circuit is not needed.
Circuit for VCC for another power stage thus components structure and values may vary.
Figure 45. Demonstration Circuit
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18
Transformer
Figure 46. Transformer Schematic Diagram
Winding Specifications
Barrier Tape
Winding
Method
Position
No
Pin (S → F)
Wire
Turns
TOP
BOT
Ts
Np
9, 10 → 7, 8
0.1φ×50
49
Solenoid Winding
1
Bottom
Top
Insulation: Polyester Tape t = 0.025 mm, 3 Layers
NAUX 2 → 4 0.3φ
Insulation: Polyester Tape t = 0.025 mm, 4 Layers
6
Solenoid Winding
Electrical Characteristics
Pin
Specification
230 µH ±7%
Remark
Inductance
9, 10 → 7, 8
100 kHz, 1 V
Core & Bobbin
Core: EER3124, Samhwa (PL-7) (Ae=97.9 mm2)
Bobbin: EER3124
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19
Bill of Materials
Part #
Value
Note
Part #
Value
Note
Resistor
Switch
20 A, 600 V, SuperFET®
Diode
R101
R102
R103
1 MΩ
330 kΩ
10 kΩ
1W
1/2W
1W
Q101
FCPF20N60
D101
D102
1N4746
UF4004
1 W, 18 V, Zener Diode
1 A, 400 V Glass Passivated
High-Efficiency Rectifier
R104
30 kΩ
1/4W
R107
R108
10 kΩ
1/4W
1/4W
D103
D104
1N4148
1N4148
1 A, 100 V Small-Signal Diode
1 A, 100 V Small-Signal Diode
4.7 kΩ
8 A, 600 V, General-Purpose
Rectifier
R109
47 kΩ
1/4W
D105
D106
3 A, 600 V, General-Purpose
Rectifier
R110
R111
10 kΩ
0.80 kΩ
3.9 kΩ
75 kΩ
1/4W
5W
R112,
113, 114
1/4W
1/4W
IC101
FL7930C
CRM PFC Controller
R115
Capacitor
Fuse
NTC
C101
C102
C103
C104
C105
220 nF / 275 VAC
680 nF / 275 VAC
0.68 µF / 630 V
12 nF / 50 V
Box Capacitor
Box Capacitor
Box Capacitor
Ceramic Capacitor
SMD (1206)
FS101
TH101
BD101
5 A / 250 V
5D-15
Bridge Diode
100 nF / 50 V
15 A, 600 V
Electrolytic
Capacitor
C107
33 µF / 50 V
Line Filter
C108
C109
C110
C112
220 nF / 50 V
47 nF / 50 V
1 nF / 50 V
Ceramic Capacitor
Ceramic Capacitor
Ceramic Capacitor
Ceramic Capacitor
LF101
T1
23 mH
Transformer
ZNR
EER3124
Ae=97.9 mm2
47 nF / 50 V
Electrolytic
Capacitor
C111
220 µF / 450 V
ZNR101
10D471
C114
C115
2.2 nF / 450 V
2.2 nF / 450 V
Box Capacitor
Box Capacitor
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20
Physical Dimensions
5.00
4.80
A
0.65
3.81
8
5
B
1.75
6.20
5.80
4.00
3.80
5.60
1
4
PIN ONE
INDICATOR
1.27
1.27
(0.33)
0.25
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
0.25
0.10
0.25
0.19
C
1.75 MAX
0.10
0.51
0.33
OPTION A - BEVEL EDGE
0.50
0.25
x 45°
R0.10
R0.10
GAGE PLANE
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERWISE SPECIFIED
8°
0°
0.90
0.40
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
SEATING PLANE
(1.04)
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08Arev14
DETAIL A
Figure 47. 8-Lead, Small Outline Package (SOP)
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any manner without notice. Please note the revision and/or date on the drawing and contact a ON Semiconductor representative to
verify or obtain the most recent revision. Package specifications do not expand the terms of ON Semiconductor worldwide terms
and conditions, specifically the warranty therein, which covers ON Semiconductor products.
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