FLS6617MX [ONSEMI]
Primary-Side-Regulation PWM with POWER MOSFET;
| 型号： | FLS6617MX |
| 厂家： | 
ONSEMI |
| 描述： | Primary-Side-Regulation PWM with POWER MOSFET 开关 光电二极管 |
| 文件： | 总15页 (文件大小：454K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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May 2016
FLS6617
Primary-Side-Regulation PWM with POWER MOSFET
Integrated
Features
Description
This third-generation Primary Side Regulation (PSR)
and highly integrated PWM controller provides several
features to enhance the performance of low-power
flyback converters. The proprietary TRUECURRENT®
technology of FLS6617 enables precise CC regulation
and simplified circuit design for battery-charger
applications leading to lower-cost, smaller, and lighter
chargers, compared to a conventional design or a linear
transformer.
.
.
.
.
Low Standby Power under 30 mW
High-Voltage Startup
Fewest External Component Counts
Constant-Voltage (CV) and Constant-Current (CC)
Control without Secondary-Feedback Circuitry
.
.
Green-Mode: Linearly Decreasing PWM Frequency
with Cycle Skipping
To minimize standby power consumption, the
proprietary green mode provides off-time modulation to
linearly decrease PWM frequency under light-load
conditions. Green mode assists the power supply in
meeting power conservation requirements.
Fixed PWM Frequency at 50 kHz with Proprietary
Frequency Hopping to Solve EMI Problem
.
.
.
.
.
.
Peak-Current-Mode Control in CV Mode
Cycle-by-Cycle Current Limiting
By using the FLS6617, a charger can be implemented
with few external components and minimized cost. A
typical output CV/CC characteristic envelope is shown
in Figure 1.
VDD Over-Voltage Protection with Auto Restart
VDD Under-Voltage Lockout (UVLO)
Gate Output Maximum Voltage Clamped at 15 V
Fixed Over-Temperature Protection with
Auto Restart
VO
.
Available in the 7-Lead SOP Package
Applications
±7%
.
.
Battery chargers for cellular phones, cordless
phones, PDA, digital cameras, power tools, etc.
Replaces linear transformers and RCC SMPS
IO
Related Resources
Figure 1. Typical Output V-I Characteristic
.
Fairchild Power Supply WebDesigner — Flyback
Design & Simulation - In Minutes at No Expense
Ordering Information
Operating
Temperature Range
Packing
Part Number
Package
Method
FLS6617MX
-40°C to +125°C
7-Lead, Small Outline Package (SOP-7)
Tape & Reel
© 2015 Fairchild Semiconductor Corporation
FLS6617 • Rev. 1.1
www.fairchildsemi.com
Application Diagram
Csn2
Rsn
L1
T1
DF
Rsn2
Csn
DC
Output
D1
D4
Rd
CO1 CO2
RF
Rsn1
Dsn
AC
Input
C1
C2
DFa
R1
R2
CVDD
D2
D3
CVS
VDD
HV
VS
5
8
1
4
2
7
DRAIN
CS
NC
3
GND
RSENSE
FLS6617
Figure 2. Typical Application
Internal Block Diagram
Drain
8
HV
7
Auto
Recovery
OTP
24V
Soft
Driver
PWM
S
R
Q
OSC
VRESET
2
VDD
Max.
Duty
…
0.8V
16V/5V
Pattern
Generator
1
CS
LEB
VRESET
Peak Detect
Vcs,pk
S
EA_I
TS
Slope
Compensation
Tdis
2.5V
4
NC
Constant Current
Regulation
Vsah
Sample and
Hold
EA_V
5
VS
Vsah= Output voltage feedback signal
Constant Voltage
Regulation
2.5V
Figure 3. Functional Block Diagram
© 2015 Fairchild Semiconductor Corporation
FLS6617 • Rev. 1.1
www.fairchildsemi.com
2
Marking Information
F: Fairchild Logo
Z: Plant Code
X: 1-Digit Year Code
Y: 1-Digit Week Code
TT: 2-Digit Die Run Code
T: Package Type (M=SOP)
M: Manufacture Flow Code
ZXYTT
6617
TM
Figure 4. Top Mark
Pin Configuration
CS 1
8
7
DRAIN
HV
VDD
2
3
4
GND
NC
5
VS
Figure 5. Pin Configuration
Pin Definitions
Pin #
Name
Description
Current Sense. This pin connects to current-sense resistor. Detect the MOSFET current for
peak-current-mode control in CV mode and provide the output-current regulation in CC mode.
1
CS
Power Supply. IC operating current and MOSFET driving current are supplied through this pin.
This pin is connected to an external VDD capacitor of typically 10 µF. The threshold voltages for
startup and turn-off are 16 V and 5 V, respectively. The operating current is lower than 5 mA.
2
VDD
Ground
3
4
GND
NC
No Connection
Voltage Sense. This pin detects the output voltage information and discharge time based on
voltage of auxiliary winding.
5
VS
High Voltage. This pin connects to bulk capacitor for high-voltage startup.
7
8
HV
Driver Output. Power MOSFET drain. This pin is the high-voltage power MOSFET drain.
DRAIN
© 2015 Fairchild Semiconductor Corporation
FLS6617 • Rev. 1.1
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Units
VHV
VVDD
VVS
HV Pin Input Voltage
DC Supply Voltage(1,2)
VS Pin Input Voltage
CS Pin Input Voltage
500
30
6.0
6.0
6.0
6.0
700
1
V
V
-0.3
-0.3
-0.3
-0.3
V
VCS
V
VCOMV
VCOMI
VDS
Voltage Error Amplifier Output Voltage
Current Error Amplifier Output Voltage
Drain-Source Voltage
V
V
V
TA=25°C
Continuous Drain Current
TA=100°C
A
ID
0.6
4
A
IDM
EAS
IAR
Pulsed Drain Current
A
Single Pulse Avalanche Energy
Avalanche Current
50
1
mJ
A
Power Dissipation (TA＜50°C)
PD
660
mW
θJA
Thermal Resistance (Junction-to-Air)
Thermal Resistance (Junction-to-Case)
147
11
°C/W
°C/W
ꢀJT
TJ
TSTG
TL
Operating Junction Temperature
-40
-55
+150
+150
+260
°C
°C
°C
Storage Temperature Range
Lead Temperature (Wave Soldering or IR, 10 Seconds)
Electrostatic
Discharge Capability
(Except HV Pin)
Human Body Model, JEDEC-JESD22_A114
Charged Device Model, JEDEC-JESD22_C101
4.0
2.0
ESD
kV
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
2. All voltage values, except differential voltages, are given with respect to the GND pin.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Operating Ambient Temperature
Min.
Max.
Units
TA
-40
+125
°C
© 2015 Fairchild Semiconductor Corporation
FLS6617 • Rev. 1.1
www.fairchildsemi.com
4
Electrical Characteristics
Unless otherwise specified, VDD=15 V and TA=25°C.
Symbol
VDD Section
VOP
Parameter
Condition
Min. Typ. Max. Unit
Continuously Operating Voltage
Turn-On Threshold Voltage
Turn-Off Threshold Voltage
Operating Current
23
17
V
V
VDD-ON
15
16
5.0
2.5
VDD-OFF
IDD-OP
4.5
5.5
5.0
V
mA
IDD-GREEN Green-Mode Operating Supply Current
0.95
24
1.2
mA
V
VDD-OVP
VDD Over-Voltage-Protection Level (OVP)
VDD Over-Voltage-Protection Debounce Time
tD-VDDOVP
90
1
200
350
µs
HV Startup Current Source Section
VHV-MIN
Minimum Startup Voltage on HV Pin(3)
50
V
VAC=90 V (VDC=100 V),
VDD=0 V
IHV
Supply Current Drawn from HV Pin
Leakage Current after Startup
2.0
0.5
5.0
mA
HV=500 V,
VDD=VDD-OFF+1 V
IHV-LC
3.0
µA
Oscillator Section
Center Frequency
44
50
56
Normal Frequency 1
>Vo*0.78
<Vo*0.78
Frequency Hopping
Range
1.6
3.4
36
5.2
fOSC
kHz
Center Frequency
Normal Frequency 2
Frequency Hopping
Range
2.5
50 kHz→36 kHz, Vs
36 kHz→50 kHz, Vs
VF-JUM-53
VF-JUM-35
1.75 1.95 2.15
2.05 2.25 2.45
V
V
Frequency Jumping Point
fOSC-N-MIN Minimum Frequency at No-Load
fOSC-CM-MIN Minimum Frequency at CCM
270
395
13
520
Hz
kHz
COMV Level for High Cycle Skipping Period
VS-F-SKIPH
VS-F-SKIPL
1.14
0.80
V
V
Change(3)
COMV Level for Low Cycle Skipping Period
Change(3)
VS-F-SKIPH<COMV<VN
VS-F-SKIPL>COMV
VDD=10 V, 25 V
240
160
1
ms
ms
%
TSKIP-CV
Cycle skipping period(3)
fDV
fDT
Voltage-Sense Section
Frequency Variation vs. VDD Deviation
2
Frequency Variation vs. Temperature Deviation TA=-40°C to 105°C
15
%
Itc
IC Bias Current
10
µA
V
VBIAS-COMV Adaptive Bias Voltage Dominated by VCOMV
RVS=20 kꢁ
1.4
Continued on the following page…
© 2015 Fairchild Semiconductor Corporation
FLS6617 • Rev. 1.1
www.fairchildsemi.com
5
Electrical Characteristics
Unless otherwise specified, VDD=15 V and TA=25°C.
Symbol
Parameter
Condition
Min. Typ. Max. Unit
Current-Sense Section
tPD
tMIN-N
VTH
Propagation Delay to GATE Output
Minimum On Time at No-Load
90
850
0.8
200
ns
ns
V
700
1050
Threshold Voltage for Current Limit
Voltage Error Amplifier Section
VVR
VN
Reference Voltage
2.475 2.500 2.525
V
V
V
fOSC=Normal
Frequency1 - 2 kHz
Green-Mode Starting Voltage on EA_V
Green-Mode Ending Voltage on EA_V
2.5
0.5
VG
fOSC=1 kHz
Current Error Amplifier Section
VIR Reference Voltage
Internal MOSFET Section(4)
2.475 2.500 2.525
V
DCYMAX
BVDSS
Maximum Duty Cycle
Drain-Source Breakdown Voltage
60
75
85
%
V
ID=250 μA, VGS=0 V
ID=250 μA,
700
900
∆BVDSS/∆TJ Breakdown Voltage Temperature Coefficient Referenced to
TA=25°C
0.53
13
V/°C
RDS(ON)
IS
Static Drain-Source On-Resistance
ID=0.5 A, VGS=10 V
16
1
ꢁ
Maximum Continuous Drain-Source Diode
Forward Current
A
VDS=700 V, TA=25°C
VDS=560 V, TA=100°C
10
100
30
µA
µA
ns
ns
IDSS
Drain-Source Leakage Current
tD-ON
Turn-On Delay Time
Turn-Off Delay Time
10
20
VDS=350 V, ID=1 A,
RG=25 ꢁ(5)
tD-OFF
50
VGS=0 V, VDS=25 V,
fS=1 MHz
CISS
Input Capacitance
Output Capacitance
175
23
200
25
pF
pF
COSS
Over-Temperature-Protection Section
TOTP
Threshold Temperature for OTP(6)
Notes:
3. Guaranteed by design.
+140
°C
4. These parameters, although guaranteed, are not 100% tested in production.
5. Pulse test: pulse width ≦ 300 µs, duty cycle ≦ 2%.
6. When the over-temperature protection is activated, the power system enter auto-restart mode and output is
disabled.
© 2015 Fairchild Semiconductor Corporation
FLS6617 • Rev. 1.1
www.fairchildsemi.com
6
Typical Performance Characteristics
17
5.5
5.3
5.1
4.9
4.7
4.5
16.6
16.2
15.8
15.4
15
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
5
20
35
50
65
80
95 110 125
Temperature(oC)
Temperature(oC)
Figure 6. Turn-on Threshold Voltage(VDD-ON
vs. Temperature
)
Figure 7. Turn-off Threshold Voltage (VDD-OFF
vs. Temperature
)
3
2.8
2.6
2.4
2.2
2
56
54
52
50
48
46
44
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
5
20
35
50
65
80
95 110 125
Temperature(oC)
Temperature(oC)
Figure 8. Operating Current (IDD-OP
vs. Temperature
)
Figure 9. Normal Frequency 1 (fOSC
vs. Temperature
)
2.525
2.515
2.505
2.495
2.485
2.475
1.1
1.05
1
0.95
0.9
0.85
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
5
20
35
50
65
80
95 110 125
Temperature(oC)
Temperature(oC)
Figure 10. Reference Voltage (VVR) vs. Temperature
Figure 11. Green Mode Operating Supply Current
(IDD-GREEN) vs. Temperature
© 2015 Fairchild Semiconductor Corporation
FLS6617 • Rev. 1.1
www.fairchildsemi.com
7
Typical Performance Characteristics
520
15
14.2
13.4
12.6
11.8
11
470
420
370
320
270
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
5
20
35
50
65
80
95 110 125
Temperature(oC)
Temperature(oC)
Figure 12. Minimum Frequency at No Load
(fOSC-N-MIN) vs. Temperature
Figure 13. Minimum Frequency at CCM
(fOSC-CM-MIN) vs. Temperature
4
1000
950
900
850
800
750
3.5
3
2.5
2
1.5
1
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
5
20
35
50
65
80
95 110 125
Temperature(oC)
Temperature(oC)
Figure 14. Supply Current Drawn from HV Pin (IHV
vs. Temperature
)
Figure 15. Minimum On Time at No Load (tMIN-N
vs. Temperature
)
2.8
2.7
2.6
2.5
2.4
2.3
0.8
0.75
0.7
0.65
0.6
0.55
0.5
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
5
20
35
50
65
80
95 110 125
Temperature(oC)
Temperature(oC)
Figure 16. Green Mode Starting Voltage on EA_V
(VN) vs. Temperature
Figure 17. Green Mode Ending Voltage on EA_V (VG)
vs. Temperature
© 2015 Fairchild Semiconductor Corporation
FLS6617 • Rev. 1.1
www.fairchildsemi.com
8
Typical Performance Characteristics
11
3
2.5
2
10.6
10.2
9.8
9.4
9
1.5
1
0.5
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
5
20
35
50
65
80
95 110 125
Temperature(oC)
Temperature(oC)
Figure 18. IC Bias Current (Itc) vs. Temperature
Figure 19. Leakage Current after Startup (IHV-LC
vs. Temperature
)
85
81
77
73
69
65
-40 -25 -10
5
20
35
50
65
80
95 110 125
Temperature(oC)
Figure 20. Maximum Duty Cycle (DCYMAX
vs. Temperature
)
© 2015 Fairchild Semiconductor Corporation
FLS6617 • Rev. 1.1
www.fairchildsemi.com
9
Functional Description
Figure 21 shows the basic circuit diagram of primary-
side regulated flyback converter, with typical waveforms
shown in Figure 22. Generally, Discontinuous
Conduction Mode (DCM) operation is preferred for
primary-side regulation because it allows better output
regulation. The operation principles of DCM flyback
converter are as follows:
constant current regulation mode, VCOMI determines the
duty cycle while VCOMV is saturated to HIGH.
ID
IO
Np:Ns
D
+
+ VF
-
+
L
Lm
During the MOSFET on time (tON), input voltage (VDL) is
applied across the primary-side inductor (Lm). Then
MOSFET current (Ids) increases linearly from zero to the
peak value (Ipk). During this time, the energy is drawn
from the input and stored in the inductor.
VDL
O
VO
-
V
A
D
AC
-
Ids
When the MOSFET is turned off, the energy stored in
the inductor forces the rectifier diode (D) to be turned
on. While the diode is conducting, the output voltage
(Vo), together with diode forward-voltage drop (VF), is
applied across the secondary-side inductor (LmNs2/
EA_I
CS
I
Estimator
O
RCS
VCOMI
Ref
t DIS
Detector
PWM
Control
V
2
S
Np ) and the diode current (ID) decreases linearly from
NA
V
DD
VCOMV
the peak value (IpkNp/Ns) to zero. At the end of inductor
current discharge time (tDIS), all the energy stored in the
inductor has been delivered to the output.
V
O
Estimator
RS1
RS2
+
Vw
-
EA_V
Ref
Primary-Side Regulation
Controller
When the diode current reaches zero, the transformer
auxiliary winding voltage (Vw) begins to oscillate by the
resonance between the primary-side inductor (Lm) and
the effective capacitor loaded across the MOSFET.
Figure 21. Simplified PSR Flyback Converter Circuit
During the inductor current discharge time, the sum of
output voltage and diode forward-voltage drop is
reflected to the auxiliary winding side as (Vo+VF)
Na/Ns. Since the diode forward-voltage drop decreases
as current decreases, the auxiliary winding voltage
reflects the output voltage best at the end of diode
conduction time where the diode current diminishes to
zero. Thus, by sampling the winding voltage at the end
of the diode conduction time, the output voltage
information can be obtained. The internal error amplifier
for output voltage regulation (EA_V) compares the
sampled voltage with internal precise reference to
generate error voltage (VCOMV), which determines the
duty cycle of the MOSFET in CV mode.
Ids (MOSFET Drain-to-Source Current)
Ipk
ID (Diode Current)
NP
I
pk
NS
ID.avg Io
Vw (Auxiliary Winding Voltage)
Meanwhile, the output current can be estimated using
the peak drain current and inductor current discharge
time because output current is same as the average of
the diode current in steady state.
NA
VF
NS
NA
NS
VO
The output current estimator identifies the highest value
of the drain current with a peak detection circuit and
calculates the output current using the inductor
discharge time (tDIS) and switching period (ts). This
output information is compared with an internal precise
reference to generate error voltage (VCOMI), which
determines the duty cycle of the MOSFET in CC Mode.
tON
tDIS
tS
With
Fairchild’s
innovative
TRUECURRENT®
Figure 22. Key Waveforms of DCM Flyback
Converter
technique, constant current (CC) output can be
precisely controlled.
Among the two error voltages, VCOMV and VCOMI, the
smaller one determines the duty cycle. Therefore, during
constant voltage regulation mode, VCOMV determines the
duty cycle while VCOMI is saturated to HIGH. During
© 2015 Fairchild Semiconductor Corporation
FLS6617 • Rev. 1.1
www.fairchildsemi.com
10
Operating Current
VDL
+
Np
The FLS6617 operating current is as small as 2.5 mA,
which results in higher efficiency and reduces the VDD
hold-up capacitance requirement. Once FLS6617 enters
“deep” green mode, the operating current is reduced to
0.95 mA, assisting the power supply in meeting power
conservation requirements.
RSTART
CDL
-
I
startup
AC line
CDD
NA
Green-Mode Operation
1
2
3
4
8
7
CS
Drain
HV
The FLS6617 uses voltage regulation error amplifier
output (VCOMV) as an indicator of the output load and
modulates the PWM frequency as shown in Figure 23.
The switching frequency decreases with cycle skipping
as the load decreases. In heavy load conditions, the
switching frequency is fixed at 50 kHz. Once VCOMV
decreases below VN, the PWM frequency linearly
decreases with cycle skipping from 50 kHz to reduce
switching losses.
VDD
GND
NC
RCS
RS1
5
VS
Cvs
RS2
Figure 24. HV Startup Circuit
Switching Frequency
with cycle skipping
Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally at
16 V and 5 V, respectively. During startup, the hold-up
capacitor must be charged to 16 V through the startup
resistor to enable the FLS6617. The hold-up capacitor
continues to supply VDD until power can be delivered
from the auxiliary winding of the main transformer. VDD
is not allowed to drop below 5 V during this startup
process. This UVLO hysteresis window ensures that
hold-up capacitor properly supplies VDD during startup.
fOSC
Green Mode
Normal Mode
395 Hz
Protections
VG
VN
The FLS6617 has several self-protection functions, such
as Over-Voltage Protection (OVP), Over-Temperature
Protection (OTP), and pulse-by-pulse current limit. All
the protections are implemented as auto-restart mode.
Once the abnormal condition occurs, the switching is
terminated and the MOSFET remains off, causing VDD
to drop. When VDD drops to the VDD turn-off voltage of
5 V, internal startup circuit is enabled again and the
supply current drawn from the HV pin charges the hold-
up capacitor. When VDD reaches the turn-on voltage of
16 V, normal operation resumes. In this manner, the
auto-restart alternately enables and disables the
switching of the MOSFET until the abnormal condition is
eliminated (see Figure 25).
VCOMV
VS-F-SKIPL
VS-F-SKIPH
Figure 23. Switching Frequency in Green Mode
Frequency Hopping
EMI reduction is accomplished by frequency hopping,
which spreads the energy over a wider frequency range
than the bandwidth measured by the EMI test
equipment. FLS6617 has
frequency hopping circuit that changes the switching
frequency between 44 kHz and 56 kHz.
a
proprietary internal
High-Voltage Startup
Figure 24 shows the HV-startup circuit for FLS6617
applications. The HV pin is connected to the line input or
bulk capacitor through
a resistor, RSTART (100 kꢁ
recommended). During startup status, the internal
startup circuit is enabled. Meanwhile, line input supplies
the current, ISTARTUP, to charge the hold-up capacitor,
CDD, through RSTART. When the VDD voltage reaches VDD-
ON, the internal startup circuit is disabled, blocking
ISTARTUP from flowing into the HV pin. Once the IC turns
on, CDD is the only energy source to supply the IC
consumption current before the PWM starts to switch.
Thus, CDD must be large enough to prevent VDD from
dropping down to VDD-OFF before the power can be
delivered from the auxiliary winding.
© 2015 Fairchild Semiconductor Corporation
FLS6617 • Rev. 1.1
www.fairchildsemi.com
11
Built-In Slope Compensation
Error occurs
Power
on
The sensed voltage across the current-sense resistor is
used for current mode control and pulse-by-pulse
current limiting. Built-in slope compensation improves
stability and prevents sub-harmonic oscillations due to
VDS
Error removed
peak-current mode control. The FLS6617 has
a
synchronized, positive-slope ramp built-in at each
switching cycle.
VDD
16V
Noise Immunity
Noise from the current sense or the control signal can
cause significant pulse width jitter, particularly in
continuous-conduction
mode.
While
slope
5V
compensation helps alleviate these problems, further
precautions should still be taken. Good placement and
layout practices should be followed. Avoiding long PCB
traces and component leads, locating compensation
and filter components near the FLS6617, and increasing
the power MOS gate resistance are advised.
Operating Current
2.5mA
normal
operation
abnormal
situation
normal
operation
Operation Area
Figure 25. Auto-Restart Operation
Figure 26 shows operation area. FLS6617 has two
switching frequency (fs) in constant current mode. In
order to ensure IC can normally work at DCM under
constant current mode, frequency will jump to lower
level(36 kHz) when system is operated at low output
voltage.
VDD Over-Voltage Protection (OVP)
VDD over-voltage protection prevents damage from over-
voltage conditions. If the VDD voltage exceeds 24 V at
open-loop feedback condition, OVP is triggered and the
PWM switching is disabled. The OVP has a debounce
time (typically 200 µs) to prevent false triggering due to
switching noises.
VOUT
Over-Temperature Protection (OTP)
The built-in temperature-sensing circuit shuts down
PWM output if the junction temperature exceeds 140°C.
CV region
50kHz
Pulse-by-pulse Current Limit
CC region
When the sensing voltage across the current-sense
resistor exceeds the internal threshold of 0.8 V, the
MOSFET is turned off for the remainder of switching
cycle. In normal operation, the pulse-by-pulse current
limit is not triggered since the peak current is limited by
the control loop.
36kHz
Leading-Edge Blanking (LEB)
IOUT
Each time the power MOSFET switches on, a turn-on
spike occurs at the sense resistor. To avoid premature
termination of the switching pulse, a leading-edge
blanking time is built in. During this blanking period,
the current-limit comparator is disabled and cannot
switch off the gate driver. As a result conventional RC
filtering can be omitted.
Figure 26. Operation Area
Gate Output
The FLS6617 output stage is a fast totem-pole gate
driver. Cross conduction has been avoided to minimize
heat dissipation, increase efficiency, and enhance
reliability. The output driver is clamped by an internal
15 V Zener diode to protect the power MOSFET
transistors against undesired over-voltage gate signals.
© 2015 Fairchild Semiconductor Corporation
FLS6617 • Rev. 1.1
www.fairchildsemi.com
12
5.00
4.80
A
3.81
B
5
7 6
1.75 TYP
1.27
3.81
4.00
3.80
6.20
5.80
3.85 7.35
1 2
3
4
PIN #1
1.27
0.25
0.65 TYP
(0.33)
M
C
B A
TOP VIEW
LAND PATTERN RECOMMENDATION
B
0.25
0.19
C
1.75 MAX
0.10
C
0.51
0.33
OPTION A
BEVEL EDGE
OPTION B
NO BEVEL EDGE
0.25
0.10
FRONT VIEW
SIDE VIEW
NOTES:
A. THIS PACKAGE DOES NOT FULLY CONFORM
TO JEDEC MS-012, VARIATION AA
B. ALL DIMENSIONS ARE IN MILLIMETERS
C. DIMENSIONS DO NOT INCLUDE MOLD FLASH
OR BURRS
0.50
0.25
x 45
R0.10
R0.10
GAGE PLANE
0.36
D. DRAWING FILENAME: MKT-M07Brev4
8°
0°
0.900
0.406
SEATING PLANE
(1.04)
DETAIL B
SCALE 2:1
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