FMS6346MTC20X [ONSEMI]

视频滤波器驱动器,六沟道,6 阶 SD HD;
FMS6346MTC20X
型号: FMS6346MTC20X
厂家: ONSEMI    ONSEMI
描述:

视频滤波器驱动器,六沟道,6 阶 SD HD

驱动 光电二极管 商用集成电路 驱动器
文件: 总12页 (文件大小:1053K)
中文:  中文翻译
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October 2009  
FMS6346  
Six Channel, 6th-Order SD/HD Video Filter Driver  
Features  
Description  
Three selectable sixth-order 8/32MHz (SD/HD) lters  
Three xed sixth-order 8MHz (SD) lters  
Transparent input clamping  
The FMS6346 Low Cost Video Filter (LCVF) is intended  
to replace passive LC lters and drivers with a low-cost  
integrated device. Six sixth-order Butterworth lters pro-  
vide improved image quality compared to typical passive  
solutions. The combination of low-power Standard-Deni-  
tion (SD) and High-Denition (HD) lters greatly simplify  
DVD video output circuitry. Three channels offer xed SD  
lters, while the other three are selectable between SD  
and HD lters.  
Single video load drive (2V , 150Ω, A = 6dB)  
pp  
V
AC- or DC-coupled inputs  
AC- or DC-coupled outputs  
DC-coupled outputs eliminate AC-coupling capacitors  
Low power  
The FMS6346 offers a xed gain of 6dB. The FMS6346  
may be directly driven by a DC-coupled DAC output or an  
AC-coupled signal. Internal diode clamps and bias  
circuitry may be used if AC-coupled inputs are required  
(see Applications section for details).  
5V only  
Robust (12kV HBM) output ESD protection  
Lead-free package - TSSOP-20  
Applications  
Cable and satellite set-top boxes  
The outputs can drive AC- or DC-coupled single (150Ω)  
video loads. DC-coupling the outputs removes the need  
for output coupling capacitors. The input DC levels are  
offset approximately +280mV at the output.  
DVD players  
HDTV  
Personal Video Recorders (PVR)  
Video On Demand (VOD)  
Transparent Clamp  
6dB  
SD IN1  
SD OUT1  
Transparent Clamp  
6dB  
SD IN2  
SD OUT2  
Transparent Clamp  
6dB  
SD IN3  
SD OUT3  
th  
8MHz, 6 order  
Transparent Clamp  
6dB  
6dB  
6dB  
SD/HD IN1  
SD/HD OUT1  
SD/HD OUT2  
SD/HD OUT3  
Transparent Clamp  
SD/HD IN2  
Transparent Clamp  
SD/HD IN3  
Selectable  
8/32MHz  
6th order  
SD/HD  
Figure 1. Block Diagram  
Ordering Information  
Operating  
Temperature  
Part Number  
Gain Option  
Eco Status Package  
Packing Method  
2500 Units on  
Tape and Reel  
FMS6346MTC20X  
6dB  
0°C to 70°C  
RoHS  
TSSOP-20  
For Fairchild’s denition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.  
© 2006 Fairchild Semiconductor  
FMS6346 • Rev. 1.0.5  
www.fairchildsemi.com  
Pin Conguration  
SD IN1  
SD IN2  
SD IN3  
N/C  
SD OUT1  
SD OUT2  
SD OUT3  
GND  
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
3
FMS6346  
20L TSSOP  
4
V
GND  
5
CC  
N/C  
6
F
cSEL  
SD/HD IN1  
SD/HD IN2  
SD/HD IN3  
N/C  
SD/HD OUT1  
SD/HD OUT2  
SD/HD OUT3  
N/C  
7
8
9
10  
Figure 2. Pin Conguration  
Pin Assignments  
Pin#  
1
Pin  
SD IN1  
SD IN2  
SD IN3  
N/C  
Type  
Description  
Input SD video input, channel 1  
Input SD video input, channel 2  
Input SD video input, channel 3  
Input No Connection  
2
3
4
5
VCC  
Input +5V supply  
6
FcSEL  
Input Selects lter corner frequency for pins 7, 8, and 9: “0” = SD, “1” = PS  
7
SD/HD IN1 Input Selectable SD or PS video input, channel 1  
SD/HD IN2 Input Selectable SD or PS video input, channel 2  
SD/HD IN3 Input Selectable SD or PS video input, channel 3  
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
N/C  
N/C  
Input No Connection  
Input No Connection  
SD/HD  
SD/HD  
SD/HD  
N/C  
Out- Filtered SD or PS video output, channel 3  
Out- Filtered SD or PS video output, channel 2  
Out- Filtered SD or PS video output, channel 1  
Input No Connection  
GND  
Input Must be tied to ground  
GND  
Input Must be tied to ground  
SD OUT3  
SD OUT2  
SD OUT1  
Out- Filtered SD video output, channel 3  
Out- Filtered SD video output, channel 2  
Out- Filtered SD video output, channel 1  
© 2006 Fairchild Semiconductor  
FMS6346 • Rev. 1.0.5  
www.fairchildsemi.com  
2
Absolute Maximum Ratings  
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable  
above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition,  
extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute  
maximum ratings are stress ratings only.  
Symbol  
VCC  
Parameter  
Min.  
-0.3  
-0.3  
Max.  
6
Unit  
V
DC Supply Voltage  
VIO  
Analog and Digital I/O  
VCC + 0.3  
V
IOUT  
Output Current, Any One Channel (Do Not Exceed)  
50  
mA  
Reliability Information  
Symbol  
Parameter  
Min.  
Typ.  
Max.  
Unit  
TJ  
TSTG  
TL  
Junction Temperature  
150  
150  
300  
°C  
°C  
°C  
Storage Temperature Range  
-65  
Lead Temperature (Soldering, 10 Seconds)  
Thermal Resistance, JEDEC Standard Multi-Layer Test Boards,  
Still Air  
74  
°C/W  
θJA  
Electrostatic Discharge Information  
Symbols  
Parameter  
Max.  
Unit  
Human Body Model, JESD22-A114  
Charged Device Model, JESD22-C101  
12  
2
ESD  
kV  
Recommended Operating Conditions  
The Recommended Operating Conditions table denes the conditions for actual device operation. Recommended oper-  
ating conditions are specied to ensure optimal performance to the datasheet specications. Fairchild does not recom-  
mend exceeding them or designing to absolute maximum ratings.  
Symbol  
TA  
Parameter  
Min.  
0
Typ.  
Max.  
70  
Unit  
°C  
Operating Temperature Range  
Supply Voltage Range  
VCC  
4.75  
5.00  
5.25  
V
© 2006 Fairchild Semiconductor  
FMS6346 • Rev. 1.0.5  
www.fairchildsemi.com  
3
DC Electrical Characteristics  
TA = 25°C, Vcc = 5V, Rsource = 37.5Ω, inputsAC coupled with 0.1μF, all outputsAC coupled with 220μF into 150Ω loads,  
referenced to 400kHz; unless otherwise noted.  
Symbol  
ICC  
Parameter  
Supply Current(1)  
Conditions  
Min. Typ. Max. Units  
No Load  
60  
80  
mA  
Vpp  
V
VIN  
Video Input Voltage Range  
Digital Input Low(1)  
Referenced to GND, if DC-coupled  
1.4  
VIL  
fcSEL  
fcSEL  
0
0.8  
VIH  
Digital Input High(1)  
2.4  
VCC  
V
Standard-Denition Electrical Characteristics  
TA= 25°C, Vin = 1Vpp, Vcc = 5V, Rsource = 37.5Ω, all inputsAC coupled with 0.1μF, all outputsAC coupled with 220μF into 150Ω  
loads, referenced to 400kHz; unless otherwise noted.  
Symbol  
AVSD  
f1dBSD  
fcSD  
Parameter  
Channel Gain(1)  
Conditions  
Min. Typ. Max. Units  
All SD Channels  
5.8  
5.50  
6.5  
6.0  
7.15  
8.0  
50  
6.2  
dB  
MHz  
MHz  
dB  
%
-1dB Bandwidth(1)  
-3dB Bandwidth(1)  
All SD Channels  
All SD Channels  
fSBSD  
DG  
Attenuation (Stopband Reject)(1) All SD Channels at f = 27MHz  
43  
Differential Gain  
Differential Phase  
Output Distortion  
All SD Channels  
All SD Channels  
0.7  
1.0  
0.35  
-54  
72  
DP  
°
THD  
V
OUT = 1.4Vpp, 3.58MHz  
%
XTALKSD Crosstalk (ch-to-ch)  
at 1MHz  
dB  
dB  
ns  
SNR  
tpdSD  
Signal-to-Noise Ratio(2)  
NTC-7 weighting, 100kHz to 4.2MHz  
Delay from input to output, 4.5MHz  
Propagation Delay  
90  
High-Denition Electrical Characteristics  
TA = 25°C, VIN = 1Vpp, Vcc = 5V, Rsource = 37.5Ω, FcSEL = 1, all inputs AC coupled with 0.1μF, all outputs AC coupled with  
220μF into 150Ω loads, referenced to 400kHz; unless otherwise noted.  
Symbol  
Parameter  
Conditions  
Min. Typ. Max. Units  
AVHD  
Channel Gain(1)  
All HD Channels  
5.8  
28  
30  
30  
6.0  
31  
6.2  
dB  
MHz  
MHz  
dB  
f1dBSHD  
fcHD  
-1dB Bandwidth(1)  
All HD Channels  
-3dB Bandwidth(1)  
All HD Channels  
34  
fSBHD  
THD  
Attenuation (Stopband Reject)(1)  
All HD Channels at f = 74.25MHz  
41  
Output Distortion (All HD Channels) VOUT = 1.4Vpp, 22MHz  
0.9  
-54  
60  
%
XTALKHD Crosstalk (ch-to-ch)  
at 1MHz  
dB  
SNR  
tpdHD  
Signal-to-Noise Ratio(2)  
Propagation Delay  
Unweighted; 100kHz to 30MHz  
Delay from input to output  
dB  
25  
ns  
Notes:  
1. 100% tested at 25°C.  
2. SNR = 20 * log (714mV/rms noise).  
© 2006 Fairchild Semiconductor  
FMS6346 • Rev. 1.0.5  
www.fairchildsemi.com  
4
Typical Performance Characteristics  
TA = 25°C, VIN = 1Vpp, VCC = 5V, Rsource = 37.5Ω, inputsAC coupled with 0.1μF, all outputsAC coupled with 220μF into 150Ω  
loads; unless otherwise noted.  
5
0
0.35  
0.30  
0.25  
0.20  
0.15  
0.10  
0.05  
0
-5  
-10  
-15  
-20  
-25  
-30  
-35  
-40  
-45  
-50  
-0.05  
-0.10  
-0.15  
400kHz  
5
10  
15  
20  
25  
30  
80  
10  
400kHz  
1
2
3
4
6
5
Frequency (MHz)  
Frequency (MHz)  
Figure 3. SD Gain vs. Frequency  
Figure 4. SD Flatness vs. Frequency  
5
0
1.0  
0.9  
0.8  
0.7  
-5  
-10  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0
-15  
-20  
-25  
-30  
-35  
-40  
-0.1  
400kHz 10  
20  
30  
40  
50  
60  
70  
400kHz  
5
10  
15  
20  
25  
30  
Frequency (MHz)  
Frequency (MHz)  
Figure 5. HD Gain vs. Frequency  
Figure 6. HD Flatness vs. Frequency  
70  
60  
50  
40  
30  
20  
25  
20  
15  
10  
5
10  
0
0
400kHz 1  
2
3
4
5
6
7
8
9
400kHz  
5
10 15 20 25 30 35 40 45  
Frequency (MHz)  
Frequency (MHz)  
Figure 8. HD Group Delay vs. Frequency  
Figure 7. SD Group Delay vs. Frequency  
1.0  
1.0  
NTSC  
NTSC  
0.5  
0
0
-1.0  
Min = 0.05  
Min = 0.00  
Max = 0.59  
ppmax = 0.63  
Max = 1.00  
ppmax = 1.00  
-1.0  
-2.0  
1st  
2nd  
3rd  
4th  
5th  
6th  
1st  
2nd  
3rd  
4th  
5th  
6th  
Figure 9. SD Differential Gain  
Figure 10. HD Differential Phase  
© 2006 Fairchild Semiconductor  
FMS6346 • Rev. 1.0.5  
www.fairchildsemi.com  
5
Applications Information  
Functional Description  
0.65V  
The FMS6346 Low-Cost Video Filter (LCVF) provides  
6dB gain from input to output. In addition, the input is  
slightly offset to optimize the output driver performance.  
The offset is held to the minimum required value to de-  
crease the standing DC current into the load. Typical volt-  
age levels are shown in Figure 11.  
Y
OUT  
Y
Driver  
IN  
800kΩ  
Figure 12. Input Clamp Circuit  
1.0 -> 1.02V  
0.65 -> 0.67V  
0.3 -> 0.32V  
I/O Congurations  
For DC-coupled DAC drive with DC-coupled outputs, use  
0.0 -> 0.02V  
V
IN  
the conguration shown in Figure 13.  
2.28V  
1.58V  
Driven by:  
0V - 1.4V  
DC-Coupled DAC Outputs  
AC-Coupled and Clamped  
Y, CV, R, G, B  
DVD or  
STB  
SoC  
LCVF  
Clamp  
Inactive  
75Ω  
0.88V  
0.28V  
V
OUT  
DAC  
Output  
There is a 280mV offset from the DC input level to the  
DC output level. V  
= 2 * V + 280mV.  
OUT  
IN  
Figure 13. DC-Coupled Inputs and Outputs  
0.85V  
0.5V  
If the DAC’s average DC output level causes the signal to  
exceed the range of 0V to 1.4V, it can be AC-coupled as  
shown in Figure 14.  
0.15V  
V
IN  
0V - 1.4V  
0.1μF  
1.98V  
1.28V  
0.58V  
Driven by:  
AC-Coupled and Biased  
U, V, Pb, Pr, C  
DVD or  
STB  
SoC  
DAC  
Output  
LCVF  
Clamp  
Active  
75Ω  
V
OUT  
Figure 11. Typical Voltage Levels  
The FMS6346 provides an internal diode clamp to sup-  
port AC-coupled input signals. If the input signal does not  
go below ground, the input clamp does not operate. This  
allows DAC outputs to directly drive the FMS6346 without  
an AC coupling capacitor. The worst-case sync tip com-  
pression due to the clamp does not exceed 7mV. The in-  
put level set by the clamp, combined with the internal DC  
offset, keeps the output within its acceptable range. When  
the input is AC-coupled, the diode clamp sets the sync tip  
(or lowest voltage) just below ground.  
Figure 14. AC-Coupled Inputs, DC-Coupled Outputs  
When the is driven by an unknown external source or a  
SCART switch with its own clamping circuitry, the inputs  
should be AC-coupled as shown in Figure 15.  
0V - 1.4V  
0.1μF  
LCVF  
Clamp  
Active  
75Ω  
External video  
source must  
be AC coupled  
For symmetric signals like C, U, V, Cb, Cr, Pb, and Pr; the  
average DC bias is fairly constant and the inputs can be  
AC-coupled with the addition of a pull-up resistor to set  
the DC input voltage. DAC outputs can also drive these  
same signals without the AC coupling capacitor. A con-  
ceptual illustration of the input clamp circuit is shown in  
Figure 12.  
75Ω  
Figure 15. SCART Conguration with DC-Coupled  
Outputs  
© 2006 Fairchild Semiconductor  
FMS6346 • Rev. 1.0.5  
www.fairchildsemi.com  
6
The same method can be used for biased signals with the  
addition of a pull-up resistor to make sure the clamp never  
operates. The internal pull-down resistance is 800kΩ  
±20%, so the external resistance should be 7.5MΩ to set  
the DC level to 500mV. If a pull-up resistance less than  
7.5MΩ is desired, an external pull-down can be added  
such that the DC input level is set to 500mV.  
Power Dissipation  
The FMS6346 output drive conguration must be consid-  
ered when calculating overall power dissipation. Care  
must be taken not to exceed the maximum die junction  
temperature. The following example can be used to calcu-  
late the FMS6346’s power dissipation and internal tem-  
perature rise:  
TJ = TA + Pd θJA  
External video  
source must  
be AC coupled  
where Pd = PCH1 + PCH2 + PCHx  
7.5MΩ  
0.1μF  
LCVF  
Bias  
75Ω  
2
and PCHx = Vs • ICH - (VO /RL)  
Input  
where  
75Ω  
500mV +/-350mV  
VO = 2Vin + 0.280V  
ICH = (ICC / 6) + (VO/RL)  
VIN = RMS value of input signal  
ICC = 60mA  
Figure 16. Biased SCART with DC-Coupled Outputs  
Vs = 5V  
The same circuits can be used with AC-coupled outputs if  
desired, as shown in Figure 17.  
RL = channel load resistance  
Board layout can affect thermal characteristics. Refer to  
the Layout Considerations section for more information.  
0V - 1.4V  
220µF  
DVD or  
STB  
SoC  
DAC  
Output  
LCVF  
Clamp  
Inactive  
75Ω  
Layout Considerations  
General layout and supply bypassing play major roles in  
high-frequency performance and thermal characteristics.  
Fairchild offers a demonstration board, FMS6346DEMO,  
to guide layout and aid device testing and characteriza-  
tion. The FMS6346DEMO is a four-layer board with a full  
power and ground plane. Following this layout congura-  
tion provides the optimum performance and thermal char-  
acteristics. For best results, follow the steps below as a  
basis for high-frequency layout:  
Figure 17 DC-Coupled Inputs, AC-Coupled Outputs  
0V - 1.4V  
• Include 10μF and 0.1μF ceramic bypass capacitors  
0.1μF  
220μF  
DVD or  
STB  
SoC  
DAC  
Output  
LCVF  
Clamp  
Active  
75Ω  
• Place the 10μF capacitor within 0.75 inches of the  
power pin  
• Place the 0.1μF capacitor within 0.1 inches of the  
power pin  
• For multi-layer boards, use a large ground plane to  
help dissipate heat  
Figure 18. AC-Coupled Inputs, AC-Coupled Outputs  
• For two-layer boards, use a ground plane that extends  
beyond the device by at least 0.5 inches  
External video  
source must  
be AC coupled.  
• Minimize all trace lengths to reduce series inductances  
7.5MΩ  
0.1μF  
220μF  
LCVF  
Clamp  
Active  
75Ω  
Output Considerations  
The FMS6346 outputs are DC offset from the input by  
150mV. Therefore, VOUT = 2•VIN DC+150mV. This offset is  
required to obtain optimal performance from the output  
driver and is held at the minimum value to decrease the  
standing DC current into the load. Since the FMS6346  
has a 2x (6dB) gain, the output is typically connected via a  
75-series back-matching resistor, followed by the 75ꢀ  
video cable. Due to the inherent divide by two of this con-  
guration, the blanking level at the load of the video signal  
is always less than 1V. When AC-coupling the output,  
ensure that the coupling capacitor of choice passes the  
lowest frequency content in the video signal and that line  
time distortion (video tilt) is kept as low as possible.  
75Ω  
500mV +/-350mV  
Figure 19. Biased SCART with AC-Coupled Outputs  
NOTE: The video tilt or line time distortion is dominated by  
the AC-coupling capacitor. The value may need to be in-  
creased beyond 220μF to obtain satisfactory operation in  
some applications.  
© 2006 Fairchild Semiconductor  
FMS6346 • Rev. 1.0.5  
www.fairchildsemi.com  
7
The selection of the coupling capacitor is a function of the  
subsequent circuit input impedance and the leakage cur-  
rent of the input being driven. To obtain the highest quality  
output video signal, the series termination resistor must be  
placed as close to the output pin as possible. This reduces  
the parasitic capacitance and inductance effect on the out-  
put driver. The distance from the device pin to the series  
termination resistor should be no greater than 0.1 inches.  
Figure 21 Distance from Device Pin to Series  
Termination Resistor  
Typical Application Diagram  
The following circuit may be used for direct DC-coupled drive by DACs with an output voltage range of 0V to 1.4V.  
AC-coupled or DC-coupled outputs may be used with AC-coupled outputs offering slightly lower power dissipation.  
+5V  
DVD Player or STB  
0.1  
10.0  
µF  
µF  
75Ω  
75Ω  
75Ω  
220µF  
220µF  
220µF  
75Ω Video Cables  
Y1  
C
1
2
20  
Y1OUT  
SD IN1  
SD IN2  
SD IN3  
N/C  
SD OUT1  
SD OUT2  
SD OUT3  
GND  
75Ω  
75Ω  
75Ω  
19  
COUT  
CV  
3
4
5
7
8
9
18  
CVOUT  
16, 17  
Video  
SoC  
FMS6346  
20L TSSOP  
Vcc  
75Ω  
75Ω  
75Ω  
220µF  
220µF  
220µF  
75Ω Video Cables  
Y2/G  
Pb/B  
Pr/R  
14  
13  
G/Y2OUT  
B/PbOUT  
R/PrOUT  
SD/HD IN1  
SD/HD IN2  
SD/HD OUT1  
SD/HD OUT2  
75Ω  
75Ω  
75Ω  
SD/HD IN3  
N/C  
SD/HD OUT3 12  
F
cSEL  
15  
6
AC-coupling caps  
are optional  
DAC load resistors  
Figure 20. Typical Application Diagram  
© 2006 Fairchild Semiconductor  
FMS6346 • Rev. 1.0.5  
www.fairchildsemi.com  
8
Physical Dimensions  
Figure 21. 20-Lead, Thin-Shrink Outline Package (TSSOP)  
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specically the warranty therein, which covers Fairchild products.  
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:  
http://www.fairchildsemi.com/packaging/.  
© 2006 Fairchild Semiconductor  
FMS6346 • Rev. 1.0.5  
www.fairchildsemi.com  
9
© 2006 Fairchild Semiconductor  
FMS6346 • Rev. 1.0.5  
www.fairchildsemi.com  
10  
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