FMS6502MTC24X [ONSEMI]
8 输入，6 输出视频开关矩阵，带输出驱动器;
| 型号： | FMS6502MTC24X |
| 厂家： | 
ONSEMI |
| 描述： | 8 输入，6 输出视频开关矩阵，带输出驱动器 开关 PC 驱动 光电二极管 驱动器 |
| 文件： | 总15页 (文件大小：656K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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January 2007
FMS6502
8-Input, 6-Output Video Switch Matrix with Output Drivers,
Input Clamp, and Bias Circuitry
Features
Description
■ 8 x 6 Crosspoint Switch Matrix
■ Supports SD, PS, and HD 1080i / 1080p Video
■ Input Clamp and Bias Circuitry
■ Doubly Terminated 75Ω Cable Drivers
■ Programmable 0dB or 6dB Gain
■ AC- or DC-Coupled Inputs
The FMS6502 provides eight inputs that can be routed to
any of six outputs. Each input can be routed to one or
more outputs, but only one input may be routed to any
output.
Each input supports an integrated clamp option to set the
output sync tip level of video with sync to ~300mV. Alter-
natively, the input may be internally biased to center out-
put signals without sync (Chroma, Pb, Pr) at ~1.25V.
■ AC- or DC-Coupled Outputs
■ One-to-One or One-to-Many Input-to-Output
All outputs are designed to drive a 150Ω DC-coupled
load. Each output can be programmed to provide either
0dB or 6dB of signal gain.
Switching
■ I2CTM-Compatible Digital Interface, Standard Mode
■ 3.3V or 5V Single Supply Operation
■ Pb-Free TSSOP-24 Package
Input-to-output routing and input bias mode functions are
controlled via an I2C-compatible digital interface.
Applications
■ Cable and Satellite Set-Top Boxes
Block Diagram
■ TV and HDTV Sets
IN1
C / B
■ A / V Switchers
IN2
C / B
■ Personal Video Recorders (PVR)
■ Security and Surveillance
■ Video Distribution
■ Automotive (In-Cabin Entertainment)
IN8
C / B
SDA
SCL
ADDR0
ADDR1
VCC (2)
GND (4)
OUT1
OUT2
OUT6
Figure 1. Block Diagram
Ordering Information
Operating
Part Number
Pb-Free
Temperature Range
Package
Packing Method
24-Lead Thin Shrink Small
Ouline Package
FMS6502MTC24
Yes
-40°C to 85°C
Rail
24-Lead Thin Shrink Small
Ouline Package
FMS6502MTC24X
Yes
-40°C to 85°C
Reel
© 2006 Fairchild Semiconductor Corporation
Rev. 1.0.0
www.fairchildsemi.com
Pin Configuration
Pin Description
Pin#
1
Pin
IN1
Type Description
Input Input, channel 1
Output Must be tied to ground
IN1
GND
IN2
1
2
24
23
22
21
20
19
18
17
16
15
14
13
GND
OUT1
OUT2
OUT3
VDD
OUT4
OUT5
OUT6
GND
IN8
2
GND
IN2
FAIRCHILD
FMS6502
3
Input
Input
Input
Input, channel 2
3
4
VDD
IN3
Positive power supply
Input, channel 3
5
VDD
IN3
4
6
GND
IN4
Output Must be tied to ground
24L TSSOP
7
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input, channel 4
Selects I2C address
5
8
ADDR1
IN5
GND
IN4
6
9
Input, channel 5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ADDR0
IN6
Selects I2C address
Input, channel 6
Serial clock for I2C port
7
SCL
ADDR1
IN5
8
IN7
Input, channel 7
9
SDA
IN8
Serial data for I2C port
Input, channel 8
ADDR0
IN6
10
11
12
GND
OUT6
OUT5
OUT4
VDD
OUT3
OUT2
OUT1
GND
Output Must be tied to ground
Output Output, channel 6
Output Output, channel 5
Output Output, channel 4
SDA
SCL
IN7
Input
Positive power supply
Figure 2. Pin Configuration
Output Output, channel 3
Output Output, channel 2
Output Output, channel 1
Output Must be tied to ground
© 2006 Fairchild Semiconductor Corporation
FMS6502 Rev. 1.0.0
www.fairchildsemi.com
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-
ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-
tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only.
Parameter
Min.
-0.3
-0.3
Max.
6
Unit
V
DC Supply Voltage
Analog and Digital I/O
Vcc + 0.3
40
V
Output Current Any One Channel, Do Not Exceed
mA
Reliability Information
Symbol
TJ
Parameter
Min.
Typ.
Max.
Unit
°C
Junction Temperature
150
150
300
TSTG
TL
Storage Temperature Range
-65
°C
Lead Temperature (Soldering, 10s)
°C
Thermal Resistance, JEDEC Standard Multi-Layer Test Boards,
Still Air
ΘJA
84
°C/W
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
TA
Parameter
Operating Temperature Range
Supply Voltage Range
Min.
-40
Typ.
Max.
85
Unit
°C
VCC
3.135
5.0
5.25
V
Electrostatic Discharge Information
Symbol
HBM
Parameter
Human Body Model (JEDEC: JESD22-A114)
Charged Device Model (JEDEC: JESD22-A101)
Value
Unit
10
2
kV
kV
CDM
© 2006 Fairchild Semiconductor Corporation
FMS6502 Rev. 1.0.0
www.fairchildsemi.com
3
Digital Interface
The I2C-compatibe interface is used to program output
enables, input-to-output routing, and input bias configu-
ration. The I2C address of the FMS6502 is 0x06 (0000
0110) with the ability to offset based upon the values of
the ADDR0 and ADDR1 inputs. Offset addresses are
defined below:
ADDR1
ADDR0
Binary
Hex
0x06
0x46
0x86
0xC6
0
0
1
1
0
1
0
1
0000 0110
0100 0110
1000 0110
1100 0110
Data and address data of eight bits each are written to
the FMS6502 I2C address register to access control
functions.
The clamp / bias control bits are written to their own
internal address since they should remain the same
regardless of signal routing. They are set based on the
input signal that is connected to the FMS6502.
For efficiency, a single data register is shared between
two outputs for input selection. More than one output can
select the same input channel for one-to-many routing.
All undefined addresses may be written without effect.
Output Control Register Contents and Defaults
Control Name
Width
Type
Default
Bit(s)
Description
Input selected to drive this output:
In-A
4 bits
Write
0
3:0
0000=OFF1, 0001=IN1, 0010=IN2, 1000=IN8
Input selected to drive this output:
In-B
4 bits
Write
0
7:4
0000=OFF1, 0001=IN1, 0010=IN2, 1000=IN8
Output Control Register MAP
Name
OUT1,2
OUT3,4
OUT5,6
Address
0x00
Bit 7
Bit 6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
B3-Out2 B2-Out2 B1-Out2 B0-Out2 B3-Out1 B2-Out1 B1-Out1 B0-Out1
B3-Out4 B2-Out4 B1-Out4 B0-Out4 B3-Out3 B2-Out3 B1-Out3 B0-Out3
B3-Out6 B2-Out6 B1-Out6 B0-Out6 B3-Out5 B2-Out5 B1-Out5 B0-Out5
0x01
0x02
Clamp Control Register Contents and Defaults
Control Name
Width
Type
Default
Bit(s)
Description
Clmp
1 bit
Write
0
7:0
Clamp / Bias selection: 1 = Clamp, 0 = Bias
Clamp Control Register Map
Name
Address
Bit 7
Bit 6
Bit5
Clmp6
Bit4
Bit3
Bit2
Bit1
Bit0
CLAMP
0x03
Clmp8
Clmp7
Clmp5
Clmp4
Clmp3
Clmp2
Clmp1
Gain Control Register Contents and Defaults
Control Name
Width
Type
Default
Bit(s)
7:0
Description
Output Gain selection: 0 = 6dB, 1 = 0dB
Gain
1 bit
Write
0
Gain Control Register Map
Name
Address
Bit 7
Bit 6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
GAIN
0x04
Unused Unused
Gain6
Gain5
Gain4
Gain3
Gain2
Gain1
Note:
1. When the OFF input selection is used, the output amplifier is powered down and enters a high-impedance state.
© 2006 Fairchild Semiconductor Corporation
FMS6502 Rev. 1.0.0
www.fairchildsemi.com
4
DC Electrical Characteristics
TA = 25°C, Vcc = 5V, Vin = 1Vpp, input bias mode, one-to-one routing, 6dB gain, all inputs AC-coupled with 0.1μF,
unused inputs AC-terminated through 75Ω to GND, all outputs AC-coupled with 220μF into 150Ω, referenced to
400kHz unless otherwise noted.
Symbol
ICC
Parameter
Supply Current(1)
Conditions
Min.
Typ.
55
Max.
Unit
mA
Vpp
V
No Load, All Outputs Enabled
75
VOUT
Video Output Range
DC Input Level(1)
DC Output Level(1)
DC Output Level(1)
DC Input Level(1)
DC Output Level(1)
DC Output Level(1)
2.8
Clamp Mode, All Gain Settings
Clamp Mode, 0dB Gain Setting
Clamp Mode, 6dB Gain Setting
Bias Mode, All Gain Settings
Bias Mode, 0dB Gain Setting
Bias Mode, 6dB Gain Setting
0.10
0.10
0.15
0.15
0.30
0.625
0.625
1.250
90
0.20
0.20
Vclamp
V
0.20
0.40
V
0.575
0.575
1.150
0.675
0.700
1.400
V
Vbias
V
V
PSRR
Power Supply Rejection Ratio All Channels, DC
dB
Note:
1. 100% tested at 25°C.
AC Electrical Characteristics
TA= 25°C, Vcc = 5V, Vin = 1Vpp, input bias mode, one-to-one routing, 6dB gain, all inputs AC-coupled with 0.1μF,
unused inputs AC-terminated through 75Ω to GND, all outputs AC-coupled with 220μF into 150Ω, referenced to
400kHz unless otherwise noted.
Symbol
AV0dB
AV6dB
f+1dB
f-1dB
fC
Parameter
Channel Gain(1)
Channel Gain(1)
Conditions
Min.
-0.2
5.8
Typ.
0
Max.
+0.2
6.2
Unit
dB
dB
MHz
MHz
MHz
%
DC, All Channels, 0dB Gain Setting
DC, All Channels, 6dB Gain Setting
6
+1dB Peaking Bandwidth VOUT = 1.4Vpp
65
-1dB Bandwidth
-3dB Bandwidth
Differential Gain
Differential Phase
VOUT = 1.4Vpp
90
VOUT = 1.4Vpp
115
0.1
0.2
0.05
0.4
-77
-62
-81
-62
-50
78
dG
VCC = 5.0V , 3.58MHz
VCC = 5.0V , 3.58MHz
VOUT = 1.4Vpp, 5MHz, VCC = 5.0V
VOUT = 1.4Vpp, 22MHz, VCC = 5.0V
dφ
°
THDSD SD Output Distortion
THDHD HD Output Distortion
XTALK1 Input Crosstalk
%
%
(2)
1MHz, VOUT = 2Vpp
dB
dB
dB
dB
dB
dB
(2)
XTALK2 Input Crosstalk
15MHz, VOUT = 2Vpp
(3)
XTALK3 Output Crosstalk
XTALK4 Output Crosstalk
XTALK5 Multi-Channel Crosstalk
SNRSD Signal-to-Noise Ratio(5)
1MHz, VOUT = 2Vpp
(3)
15MHz, VOUT = 2Vpp
(4)
Standard Video, VOUT = 2Vpp
NTC-7 Weighting, 4.2MHz LP,
100kHz HP
VNOISE Channel Noise
400kHz to 100MHz, Input Referred
Post I2C Programming
20
nV/ Hz
√
AMPON Amplifier Recovery Time
300
ns
Notes:
1. 100% tested at 25°C.
2. Adjacent input pair to adjacent output pair. Interfering input is through an open switch.
3. Adjacent input pair to adjacent output pair. Interfering input is through a closed switch.
4. Crosstalk of eight synchronous switching outputs onto single, asynchronous switching output.
5. SNR = 20 * log (714mV / rms noise).
© 2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FMS6502 Rev. 1.0.0
5
2
I C BUS Characteristics
TA = 25°C, Vcc = 5V unless otherwise noted.
Symbol
Parameter
Digital Input Low1
Digital Input High1
Clock Frequency
Input Rise Time
Input Fall Time
Conditions
SDA,SCL,ADDR
SDA,SCL,ADDR
SCL
Min.
0
Typ.
Max.
1.5
Unit
V
Vil
Vih
fSCL
tr
3.0
Vcc
V
100
1000
300
4.7
4.0
300
0
kHz
ns
ns
µs
µs
ns
ns
µs
µs
µs
µs
1.5V to 3V
tf
1.5V to 3V
tlow
thigh
Clock Low Period
Clock High Period
tSU,DAT Data Set-up Time
tHD,DAT Data Hold Time
tSU,STO Set-up Time from Clock High to Stop
4
tBUF
Start Set-up Time following a Stop
4.7
4
tHD,STA Start Hold Time
tSU,STA Start Set-up Time following Clock Low to High
4.7
Note:
1. 100% tested at 25°C.
SDA
SCL
t
t
BUF
LOW
t
f
t
t
t
t
t
HD,STA
HD,DAT
HIGH
SU,DAT
r
SDA
t
t
SU,STA
SU,STO
Figure 3. I2C Bus Timing
© 2006 Fairchild Semiconductor Corporation
FMS6502 Rev. 1.0.0
www.fairchildsemi.com
6
2
I C Interface
Operation
The I2C-compatible interface conforms to the I2C specifi-
cation for Standard Mode. Individual addresses may be
written, but there is no read capability. The interface con-
sists of two lines: a serial data line (SDA) and a serial
clock line (SCL). Both lines must be connected to a posi-
tive supply through an external resistor. Data transfer
may be initiated only when the bus is not busy.
Bit Transfer
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during the
HIGH period of the clock pulse. Changes in the data line
during this time are interpreted as control signals.
SCL
SDA
Data line
stable;
Change
of data
data valid
allowed
Figure 4. Bit Transfer
Start and Stop conditions
Both data and clock lines remain HIGH when the bus is
not busy. A HIGH-to-LOW transition of the data line,
while the clock is HIGH, is defined as start condition (S).
A LOW-to-HIGH transition of the data line, while the
clock is HIGH, is defined as stop condition (P).
SCL
S
P
SDA
STOP condition
START condition
Figure 5. START and STOP conditions
© 2006 Fairchild Semiconductor Corporation
FMS6502 Rev. 1.0.0
www.fairchildsemi.com
7
Acknowledge
The number of data bytes transferred between the start
and stop conditions from transmitter to receiver is unlim-
ited. Each byte of eight bits is followed by an acknowl-
edge bit. The acknowledge bit is a HIGH level signal put
on the bus by the transmitter while the master generates
an extra acknowledge-related clock pulse. The slave
receiver addressed must generate an acknowledge after
the reception of each byte. A master receiver must gen-
erate an acknowledge after the reception of each byte
clocked out of the slave transmitter.
The device that acknowledges must pull down the SDA
line during the acknowledge clock pulse so the SDA line
is stable LOW during the HIGH period of the acknowl-
edge-related clock pulse (set-up and hold times must be
taken into consideration). A master receiver must signal
an end of data to the transmitter by not generating an
acknowledge on the last byte clocked out of the slave. In
this event, the transmitter must leave the data line HIGH
to enable the master to generate a stop condition.
START
condition
clock pulse for
acknowledgement
SCL FROM
MASTER
1
2
8
9
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
Figure 6. Acknowledgement on the I2C Bus
2
I C Bus Protocol
Before any data is transmitted on the I2C bus, the device
which is to respond is addressed first. The addressing is
always carried out with the first byte transmitted after the
start procedure. The I2C bus configuration for a data
write to the FMS6502 is shown in Figure 7.
1
9
1
9
SCL
SDA
A5
A4
A3
A2
A1
A0 R/W
D7
D6
D5
D4
D3
D2
D1
D0
A6
ACK. BY
FMS6502
ACK. BY
FMS6502
START BY
MASTER
FRAME1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
9
1
SCL(CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
SDA(CONTINUED)
ACK. BY
FMS6502
STOP BY
MASTER
FRAME 3
DATA BYTE
Figure 7. Write Register Address to Pointer Register; Write Data to Selected Register
3.3V Operation
The FMS6502 operates from a single 3.3V supply. With
Vcc = 3.3V, the digital input low (Vil) is 0V to 1V and the
digital input high (Vih) is 1.8V to 2.9V.
© 2006 Fairchild Semiconductor Corporation
FMS6502 Rev. 1.0.0
www.fairchildsemi.com
8
Applications Information
Input Clamp / Bias Circuitry
Output Configuration
The FMS6502 can accommodate AC- or DC-coupled
inputs. Internal clamping and bias circuitry are provided
to support AC-coupled inputs. These are selectable
through the CLMP bits via the I2C-compatible interface.
For DC-coupled inputs, the device should be pro-
grammed to use the 'bias' input configuration. In this con-
figuration, the input is internally biased to 625mV through
a 100kΩ resistor. Distortion is optimized with the output
levels set between 250mV above ground and 500mV
below the power supply.
The FMS6502 outputs may be AC or DC-coupled. DC-
coupled loads can drive a 150Ω load. AC-coupled out-
puts are capable of driving a single, doubly terminated
video load of 150Ω. An external transistor is needed to
drive DC low-impedance loads. DC-coupled outputs
should be connected as indicated in Figure 10.
75
FMS6502
Output
Amplifier
75
With AC-coupled inputs, the FMS6502 uses a simple
clamp rather than a full DC-restore circuit. For video sig-
nals with and without sync; (Y,CV,R,G,B), the lowest volt-
age at the output pins is clamped to approximately
300mV above ground.
If symmetric AC-coupled input signals are used
(Chroma,Pb,Pr,Cb,Cr), the bias circuit can be used to
center them within the input common range. The aver-
age DC value at the output is approximately 1.27V.
Figure 10. DC-Coupled Load Connection
Configure AC-coupled loads as shown in Figure 11.
Figure 8 shows the clamp mode input circuit and the
internally controlled voltage at the input pin for AC-cou-
pled inputs.
220µF
75
FMS6502
Output
Amplifier
Lowest voltage
set to 125mV
75
0.1µF
FMS6502
Input
Clamp
Video source must
be AC coupled
75
Figure 11. AC-Coupled Load Connection
When an output channel is not connected to an input, the
input to that particular channel’s amplifier is forced to
approximately 150mV. The output amplifier is still active
unless specifically disabled by the I2C interface. Voltage
output levels depend on the programmed gain for that
channel.
Figure 8. Clamp Mode Input Circuit
Figure 9 shows the bias mode input circuit and the inter-
nally controlled voltage at the input pin for AC-coupled
inputs.
Average voltage
Driving Capacitive Loads
set to 625m
V
When driving capacitive loads, use a 10Ω-series resis-
tance to buffer the output, as indicated in Figure 12.
0.1µF
FMS6502
Input
Bias
Video source must
be AC coupled
10
FMS6502
75
Output
CL
Amplifier
Figure 9. Bias Mode Input Circuit
Figure 12. Driving Capacitive Loads
© 2006 Fairchild Semiconductor Corporation
FMS6502 Rev. 1.0.0
www.fairchildsemi.com
9
Crosstalk
Crosstalk is an important consideration when using the
FMS6502. Input and output crosstalk represent the two
major coupling modes that may be present in a typical
application. Input crosstalk is crosstalk in the input pins
and switches when the interfering signal drives an open
switch. It is dominated by inductive coupling in the pack-
age lead frame between adjacent leads. It decreases
rapidly as the interfering signal moves further away from
the pin adjacent to the input signal selected. Output
crosstalk is coupling from one driven output to another
active output. It decreases with increasing load imped-
ance as it is caused mainly by ground and power cou-
pling between output amplifiers. If a signal is driving an
open switch, its crosstalk is mainly input crosstalk. If it is
driving a load through an active output, its crosstalk is
mainly output crosstalk.
Crosstalk from multiple sources into a given channel is
measured with the setup shown in Figure 14. Input In1 is
driven with a 1Vpp pulse source and connected to out-
puts Out1 to Out8. Input In9 is driven with a secondary,
asynchronous gray field video signal and is connected to
Out9. All other inputs are AC terminated with 75Ω.
Crosstalk effects on the gray field are measured and cal-
culated with respect to a standard 1Vpp output measured
at the load.
If not all inputs and outputs are needed, avoid using
adjacent channels to reduce crosstalk.
TERMINATION
IN1
Bias
Input and output crosstalk measurements are performed
with the test configuration shown in Figure 13.
IN1 driven with
SD video 1VPP
IN6 driven with
asynchronous
.
SD video 1VPP
.
TERMINATION
IN2,3,4,5,7,8 are
AC-term to GND
Bias
IN1
with 75
IN6
.
Bias
Bias
IN2 - IN8 are
AC-Term to
Ground
w/75
IN1 = 1V
PP
Open switch
for input
IN8
crosstalk.
Close switch
for output
crosstalk.
Measure crosstalk from
channels 1-5 into
channel6
OUT1
OUT6
IN8
Bias
Figure 14. Test Configuration for Multi-Channel
Crosstalk
Gain = 6dB
Out1 = 2.0V
Input Crosstalk from IN1
to OUTx
PP
Output Crosstalk from
OUT1 to OUTx
OUT1
OUT6
Figure 13. Test Configuration for Crosstalk
For input crosstalk, the switch is open and all inputs are
in bias mode. Channel 1 input is driven with a 1Vpp sig-
nal, while all other inputs are AC terminated with 75Ω. All
outputs are enabled and crosstalk is measured from IN1
to any output.
For output crosstalk, the switch is closed. Crosstalk from
OUT1 to any output is measured.
© 2006 Fairchild Semiconductor Corporation
FMS6502 Rev. 1.0.0
www.fairchildsemi.com
10
Layout Considerations
General layout and supply bypassing play a major role in
high-frequency performance and thermal characteristics.
Fairchild offers a demonstration board to guide layout
and aid device evaluation. The demo board is a four-
layer board with full power and ground planes. Following
this layout configuration provides optimum performance
and thermal characteristics for the device. For the best
results, follow the steps and recommended routing rules
listed below.
• Make the PCB as thin as possible by reducing FR4
thickness.
• Use vias in power pad to tie adjacent layers together.
• Remember that baseline temperature is a function of
board area, not copper thickness.
• Modeling techniques can provide a first-order approxi-
mation.
Power Dissipation
Recommended Routing/Layout Rules
Worst-case, additional die power due to DC loading can
be estimated at Vcc2/4Rload per output channel. This
assumes a constant DC output voltage of Vcc/2. For 5V
Vcc with a dual DC video load, add 25/(4*75) = 83mW,
per channel.
• Do not run analog and digital signals in parallel.
• Use separate analog and digital power planes to sup-
ply power.
• Traces should run on top of the ground plane at all
times.
Applications for the FMS6502 Video Switch
Matrix
• No trace should run over ground/power splits.
• Avoid routing at 90-degree angles.
The increased demand for consumer multimedia sys-
tems has created a large challenge for system designers
to provide cost-effective solutions to capitalize on the
growth potential in graphics display technologies. These
applications require cost-effective video switching and fil-
tering solutions to deploy high-quality display technolo-
gies rapidly and effectively to the target audience. Areas
of specific interest include HDTV, media centers, and
automotive infotainment (such as navigation, in-cabin
entertainment, and back-up cameras). In all cases, the
advantages the integrated video switch matrix provides
are high-quality video switching specific to the applica-
tion, as well as video input clamps and on-chip, low-
impedance output cable drivers with switchable gain.
• Minimize clock and video data trace length differ-
ences.
• Include 10µF and 0.1µF ceramic power supply bypass
capacitors.
• Place the 0.1µF capacitor within 0.1 inches of the
device power pin.
• Place the 10µF capacitor within 0.75 inches of the
device power pin.
• For multilayer boards, use a large ground plane to
help dissipate heat.
• For two-layer boards, use a ground plane that extends
beyond the device body by at least 0.5 inches on all
sides. Include a metal paddle under the device on the
top layer.
Generally the largest application for a video switch is for
the front-end of an HDTV. This is used to take multiple
inputs and route them to their appropriate signal paths
(main picture and picture-in-picture, or PiP). These are
normally routed into ADCs that are followed by decod-
ers. Technologies for HDTV include LCD, plasma, and
CRT, which have similar analog switching circuitry.
• Minimize all trace lengths to reduce series inductance.
Thermal Considerations
Since the interior of most systems, such as set-top
boxes, TVs, and DVD players, are at +70ºC; consider-
ation must be given to providing an adequate heat sink
for the device package for maximum heat dissipation.
When designing a system board, determine how much
power each device dissipates. Ensure that devices of
high power are not placed in the same location, such as
directly above (top plane) or below (bottom plane) each
other on the PCB.
TM
VIPDEMO Control Software
The FMS6502 is configured via an I2C-compatible digital
interface. To facilitate demonstration, Fairchild Semicon-
ductor had developed the VIPDEMOTM GUI-based con-
trol software to write to the FMS6502 register map. This
software is included in the FMS6502DEMO kit. A parallel
port I2C adapter and an interface cable to connect to the
demo board are also included. Besides using the full
FMS6502 interface, the VIPDEMOTM can also be used
to control single register read and writes for I2C.
PCB Thermal Layout Considerations
• Understand the system power requirements and envi-
ronmental conditions.
• Maximize thermal performance of the PCB.
• Consider using 70µm of copper for high-power
designs.
© 2006 Fairchild Semiconductor Corporation
FMS6502 Rev. 1.0.0
www.fairchildsemi.com
11
Physical Dimensions
Dimensions are in millimeters unless otherwise noted.
Figure 15. 24-Lead Thin Shrink Small Outline Package
© 2006 Fairchild Semiconductor Corporation
FMS6502 Rev. 1.0.0
www.fairchildsemi.com
12
© 2006 Fairchild Semiconductor Corporation
FMS6502 Rev. 1.0.0
www.fairchildsemi.com
13
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