FNA25012A [ONSEMI]
智能功率模块，1200V，50A;
| 型号： | FNA25012A |
| 厂家： | 
ONSEMI |
| 描述： | 智能功率模块，1200V，50A |
| 文件： | 总15页 (文件大小：696K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FNA25012A
1200 V Motion SPM)
2ꢀSeries
General Description
The FNA25012A is a Motion SPM 2 module providing
®
a fully−featured, high−performance inverter output stage for AC
induction, BLDC, and PMSM motors. These modules integrate
optimized gate drive of the built−in IGBTs to minimize EMI and
losses, while also providing multiple on−module protection features:
under−voltage lockouts, over−current shutdown, temperature sensing,
and fault reporting. The built−in, high−speed HVIC requires only
a single supply voltage and translates the incoming logic−level gate
inputs to high−voltage, high−current drive signals to properly drive the
module’s internal IGBTs. Separate negative IGBT terminals are
available for each phase to support the widest variety of control
algorithms.
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Features
• 1200 V − 50 A 3−Phase IGBT Inverter, Including Control Ics for
Gate Drive and Protections
• Low−Loss, Short−Circuit−Rated IGBTs
• Very Low Thermal Resistance Using AIN DBC Substrate
• Built−In Bootstrap Diodes and Dedicated Vs Pins Simplify PCB
Layout
SPMCA−A34/34 LD, PDD STD, DBC DIP TYPE
CASE MODFQ
• Separate Open−Emitter Pins from Low−Side IGBTs for Three−Phase
Current Sensing
Figure 1. 3D Package Drawing
• Single−Grounded Power Supply Supported
• Built−In NTC Thermistor for Temperature Monitoring and
Management
(Click to Activate 3D Content)
MARKING DIAGRAM
• Adjustable Over−Current Protection via Integrated Sense−IGBTs
• Isolation Rating of 2500 Vrms/1 min.
Applications
FNA25012A
XXX YWW
• Motion Control − Industrial Motor (AC 400 V Class)
Related Resources
®
• AN9075 − Users Guide for 1200 V SPM 2 Series
®
• AN9076 − Mounting Guide for New SPM 2 Package
®
• AN9079 − Thermal Performance of 1200 V Motion SPM 2 Series
FNA25012A
XXX
= Specific Device Code
= Lot Code
by Mounting Torque
YWW
= Work Week Code
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
October, 2018 − Rev. 3
FNA25012A/D
FNA25012A
PACKAGE MARKING AND ORDERING INFORMATION
Device
Device Marking
Package
Packing Type
Quantity
FNA25012A
FNA25012A
SPMCB−A34
Rail
6
Integrated Power Functions
• 1200 V − 50 A IGBT inverter for three−phase DC/AC power conversion (Refer to Figure 3)
Integrated Drive, Protection and System Control Functions
• For inverter high−side IGBTs: gate−drive circuit, high−voltage isolated high−speed level shifting control circuit,
Under−Voltage Lock−Out Protection (UVLO), Available bootstrap circuit example is given in Figures 5 and 15
• For inverter low−side IGBTs: gate−drive circuit, Short−Circuit Protection (SCP) control circuit, Under−Voltage
Lock−Out Protection (UVLO)
• Fault signaling: corresponding to UV (low−side supply) and SC faults
• Input interface: active−HIGH interface, works with 3.3/5 V logic, Schmitt−trigger input
PIN CONFIGURATION
(34) V
(33) V
S(W)
B(W)
(32) V
(31) V
BD(W)
CC(WH)
(1) P
(30) IN
(WH)
(29) V
(28) V
S(V)
B(V)
(2) W
(3) V
(27) V
(26) V
BD(V)
CC(VH)
(25) IN
(VH)
(24) V
(23) V
S(U)
B(U)
Case Temperature (T )
Detecting Point
C
(22) V
(21) V
BD(U)
CC(UH)
(20) COM
(H)
(UH)
(4) U
(19) IN
(18) R
(17) C
(16) C
SC
(5) N
W
SC
(6) N
FOD
FO
(WL)
(VL)
(UL)
V
(15) V
(14) IN
(13) IN
(12) IN
(7) N
(8) R
U
(11) COM
(10) VCC
(L)
(L)
TH
TH
(9) V
Figure 2. Top View
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2
FNA25012A
PIN DESCRIPTIONS
Pin Number
Pin Name
Pin Description
1
2
P
Positive DC−Link Input
)
W
V
Output for W−Phase
Output for V−Phase
Output for U−Phase
3
4
U
5
N
Negative DC−Link Input for W−Phase
W
6
N
V
N
U
Negative DC−Link Input for V−Phase
7
Negative DC−Link Input for U−Phase
8
R
TH
V
TH
Series Resistor for Thermistor (Temperature Detection)
Thermistor Bias Voltage
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
V
Low−Side Bias Voltage for IC and IGBTs Driving
Low−Side Common Supply Ground
CC(L)
COM
(L)
(UL)
IN
IN
Signal Input for High−Side U−Phase
Signal Input for High−Side V−Phase
(VL)
IN
Signal Input for High−Side W−Phase
(WL)
V
Fault Output
FO
C
Capacitor for Fault Output Duration Selection
Capacitor (Low−Pass Filter) for Short−Circuit Current Detection Input
Resistor for Short−Circuit Current Detection
Signal Input for High−Side U Phase
FOD
C
SC
SC
R
IN
(UH)
COM
High−Side Common Supply Ground
(H)
V
High−Side Bias Voltage for U Phase IC
CC(UH)
V
BD(U)
Anode of Bootstrap Diode for U Phase High−Side Bootstrap Circuit
High−Side Bias Voltage for U Phase IGBT Driving
High−Side Bias Voltage Ground for U Phase IGBT Driving
Signal Input for High−Side V Phase
V
B(U)
V
S(U)
IN
(VH)
V
High−Side Bias Voltage for V Phase IC
CC(VH)
V
BD(V)
Anode of Bootstrap Diode for V Phase High−Side Bootstrap Circuit
High−Side Bias Voltage for V Phase IGBT Driving
High−Side Bias Voltage Ground for V Phase IGBT Driving
Signal Input for High−Side W Phase
V
B(V)
S(V)
(WH)
V
IN
V
High−Side Bias Voltage for W Phase IC
CC(WH)
V
BD(W)
Anode of Bootstrap Diode for W Phase High−Side Bootstrap Circuit
High−Side Bias Voltage for W Phase IGBT Driving
High−Side Bias Voltage Ground for W Phase IGBT Driving
V
B(W)
V
S(W)
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3
FNA25012A
INTERNAL EQUIVALENT CIRCUIT AND INPUT/OUTPUT PINS
(1) P
(33) V
B(W)
V
V
OUT
IN
B
(32) V
(31) V
BD(W)
OUT
CC
HVIC
HVIC
HVIC
CC(WH)
V
S
(30) IN
(34) V
(WH)
S(W)
(2) W
(3) V
(28) V
V
B
B(V)
(27) V
(26) V
BD(V)
CC(VH)
OUT
V
OUT
IN
CC
(25) IN
(29) V
V
S
(VH)
S(V)
(23) V
V
B
B(U)
(22) V
(21) V
BD(U)
CC(UH)
(20) COM
OUT
V
OUT
IN
CC
(H)
(UH)
S(U)
V
S
(19) IN
(24) V
(4) U
(17) C
(16) C
SC
C
C
OUT
OUT
OUT
SC
FOD
FOD
(5) N
(6) N
W
(15) V
V
FO
FO
(14) IN
IN
(WL)
LVIC
(13) IN
(12) IN
IN
(VL)
(UL)
V
IN
(11) COM
(10) VCC
COM
(L)
(L)
V
CC
(7) N
U
(8) R
TH
Thermistor
(9) V
TH
(18) R
SC
NOTES:
1. Inverter high−side is composed of three normal−IGBTs, freewheeling diodes, and one control IC for each IGBT.
2. Inverter low−side is composed of three sense−IGBTs, freewheeling diodes, and one control IC for each IGBT. It has gate drive and
protection functions.
3. Inverter power side is composed of four inverter DC−link input terminals and three inverter output terminals.
Figure 3. Internal Block Diagram
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4
FNA25012A
ABSOLUTE MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
INVERTER PART
Symbol
Parameter
Conditions
Applied between P−N , N , N
Rating
900
Unit
V
V
Supply Voltage
PN
PN(Surge)
U
V
W
W
V
Supply Voltage (Surge)
Applied between P−N , N , N
1000
1200
50
V
U
V
V
CES
Collector−Emitter Voltage
V
I
C
Each IGBT Collector Current
Each IGBT Collector Current (Peak)
T
T
= 25°C, T =150°C
(Note 4)
A
C
J
I
= 25°C, T =150°C, Under 1 ms
75
A
CP
C
J
Pulse Width
(Note 4)
P
C
Collector Dissipation
T =25°C per One Chip
C
(Note 4)
347
W
T
J
Operating Junction Temperature
−40∼150
°C
CONTROL PART
Symbol
Parameter
Conditions
Rating
20
Unit
V
V
CC
Control Supply Voltage
Applied between V
, V
−COM
CC(H) CC(L)
V
BS
High−Side Control Bias Voltage
Applied between V
B(V) S(V) B(W) S(W)
−V
,
20
V
B(U) S(U)
V
−V
, V
−V
V
IN
Input Signal Voltage
Applied between IN
, IN
, IN
,
−0.3∼V +0.3
V
(UH)
(VH)
(WH)
CC
IN
, IN
, IN
−COM
(UL)
(VL)
(WL)
V
Fault Output Supply Voltage
Fault Output Current
Applied between V −COM
−0.3∼V +0.3
V
mA
V
FO
FO
CC
I
Sink Current at V pin
2
FO
FO
V
SC
Current Sensing Input Voltage
Applied between C −COM
−0.3∼V +0.3
SC
CC
BOOTSTRAP DIODE PART
Symbol
Parameter
Conditions
Rating
1200
1.0
Unit
V
V
Maximum Repetitive Reverse Voltage
Forward Current
RRM
I
F
T
T
= 25°C, T ≤150°C
(Note 4)
A
C
J
I
FP
Forward Current (Peak)
= 25°C, T =150°C, Under 1 ms
2.0
A
C
J
Pulse Width
(Note 4)
T
J
Operating Junction Temperature
−40∼150
°C
TOTAL SYSTEM
Symbol
Parameter
Conditions
= V = 13.5∼16.5 V, T = 150°C,
Rating
Unit
V
Self Protection Supply Voltage Limit
(Short Circuit Protection Capability)
V
CC
V
800
V
PN(PROT)
BS
J
= < 1200 V, Non−repetitive, < 2 ms
CES
T
Module Case Operation Temperature
Storage Temperature
See Figure 2
−40∼125
−40∼125
2500
°C
°C
C
T
STG
V
ISO
Isolation Voltage
60 Hz, Sinusoidal, AC 1 minute,
Connection Pins to Heat Sink Plate
V
rms
THERMAL RESISTANCE
Symbol
Parameter
Conditions
Min.
−
Typ.
−
Max.
Unit
°C/W
°C/W
R
Junction to Case Thermal
Resistance
Inverter IGBT part (per 1/6 module)
Inverter FWD part (per 1/6 module)
0.36
0.66
th(j−c)Q
(Note 5)
R
−
−
th(j−c)F
4. These values had been made an acquisition by the calculation considered to design factor.
5. For the measurement point of case temperature (T ), please refer to Figure 2.
C
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5
FNA25012A
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
INVERTER PART
Symbol
Parameter
Conditions
= V = 15 = 50 A, T = 25°C
Min.
Typ.
Max.
Unit
V
Collector − Emitter Saturation
V
I
C
−
2.20
2.80
V
CE(SAT)
DD
BS
J
Voltage
V, V = 5 V
IN
V
FWDi Forward Voltage
Switching Times
V
V
= 0 V
I = 50 A, T = 25°C
−
0.90
−
2.40
1.40
0.50
1.10
0.15
0.20
1.00
0.50
1.10
0.15
0.25
−
3.00
2.00
0.95
1.70
0.55
−
V
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
mA
F
IN
F
J
HS
LS
t
= 600 V, V = 15 V, I = 50 A,
PN CC C
ON
T = 25°C
J
t
C(ON)
V
IN
= 0 V ⇔ 5 V, Inductive Load
See Figure 5
(Note 6)
t
−
OFF
t
−
C(OFF)
t
rr
−
t
V
PN
= 600 V, V = 15 V, I = 50 A,
0.50
−
1.60
0.95
1.70
0.55
−
ON
CC
C
T = 25°C
J
t
C(ON)
V
IN
= 0 V ⇔ 5 V, Inductive Load
See Figure 5
(Note 6)
t
−
OFF
t
−
C(OFF)
t
rr
−
I
Collector−Emitter Leakage Current
V
CE
= V
CES
−
5
CES
6. t and t
include the propagation delay time of the internal drive IC. t
and t
are the switching time of IGBT itself under the
C(OFF)
ON
OFF
C(ON)
given gate−driving condition internally. For the detailed information see Figure 4.
100% I
100% I
C
C
t
rr
I
C
I
C
V
CE
V
CE
V
IN
V
IN
t
ON
t
OFF
t
t
c(OFF)
c(ON)
10% I
C
V
IN(ON)
V
IN(OFF)
10% V
10% I
CE
C
90% I 10% V
C
CE
(a) turn − on
(b) turn − off
Figure 4. Switching Time Definition
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6
FNA25012A
One−Leg Diagram of SPM 2
I
C
R
BS
P
C
BS
V
V
B
CC
LS Switching
COM
IN
OUT
V
S
V
PN
HS Switching
LS Switching
U,V,W
V
Inductor
IN
600 V
V
V
C
C
CC
FO
V
IN
HS Switching
OUT
5 V
0 V
4.7 kW
FOD
SC
V
CC
V
COM
N
U,V,W
15 V
V
5 V
R
SC
Figure 5. Example Circuit for Switching Test
INDUCTIVE LOAD, V = 600 V, V = 15 V, T = 255C
INDUCTIVE LOAD, V = 600 V, V = 15 V, T = 1505C
CC J
PN
CC
J
PN
14400
12800
14400
12800
IGBT Turn−ON, E
IGBT Turn−ON, E
on
on
IGBT Turn−OFF, E
IGBT Turn−OFF, E
off
off
11200
9600
11200
9600
FRD Turn−OFF, E
FRD Turn−OFF, E
rec
rec
8000
6400
8000
6400
4800
4800
3200
1600
3200
1600
0
0
0
4
8
12 16 20 24 28 32 36 40 44 48 52 56
0
4
8
12 16 20 24 28 32 36 40 44 48 52 56
Collector Current, I [A]
Collector Current, I [A]
C
C
Figure 6. Switching Loss Characteristics (Typical)
600
550
R−T CURVE IN 505C ꢀ 1255C
20
500
16
450
400
12
8
350
300
250
4
0
200
150
100
50
50
60
70
80
90
100 110 120
Temperature [5C]
0
−20 −10
0
10
20
30 40
50 60
70 80
90 100 110 120
Temperature, T [5C]
TH
Figure 7. R−T Curve of Built−in Thermistor
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FNA25012A
BOOTSTRAP DIODE PART
Symbol
Parameter
Conditions
Min.
−
Typ.
2.2
80
Max.
Unit
V
V
F
Forward Voltage
I = 1.0 A, T = 25°C
−
−
F
J
t
rr
Reverse−Recovery Time
I = 1.0 A, dl /dt = 50 A, T = 25°C
−
ns
F
F
J
CONTROL PART (T = 25°C)
J
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
I
Quiescent V Supply Cur-
V
= 15 V,
V
V
V
−COM
−COM
−
−
0.15
mA
QCCH
CC
CC(UH,VH.WH)
(UH,VH.WH)
CC(UH)
CC(VH)
CC(WH)
(H),
(H),
(H)
rent
IN
= 0 V
−COM
I
V
= 15 V,
(UH,VH.WH)
V
− COM
(L)
−
−
−
−
5.00
0.30
mA
mA
QCCL
CC(L)
CC(L)
IN
= 0 V
I
Operating V Supply Current
V
= 15 V, f
=
V
V
V
−COM
−COM
PDDH
DD
CC(UH,VH.WH)
PWM
CC(UH)
CC(VH)
CC(WH)
(H),
(H),
20 kHz, Duty = 50%, Applied
to one PWM Signal Input for
High−Side
−COM
(H)
I
V
= 15 V, f
= 20 kHz,
V
CC(L)
− COM
(L)
−
−
15.5
mA
PDDL
CC(L)
PWM
Duty = 50%, Applied to one
PWM Signal Input for Low−
Side
I
Quiescent V Supply Current
V
= 15 V,
(UH,VH.WH)
V
V
V
− V
S(V)
− V
,
−
−
−
−
0.30
12.0
mA
mA
QBS
BS
BS
IN
B(U)
B(V)
B(W)
S(U)
= 0 V
− V
,
,
S(W)
I
Operating V Supply Current
V
PWM
= V = 15 V,
V
B(U)
V
B(V)
V
B(W)
− V
− V
,
,
PBS
BS
CC
BS
S(U)
S(V)
− V
f
= 20 kHz, Duty = 50%,
Applied to one PWM Signal
Input for High−Side
,
S(W)
V
Fault Output Voltage
V
= 15 V, V = 0 V, V Circuit: 4.7 kW to 5 V
4.5
−
−
−
V
V
FOH
CC
SC
FO
Pull−up
V
V
CC
= 15 V, V = 1 V, V Circuit: 4.7 kW to 5 V
−
0.5
FOL
SC
FO
Pull−up
V
Short Circuit Trip Level
V
= 15 V
(Note 7)
C
− COM
(L)
0.43
10.3
10.8
9.5
10.0
50
0.50
−
0.57
12.8
13.3
12.0
12.5
−
V
V
SC(ref)
CC
SC
UV
Supply Circuit Under−Voltage
Protection
Detection Level
Reset Level
CCD
CCR
BSD
BSR
UV
UV
UV
t
−
V
Detection Level
Reset Level
−
V
−
V
Fault−Out Pulse Width
C
C
= Open
(Note 8)
−
ms
ms
V
FOD
FOD
FOD
= 2.2 nF
1.7
−
−
−
V
ON Threshold Voltage
OFF Threshold Voltage
Resistance of Thermistor
Applied between IN
IN
− COM ,
(H)
−
2.6
−
IN(ON)
(UH,VH.WH)
− COM
(L)
(UL,VL.WL)
V
0.8
−
−
V
IN(OFF)
R
TH
at T = 25°C
See Figure 7
(Note 9)
47
2.9
−
kW
kW
TH
at T = 100°C
−
−
TH
7. Short−circuit current protection os functioning only at the low−sides because the sense current is divided from main current at low−side
IGBTs. Inserting the shunt resistor for monitoring the phase current at N , N , N terminal, the trip level of the short−circuit current is changed.
U
V
FOD
W
8. The fault−out pulse width t
depends on the capacitance value of C
according to the following approximate equation :
FOD
[s].
6
t
= 0.8 x 10 x C
FOD
FOD
9. T is the temperature of thermistor itself. To know case temperature (T ), conduct experiments considering the application.
TH
C
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FNA25012A
RECOMMENDED OPERATING CONDITIONS
Value
Typ.
600
Min.
300
Max.
800
Symbol
Parameter
Supply Voltage
Conditions
Unit
V
V
Applied between P − N , N , N
U V W
PN
CC
V
Control Supply Voltage
High−Side Bias Voltage
Control Supply Variation
Applied between V
− COM
,
14.0
15.0
16.5
V
CC(UH,VH,WH)
(H)
V
− COM
CC(L)
(L)
V
BS
Applied between V
− V , V
S(U) B(V)
− V ,
S(V)
13.0
−1
15.0
−
18.5
1
V
V/ms
ms
B(U)
V
B(W)
− V
S(W)
dV /dt,
DD
dV /dt,
BS
t
Blanking Time for Preventing
Arm−Short
For Each Input Signal
−40°C ≤ T ≤ 125°C, −40°C ≤ T ≤ 150°C
2.0
−
−
dead
f
PWM Input Signal
−
−
−
20
5
kHz
V
PWM
C
J
V
SEN
Voltage for Current Sensing
Applied between N , N , N − COM
(H,L)
−5
U
V
W
(Including Surge Voltage)
PW
PW
Minimum Input Pulse Width
V
= V = 15 V, I ≤ 75 A, Wiring Inductance
2.5
2.5
−40
−
−
−
−
−
ms
°C
IN(ON)
CC
BS
C
between N , , and DC Link N < 10 nH
U V W
(Note 10)
IN(OFF)
T
Junction Temperature
150
J
10.This product might not make response if input pulse width is less than the recommended value.
44
40
36
f
= 5 kHz
SW
32
28
24
20
f
= 15 kHz
SW
16
12
V
= 600 V, V = V = 15 V
CC BS
DC
8
4
0
T
J
≤ 150°C, T ≤ 125°C
C
M.I. = 0.9, P.F. = 0.8
Sinusoidal PWM
0
10
20 30
40
50 60
70 80
90 100 110 120 130 140
Case Temperature, T [5C]
C
Figure 8. Allowable Maximum Output Current
NOTE:
11. This allowable output current value is the reference data for the safe operation of this product. This may be different from the actual application
and operating condition.
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9
FNA25012A
MECHANICAL CHARACTERISTICS AND RATINGS
Min.
Typ.
Max.
0
Device Flatness
Mounting Torque
See Figure 9
−
1.0
10.1
−
+200
1.5
15.1
−
mm
N•m
kg•cm
s
Mounting Screw: M4
See Figure 10
Recommended 1.0 N•m
0.9
9.1
10
2
Recommended 10.1 kg•cm
Terminal Pulling Strength
Terminal Bending Strength
Weight
Load 19.6 N
Load 9.8 N, 90 degrees Bend
−
−
times
g
−
50
−
Figure 9. Flatness Measurement Position
Pre−Screwing: 1 → 2
Final Screwing: 2 → 1
2
1
Figure 10. Mounting Screws Torque Order
NOTES:
12.Do not make over torque when mounting screws. Much mounting torque may cause DBC cracks, as well as bolts and Al heat−sink
destruction.
13.Avoid one−sided tightening stress. Figure 10 shows the recommended torque order for mounting screws. Uneven mounting can cause the
DBC substrate of package to be damaged. The pre−screwing torque is set to 20 ∼ 30% of maximum torque rating.
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10
FNA25012A
Input signal
Protection
Circuit State
RESET
a1
SET
RESET
UV
DDR
a6
Control
Supply Voltage
UV
CCD
a3
a4
a2
a7
Output Current
a5
Fault Output Signal
a1: Control supply voltage rises: After the voltage rises UV
a2: Normal operation: IGBT ON and carrying current.
, the circuits start to operate when next input is applied.
CCR
a3: Under voltage detection (UV
).
CCD
a4: IGBT OFF in spite of control input condition.
a5: Fault output operation starts with a fixed pulse width according to the condition of the external capacitor C
.
FOD
a6: Under−voltage reset (UV
).
CCR
a7: Normal operation: IGBT ON and carrying current by triggering next signal from LOW to HIGH.
Figure 11. Under−Voltage Protection (Low−Side)
Input signal
Protection
RESET
b1
SET
RESET
Circuit State
UV
BSR
b5
Control
Supply Voltage
UV
BSD
b3
b4
b6
b2
Output Current
High−level (no fault output)
Fault Output Signal
b1: Control supply voltage rises: After the voltage rises UV
b2: Normal operation: IGBT ON and carrying current.
, the circuits start to operate when next input is applied.
BSR
b3: Under voltage detection (UV
).
BSD
b4: IGBT OFF in spite of control input condition, but there is no fault output signal.
b5: Under voltage reset (UV ).
BSR
b6: Normal operation: IGBT ON and carrying current by triggering next signal from LOW to HIGH.
Figure 12. Under−Voltage Protection (High−Side)
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11
FNA25012A
Lower Arms
Control Input
c6
c7
Protection
Circuit State
SET
RESET
c4
c3
Internal IGBT
Gate−Emitter Voltage
c2
Internal delay
at protection circuit
SC current trip level
c8
c1
Output Current
SC reference voltage
Sensing Voltage
of Sense Resistor
RC filter circuit
time constant
delay
Fault Output Signal
c5
(with the external sense resistance and RC filter connection)
c1: Normal operation: IGBT ON and carrying current.
c2: Short circuit current detection (SC trigger).
c3: All low−side IGBTs gate are hard interrupted.
c4: All low−side IGBTs turn OFF.
c5: Fault output operation starts with a fixed pulse width according to the condition of the external capacitor C
c6: Input HIGH: IGBT ON state, but during the active period of fault output the IGBT doesn’t turn ON.
.
FOD
c7: Fault output operation finishes, but IGBT doesn’t turn on until triggering the next signal from LOW to HIGH.
c8: Normal operation: IGBT ON and carrying current.
Figure 13. Short−Circuit Current Protection (Low−Side Operation Only)
INPUT/OUTPUT INTERFACE CIRCUIT
+5V (MCU or Control power)
4.7 kΩ
ASPM
IN
IN
, IN
, IN
(UH)
(VH)
(WH)
, IN
(VL)
, IN
(WL)
(UL)
MCU
VFO
COM
NOTE:
14.RC coupling at each input might change depending on the PWM control scheme used in the application and the wiring impedance
of the application’s printed circuit board. The input signal section of the ASPM27 product integrates 5kW (typ.) pull−down resistor.
Therefore, when using an external filtering resistor, please pay attention to the signal voltage drop at input terminal.
Figure 14. Recommended CPU I/O Interface Circuit
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12
FNA25012A
P (1)
R
R
R
1
1
1
(30) IN
(WH)
Gating WH
Gating VH
Gating UH
IN
(31) V
CC(WH)
V
CC
C
4
(32) V
OUT
R
R
R
BD(W)
COM
2
HVIC
HVIC
(33) V
(34) V
B(W)
V
B
V
S
W (2)
S(W)
C
C
C
3
4
(25) IN
(VH)
IN
(26) V
CC(VH)
V
CC
C
C
4
OUT
(27) V
COM
BD(V)
2
(28) V
(29) V
B(V)
V
B
V
S
V (3)
S(V)
3
4
M
(19) IN
(21) V
(UH)
IN
C
V
DC
7
CC(UH)
V
CC
C
(20) COM
4
4
(H)
COM
OUT
M
C
U
(22) V
2
HVIC
BD(U)
C
C
C
1
1
1
(23) V
(24) V
B(U)
V
B
V
S
U (4)
S(U)
C
C
3
5 V line
R
3
C
5
R
1
OUT
OUT
OUT
(16) C
(15) V
FOD
Fault
C
FOD
A
R
4
4
N
(5)
FO
W
V
FO
R
R
1
1
(14) IN
(13) IN
(12) IN
(WL)
Gating WL
Gating VL
Gating UL
IN
IN
IN
(VL)
LVIC
R
1
(UL)
R
E
N
(6)
(7)
V
15 V line
(10) V
CC(L)
V
CC
Shunt
Resistor
C
C
C
1
1
1
Power
GND Line
(11) COM
(L)
C
C
4
2
COM
5 V line
(9) V
TH
R
4
N
C
U
(8) R
TH
SC
Temp.
Monitoring
R
Thermistor
5
R
(18)
SC
R
7
Sense
(17) C
SC
Resistor
D
B
C
R
6
W−Phase Current
V−Phase Current
U−Phase Current
Control
GND Line
C
6
NOTES:
15.To avoid malfunction, the wiring of each input should be as short as possible. (less than 2−3 cm)
16.V output is open−drain type. The signal line should be pulled up to the positive side of the MCU or control power supply with a resistor
FO
that makes I up to 2 mA. Please refer to Figure 14.
FO
17.Fault out pulse width can be adjust by capacitor C connected to the C
terminal.
5
FOD
18.Input signal is active−HIGH type. There is a 5 W resistor inside the IC to pull−down each input signal line to GND. RC coupling circuits
should be adopted for the prevention of input signal oscillation. R C time constant should be selected in the range 50 ∼ 150 ns
1
1
(recommended R = 100 W, C = 1 nF).
1
1
19.Each wiring pattern inductance of point A should be minimized (recommended less than 10 nH). Use the shunt resistor R of surface
4
mounted (SMD) type to reduce wiring inductance. To prevent malfunction, wiring of point E should be connected to the terminal of the
shunt resistor R as close as possible.
4
20.To insert the shunt resistor to measure each phase current at N , N , N terminal, it makes to change the trip level I about
U
V
W
SC
the short −circuit current.
21.To prevent errors of the protection function, the wiring of B, C and D point should be as short as possible. The wiring of B between C
SC
filter and R terminal should be divided at the point that is close to the terminal of sense resistor R .
SC
5
22.For stable protection function, use the sense resistor R with resistance variation within 1% and low inductance value.
5
23.In the short−circuit protection circuit, select the R C time constant in the range 1.0 ∼ 1.5 ms. R should be selected with a minimum of
6
6
6
10 times larger resistance than sense resistor R . Do enough evaluation on the real system because short−circuit protection time may
5
vary wiring pattern layout and value of the R C time constant.
6
6
ꢀ
24.Each capacitor should be mounted as close to the pins of the Motion SPM 2 product as possible.
25.To prevent surge destruction, the wiring between the smoothing capacitor C and the P & GND pins should be as short as possible. The
7
use of a high−frequency non−inductive capacitor of around 0.1 ∼ 0.22 mF between the P & GND pins is recommended.
26.Relays are used in most systems of electrical equipment at industrial application. In these cases, there should be sufficient distance be-
tween the MCU and the relays.
27.The Zener diode or transient voltage suppressor should be adopted for the protection of ICs from the surge destruction between each
pair of control supply terminals (recommended Zener diode is 22 V/1 W. which has the lower Zener impedance characteristic than
about 15 W).
28.C of around seven times larger than bootstrap capacitor C is recommended.
2
3
29.Please choose the electrolytic capacitor with good temperature characteristic in C . Choose 0.1 ∼ 0.2 mF R−category ceramic capacitors
3
with good temperature and frequency characteristics in C .
4
Figure 15. Typical Application Circuit
SPM is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or
other countries.
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13
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SPMCA−A34 / 34LD, PDD STD, DBC DIP TYPE
CASE MODFQ
ISSUE O
DATE 31 JAN 2017
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13565G
SPMCA−A34 / 34LD, PDD STD, DBC DIP TYPE
PAGE 1 OF 1
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