FNA41560T2 [ONSEMI]
智能功率模块 (IPM)，600V，15A;
| 型号： | FNA41560T2 |
| 厂家： | 
ONSEMI |
| 描述： | 智能功率模块 (IPM)，600V，15A 局域网 电动机控制 |
| 文件： | 总16页 (文件大小：720K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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Motion SPM) 45 Series
FNA41560T2
General Description
FNA41560T2 is a Motion SPM 45 module providing
a fully−featured, high−performance inverter output stage for AC
Induction, BLDC, and PMSM motors. These modules integrate
optimized gate drive of the built−in IGBTs to minimize EMI
and losses, while also providing multiple on−module protection
features including under−voltage lockouts, over−current shutdown,
thermal monitoring of drive IC, and fault reporting. The built−in,
high−speed HVIC requires only a single supply voltage and translates
the incoming logic−level gate inputs to the high−voltage, high−current
drive signals required to properly drive the module’s internal IGBTs.
Separate negative IGBT terminals are available for each phase
to support the widest variety of control algorithms.
3D Package Drawing (Click to Activate 3D Content)
SPMAA−C26 / 26LD, PDD STD CERAMIC TYPE,
LONG LEAD DUAL FORM TYPE
CASE MODFC
Features
• UL Certified No. E209204 (UL1557)
MARKING DIAGRAM
• 600 V − 15 A 3−Phase IGBT Inverter with Integral Gate Drives
and Protection
• Low Thermal Resistance Using Ceramic Substrate
26
10
• Low−Loss, Short−Circuit−Rated IGBTs
• Built−In Bootstrap Diodes and Dedicated Vs Pins Simplify PCB
Layout
$Y
FNA41560T2
XXX
YWW
• Built−In NTC Thermistor for Temperature Monitoring
9
1
• Separate Open−Emitter Pins from Low−Side IGBTs for Three−Phase
Current Sensing
$Y
= onsemi Logo
• Single−Grounded Power Supply
FNA41560T2 = Specific Device Code
XXX
Y
= Trace Code
= Year
= Work Week
• Isolation Rating of 2000 Vrms / 1 min.
• This is a Pb−Free and Halogen Free/BFR Free Device
WW
Applications
• Motion Control − Home Appliance / Industrial Motor
ORDERING INFORMATION
See detailed ordering and shipping information on page 14 of
this data sheet.
Related Resources
®
• AN−9084 − Smart Power Module, Motion SPM 45 H V3 Series
User’s Guilde
®
• AN−9072 − Smart Power Module Motion SPM in SPM45H
Thermal Performance Information
®
• AN−9071 − Smart Power Module Motion SPM in SPM45H
Mounting Guidance
®
• AN−9760 − PCB Design Guidance for SPM
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
October, 2021 − Rev. 2
FNA41560T2/D
FNA41560T2
Integrated Power Functions
• 600 V − 15 A IGBT inverter for three−phase DC / AC
power conversion (refer to Figure 2)
Integrated Drive, Protection, and System Control Functions
• For inverter high−side IGBTs:
• Fault signaling:
gate−drive circuit, high−voltage isolated high−speed
level−shifting control circuit,
corresponding to UVLO (low−side supply)
and SC faults
Under−Voltage Lock−Out Protection (UVLO)
• Input interface:
active−HIGH interface, works with 3.3 / 5 V logic,
Schmitt−trigger input
NOTE: Available bootstrap circuit example is given in
Figures 14
• For inverter low−side IGBTs:
gate−drive circuit, Short−Circuit Protection (SCP)
control supply circuit,
Under−Voltage Lock−Out Protection (UVLO)
Pin Configuration
Figure 1. Top View
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FNA41560T2
PIN DESCRIPTIONS
Pin No.
Pin Name
Pin Description
1
2
3
4
5
6
7
V
R
Thermistor Bias Voltage
TH
TH
Series Resistor for the Use of Thermistor (Temperature Detection)
Positive DC−Link Input
P
U
V
Output for U−Phase
Output for V−Phase
W
Output for W−Phase
N
Negative DC−Link Input for U−Phase
U
8
9
N
Negative DC−Link Input for V−Phase
Negative DC−Link Input for W−Phase
V
N
W
10
11
12
Shut Down Input for Short−circuit Current Detection Input
Fault Output
C
V
SC
FO
IN(WL)
IN(VL)
IN(UL)
COM
Signal Input for Low−Side W−Phase
13
14
15
16
17
18
Signal Input for Low−Side V−Phase
Signal Input for Low−Side U−Phase
Common Supply Ground
Low−Side Common Bias Voltage for IC and IGBTs Driving
High−Side Common Bias Voltage for IC and IGBTs Driving
Signal Input for High−Side W−Phase
V
DD(L)
DD(H)
V
IN
(WH)
19
20
21
Signal Input for High−Side V−Phase
IN(VH)
IN
(UH)
Signal Input for High−Side U−Phase
VS
VB
High−Side Bias Voltage Ground for W−Phase IGBT Driving
(W)
(W)
22
23
24
25
26
High−Side Bias Voltage for W−Phase IGBT Driving
High−Side Bias Voltage Ground for V−Phase IGBT Driving
High−Side Bias Voltage for V−Phase IGBT Driving
High−Side Bias Voltage Ground for U−Phase IGBT Driving
High−Side Bias Voltage for U−Phase IGBT Driving
VS
VB
VS
VB
(V)
(V)
(U)
(U)
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FNA41560T2
Internal Equivalent Circuit and Input/Output Pins
VTH (1)
RTH (2)
P (3)
Thermistor
(26) VB(U)
UVB
(25) VS(U)
UVS
OUT(UH)
UVS
(24) VB(V)
(23) VS(V)
U(4)
VVB
VVS
(22) VB(W)
(21) VS(W)
WVB
WVS
OUT(VH)
(20) IN(UH)
(19) IN(VH)
VVS
IN(UH)
IN(VH)
V (5)
(18) IN(WH)
(17) VDD(H)
IN(WH)
VDD
OUT(WH)
WVS
COM
W(6)
(16) VDD(L)
(15) COM
VDD
OUT(UL)
OUT(VL)
COM
NU (7)
(14) IN(UL)
(13) IN(VL)
IN(UL)
IN(VL)
IN(WL)
(12) IN(WL)
(11) VFO
N
V (8)
VFO
CSC
(10) CSC
OUT(WL)
NW (9)
NOTES:
1. Inverter high−side is composed of three normal−IGBTs, freewheeling diodes, and one control IC for each IGBT.
2. Inverter low−side is composed of three sense−IGBTs, freewheeling diodes, and one control IC for each IGBT.
It has gate drive and protection functions.
3. Inverter power side is composed of four inverter DC−link input terminals and three inverter output terminals.
Figure 2. Internal Block Diagram
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FNA41560T2
ABSOLUTE MAXIMUM RATINGS (T = 25°C, unless otherwise specified)
J
Symbol
Parameter
Conditions
Rating
Unit
INVERTER PART
V
Supply Voltage
Applied between P − N , N , N
450
500
600
15
V
V
V
A
A
PN
PN(Surge)
U
V
W
V
Supply Voltage (Surge)
Applied between P − N , N , N
U V
W
V
CES
Collector − Emitter Voltage
Each IGBT Collector Current
Each IGBT Collector Current (Peak)
I
C
T
T
= 25°C, T < 150°C
J
C
I
= 25°C, T < 150°C,
30
CP
C
J
Under 1 ms Pulse Width (Note 4)
P
C
Collector Dissipation
T
C
= 25°C per One Chip (Note 4)
38
W
T
J
Operating Junction Temperature
−40 ∼ 150
°C
CONTROL PART
V
Control Supply Voltage
Applied between V
, V − COM
DD(H) DD(L)
20
20
V
V
DD
V
High−Side Control Bias Voltage
Applied between V
− V
,
BS
B(U)
S(U)
V
S(W)
−
V
− V
, V
B(V)
S(V) B(W)
V
IN
Input Signal Voltage
Applied between IN
, IN
, IN
,
−0.3 ∼ V + 0.3
V
(UH)
(VH)
(WH)
DD
IN
, IN
, IN
− COM
(UL)
(VL)
(WL)
V
Fault Output Supply Voltage
Fault Output Current
Applied between V − COM
−0.3 ∼ V + 0.3
V
mA
V
FO
FO
DD
I
Sink Current at V pin
1
FO
FO
V
SC
Current−Sensing Input Voltage
Applied between C − COM
−0.3 ∼ V + 0.3
SC
DD
BOOTSTRAP DIODE PART
V
Maximum Repetitive Reverse Voltage
Forward Current
600
0.5
2.0
V
A
A
RRM
I
F
T
T
= 25°C, T < 150°C
J
C
I
Forward Current (Peak)
= 25°C, T < 150°C,
J
Under 1 ms Pulse Width (Note 4)
FP
C
T
J
Operating Junction Temperature
−40 ∼ 150
°C
TOTAL SYSTEM
V
Self−Protection Supply Voltage Limit
(Short−Circuit Protection Capability)
V
= V = 13.5 ∼ 16.5 V, T = 150°C,
400
V
PN(PROT)
DD
BS
J
Non−Repetitive, < 2 ms
T
Module Case Operation Temperature
Storage Temperature
See Figure 1
−40 ∼ 125
−40 ∼ 125
2000
°C
°C
C
T
STG
V
ISO
Isolation Voltage
60 Hz, Sinusoidal, AC 1 Minute,
Connect Pins to Heat Sink Plate
Vrms
THERMAL RESISTANCE
Symbol
Parameter
Conditions
Min.
Typ.
−
Max.
Unit
°C/W
°C/W
R
Junction to Case Thermal Resistance Inverter IGBT Part (per 1 / 6 Module)
(Note 5)
−
−
3.20
4.00
th(j−c)Q
R
Inverter FWDi Part (per 1 / 6 Module)
−
th(j−c)F
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
4. These values had been made an acquisition by the calculation considered to design factor.
5. For the measurement point of case temperature (T ), please refer to Figure 1.
C
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5
FNA41560T2
ELECTRICAL CHARACTERISTICS (T = 25°C, unless otherwise specified)
J
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
INVERTER PART
V
Collector − Emitter Saturation
V
V
= V = 15 V
I = 15 A,
C
J
−
−
1.60
2.00
2.20
2.60
V
V
CE(SAT)
DD
IN
BS
Voltage
= 5 V
T = 25°C
V
F
FWDi Forward Voltage
Switching Times
V
IN
= 0 V
I = 15 A,
F
T = 25°C
J
t
V
PN
= 300 V, V = V = 15 V, I = 15 A
DD BS C
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
mA
HS
0.40
−
0.80
0.20
0.85
0.25
0.10
0.85
0.25
0.90
0.25
0.15
−
1.30
0.50
1.35
0.55
−
ON
T = 25°C
J
t
V
IN
= 0 V ↔ 5 V, Inductive Load
C(ON)
(Note 6)
t
−
OFF
−
t
C(OFF)
t
rr
−
V
PN
= 300 V, V = V = 15 V, I = 15 A
DD BS C
LS
t
0.45
−
1.35
0.55
1.40
0.55
−
ON
T = 25°C
J
t
V
IN
= 0 V ↔ 5 V, Inductive Load
C(ON)
(Note 6)
t
−
OFF
t
−
C(OFF)
−
t
rr
I
Collector − Emitter Leakage
Current
V
= V
−
1
CES
CE CES
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. t and t
include the propagation delay of the internal drive IC. t
and t
are the switching times of IGBT under the given gate
ON
OFF
C(ON)
C(OFF)
driving condition internally. For the detailed information, please see Figure 3.
Figure 3. Switching Time Definition
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FNA41560T2
Inductive Load, V = 300 V, V = 15 V, T = 150°C
Inductive Load, V = 300 V, V = 15 V, T = 25°C
PN
DD
J
PN
DD
J
IGBT Turn−on, Eon
IGBT Turn−off, Eoff
FRD Turn−off, Erec
IGBT Turn−on, Eon
IGBT Turn−off, Eoff
FRD Turn−off, Erec
1400
1200
1000
800
600
400
200
0
1400
1200
1000
800
600
400
200
0
0
5
10
15
0
5
10
15
I , Collector Current (A)
C
I , Collector Current (A)
C
Figure 4. Switching Loss Characteristics (Typical)
CONTROL PART
Symbol
Parameter
Conditions
= 0 V
Min.
Typ.
−
Max.
0.10
2.65
0.15
Unit
mA
mA
mA
I
Quiescent V Supply Current
V
V
V
= 15 V, IN
= 15 V, IN
= 15 V,
V
DD(H)
V
DD(L)
V
DD(H)
− COM
− COM
− COM
−
−
−
QDDH
DD
DD(H)
DD(L)
DD(H)
(UH,VH, WH)
I
= 0 V
(UL,VL, WL)
−
QDDL
PDDH
I
Operating V Supply Current
−
DD
f
= 20 kHz, Duty = 50%,
Applied to one PWM Signal
PWM
Input for High−Side
I
V
PWM
= 15V,
V
DD(L)
− COM
−
−
4.00
mA
PDDL
DD(L)
f
= 20 kHz, Duty = 50%,
Applied to one PWM Signal
Input for Low−Side
I
Quiescent V Supply Current
V
= 15 V, IN
= 0 V
V
V
V
− V
,
,
−
−
−
−
0.30
2.00
mA
mA
QBS
BS
BS
(UH, VH, WH)
B(U)
B(V)
B(W)
S(U)
− V
S(V)
− V
S(W)
I
Operating V Supply Current
V
PWM
= V = 15 V,
V
B(U)
V
B(V)
V
B(W)
− V
− V
,
,
PBS
BS
DD
BS
S(U)
f
= 20 kHz,
S(V)
Duty = 50%, Applied to one PWM
Signal Input for High−Side
− V
S(W)
V
Fault Output Voltage
V
V
V
= 0 V, V Circuit: 4.7 kΩ to 5 V Pull−up
4.5
−
−
−
−
0.5
0.55
13.0
13.5
12.5
13.0
−
V
V
FOH
SC
SC
DD
FO
V
= 1 V, V Circuit: 4.7 kΩ to 5 V Pull−up
FO
FOL
V
SC(ref)
Short Circuit Trip Level
= 15 V (Note 7)
C
− COM
SC
0.45
10.5
11.0
10.0
10.5
30
0.50
−
V
UV
Supply Circuit Under− Voltage
Protection
Detection Level
Reset Level
V
DDD
DDR
BSD
BSR
UV
UV
UV
−
V
Detection Level
Reset Level
−
V
−
V
t
Fault−Out Pulse Width
ON Threshold Voltage
OFF Threshold Voltage
Resistance of Thermistor
−
ms
V
FOD
V
IN(ON)
Applied between IN
IN
− COM,
−
−
2.6
−
(UH, VH, WH)
− COM
(UL, VL, WL)
V
0.8
−
−
V
IN(OFF)
R
at T = 25°C (Note 8)
47
2.9
−
kW
kW
TH
TH
at T = 100°C
−
−
TH
7. Short−circuit current protection is functioning only at the low−sides.
8. T is the temperature of thermistor itselt. To know case temperature (T ), please make the experiment considering your application.
TH
C
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FNA41560T2
R−T Curve
600
550
500
450
400
350
300
250
200
150
100
50
R−T Curve in 50°C ~ 125°C
20
16
12
8
4
0
50 60 70 80 90 100 110 120
Temperature (°C)
0
−20 −10
0
10 20 30 40 50 60 70 80 90 100 110 120
T
TH
, Temperature (°C)
Figure 5. R−T Curve of The Built−In Thermistor
BOOTSTRAP DIODE PART
Symbol
Parameter
Conditions
I = 0.1 A, T = 25°C
Min.
−
Typ.
2.5
80
Max.
Unit
V
V
F
Forward Voltage
−
−
F
C
t
rr
Reverse−Recovery Time
I = 0.1 A, dI / dt = 50 A / μs,
−
ns
F
J
F
T = 25°C
Built−In Bootstrap Diode V − I Characteristic
F
F
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
T
= 25°C
C
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
V
F
(V)
NOTE: Built−in bootstrap diode includes around 15 W resistance characteristic.
Figure 6. Built−In Bootstrap Diode Characteristic
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FNA41560T2
RECOMMENDED OPERATING CONDITIONS
Value
Typ.
300
Min.
−
Max.
400
Symbol
Parameter
Supply Voltage
Conditions
Unit
V
V
PN
DD
Applied between P − N , N , N
U V W
V
Control Supply Voltage
Applied between V
COM
V
−
13.5
15.0
16.5
V
DD(H), DD(L)
V
BS
High−Side Bias Voltage
Applied between V
− V ,
S(U)
13.0
15.0
18.5
V
B(U)
V
V
− V
, V
− S(W)
B(V)
S(V) B(W)
dV / dt, dV / dt Control Supply Variation
−1
−
−
1
V / ms
ms
DD
BS
t
Blanking Time for Preventing
Arm − Short
For each input signal
1
−
dead
f
PWM Input Signal
−40_C ≤ T ≤ 125_C,
−
−
−
20
4
kHz
V
PWM
C
−40_C ≤ T ≤ 150_C
J
V
Voltage for Current Sensing
Applied between N , N , N − COM
−4
SEN
U
V
W
(Including Surge−Voltage)
PW
PW
Minimun Input Pulse Width
Minimun Input Pulse Width
Junction Temperature
V
= V = 15 V, I ≤ 15 A,
0.5
0.5
1.2
1.2
−40
−
−
−
−
−
−
−
ms
ms
_C
IN(ON)
DD
BS
C
Wiring Inductance between N
U, V, W
and DC Link N < 10 nH (Note 9)
IN(OFF)
PW
V
DD
= V = 15 V, I ≤ 30 A,
−
IN(ON)
BS
C
Wiring Inductance between N
U, V, W
PW
−
and DC Link N < 10 nH (Note 9)
IN(OFF)
T
150
J
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
9. This product might not make right output response if input pulse width is less than the recommanded value.
15
12
fSW = 5 kHz
9
6
V
DC = 300 V, VDD = VBS = 15 V
fSW = 15 kHz
Tj
= 150°C, T = 125°C
C
3
0
M.I. = 0.9, P.F. = 0.8
Sinusoidal PWM
0
20
40
60
80
100
120
140
T , Case Temperature (°C)
C
NOTE: This allowable output current value is the reference data for the safe operation of this product. This may be different
from the actual application and operating condition.
Figure 7. Allowable Maximum Output Current
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FNA41560T2
MECHANICAL CHARACTERISTICS AND RATINGS
Parameter
Conditions
Min.
Typ.
Max.
Unit
mm
Device Flatness
See Figure 8
0
−
+120
0.8
Mounting Torque
Weight
Mounting Screw: M3
See Figure 9
Recommended 0.7 N/m
Recommended 7.1 kg/cm
0.6
6.2
0.7
7.1
N/m
8.1
kg/cm
−
11.00
−
g
Figure 8. Flatness Measurement Position
Figure 9. Mounting Screws Torque Order
NOTES:
10.Do not make over torque when mounting screws. Much mounting torque may cause ceramic cracks, as well as bolts and Al heat−sink
destruction.
11. Avoid one−sided tightening stress. Figure 9 shows the recommended torque order for the mounting screws. Uneven mounting can cause
the ceramic substrate damaged. The pre−screwing torque is set to 20 ∼ 30% of maximum torque rating.
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FNA41560T2
Time Charts of Protective Function
Input Signal
Protection
SET
RESET
b1
RESET
Circuit State
UV
DDR
a6
UV
a2
DDD
Control
a3
a4
Supply Voltage
a7
Output Current
a5
Fault Output Signal
a1 : Control supply voltage rises: after the voltage rises UVDDR, the circuits start to operate when the next input is applied.
a2 : Normal operation: IGBT ON and carrying current.
a3 : Under−voltage detection (UVDDD).
a4 : IGBT OFF in spite of control input condition.
a5 : Fault output operation starts with a fixed pulse width.
a6 : Under−voltage reset (UVDDR).
a7 : Normal operation: IGBT ON and carrying current by triggering next signal from LOW to HIGH.
Figure 10. Under−Voltage Protection (Low−Side)
Input Signal
Protection
RESET
b1
SET
RESET
Circuit State
b5
Control
b3
b4
Supply Voltage
b6
b2
Output Current
High−level (no fault output )
Fault Output Signal
b1 : Control supply voltage rises: after the voltage reaches UVBSR, the circuits start to operate when the next input is applied.
b2 : Normal operation: IGBT ON and carrying current.
b3 : Under−voltage detection (UVBSD).
b4 : IGBT OFF in spite of control input condition, but there is no fault output signal.
b5 : Under−voltage reset (UVBSR).
b6 : Normal operation: IGBT ON and carrying current by triggering next signal from LOW to HIGH.
Figure 11. Under−Voltage Protection (High−Side)
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FNA41560T2
Lower Arms
Control Input
c6
c7
Protection
Circuit state
SET
RESET
Internal IGBT
Gate−Emitter Voltage
c4
c3
c2
SC
c1
c8
Output Current
SC Reference
Voltage
Sensing Voltage
of Sense Resistor
CR Circuit Time
Constant Delay
Fault Output Signal
c5
(with the external sense resistance and RC filter connection)
c1 : Normal operation: IGBT ON and carrying current.
c2 : Short−circuit current detection (SC trigger).
c3 : All low−side IGBTs gate are hard interrupted.
c4 : All low−side IGBTs turn OFF.
c5 : Fault output operation starts with a fixed pulse width according to the condition of the external capacitor CFOD.
c6 : Input HIGH: IGBT ON state, but during the active period of fault output, the IGBT doesn’t turn ON.
c7 : Fault output operation finishes, but IGBT doesn’t turn on until triggering the next signal from LOW to HIGH.
c8 : Normal operation: IGBT ON and carrying current.
Figure 12. Short−Circuit Current Protection (Low−Side Operation only)
Input/Output Interface Circuit
+5 V (for MCU or Control power)
R
= 10 kΩ
PF
SPM
,
,
IN(UH) IN(VH) IN(WH)
,
,
IN(UL) IN(VL) IN( WL)
MCU
VFO
COM
NOTE: RC coupling at each input might change depending on the PWM control scheme used in the application and the wiring
impedance of the application’s printed circuit board. The input signal section of the Motion SPM 45 product integrates
5 kW(typ.) pull−down resistor. Therefore, when using an external filtering resistor, please pay attention to the signal voltage
drop at input terminal.
Figure 13. Recommended MCU I/O Interface Circuit
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12
FNA41560T2
HVIC
(26) VB(U)
P (3)
U (4)
VB(U)
CBS
CBS
CBS
CBSC
(25) VS(U)
VS(U)
OUT(UH)
VS(U)
RS
(20) IN
(UH)
IN(UH)
Gating UH
Gating VH
Gating WH
(24) VB(V)
(23) VS(V)
VB(V)
CBSC
VS(V)
RS
(19) IN
(VH)
OUT(VH)
VS(V)
IN(VH)
V (5)
(22) VB(W)
(21) VS(W)
M
VB(W)
VS(W)
CBSC
RS
(18) IN
(WH)
IN(WH)
VDD
CDCS
VDC
OUT(WH)
VS(W)
(17) VDD(H)
(15) COM
+15 V
W (6)
CPS CPS CPS
CSPC15
CSP15
COM
MCU
+5 V
LVIC
(16) VDD(L)
VDD
VFO
OUT(UL)
RPF
RSU
NU (7)
NV (8)
NW (9)
CSPC05
CSP05
RS
(11) VFO
Fault
CPF
CBP
F
OUT(VL)
RS
(14) IN
(UL)
RSV
Gating UL
Gating VL
Gating WL
IN(UL)
IN(VL)
IN(WL)
RS
RS
(13) IN
(VL)
(12) IN
(WL)
CSC
OUT(WL)
COM
CSC
(10) C
CPS CP
SC
CPS
S
RSW
RF
(1) VTH
(2) RTH
RTH
THERMISTOR
U−Phase Current
V−Phase Current
W−Phase Current
Input Signal for
Short−Circuit Protection
Temp. Monitoring
Figure 14. Typical Application Circuit
NOTES:
12.To avoid malfunction, the wiring of each input should be as short as possible (less than 2 − 3 cm).
13.V output is an open−drain type. This signal line should be pulled up to the positive side of the MCU or control power supply with a resistor
FO
that makes I up to 1 mA.
FO
14.C
of around seven times larger than bootstrap capacitor C is recommended.
SP15
BS
15.Input signal is active−HIGH type. There is a 5 kW resistor inside the IC to pull down each input signal line to GND. RC coupling circuits is
recommanded for the prevention of input signal oscillation. R C time constant should be selected in the range 50 ~ 150 ns (recommended
S
PS
R
= 100 W, C = 1 nF).
S
PS
16.To prevent errors of the protection function, the wiring around RF and CSC should be as short as possible.
17.In the short−circuit protection circuit, please select the R C time constant in the range 1.5 ~ 2 ms. Do enough evaluaiton on the real system
F
SC
because short−circuit protection time may vary wiring pattern layout and value of the R C time constant.
F
SC
18.The connection between control GND line and power GND line which includes the N , N , N must be connected to only one point. Please
U
V
W
do not connect the control GND to the power GND by the broad pattern. Also, the wiring distance between control GND and power GND
should be as short as possible.
19.Each capacitor should be mounted as close to the pins of the Motion SPM 45 product as possible.
20.To prevent surge destruction, the wiring between the smoothing capacitor and the P & GND pins should be as short as possible. The use
of a high−frequency non−inductive capacitor of around 0.1 ~ 0.22 mF between the P and GND pins is recommended.
21.Relays are used in almost every systems of electrical equipment in home appliances. In these cases, there should be sufficient distance
between the MCU and the relays.
22.The zener diode or transient voltage suppressor should be adopted for the protection of ICs from the surge destruction between each pair
of control supply terminals (recommanded zener diode is 22 V / 1 W, which has the lower zener impedance characteristic than about 15 W).
23.Please choose the electrolytic capacitor with good temperature characteristic in C . Also, choose 0.1 ~ 0.2 mF R−category ceramic
BS
capacitors with good temperature and frequency characteristics in C
.
BSC
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13
FNA41560T2
PACKAGE MARKING AND ORDERING INFORMATION
Device
Device Marking
Package
Shipping
FNA41560T2
FNA41560T2
SPMAA−C26 / 26LD, PDD STD CERAMIC TYPE,
LONG LEAD DUAL FORM TYPE
(Pb−Free)
12 Units / Rail
SPM is registered trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or
other countries.
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14
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SPMAA−C26 / 26LD, PDD STD CERAMIC TYPE, LONG LEAD DUAL FORM TYPE
CASE MODFC
ISSUE O
DATE 31 JAN 2017
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13555G
SPMAA−C26 / 26LD, PDD STD CERAMIC TYPE, LONG LEAD DUAL
PAGE 1 OF 1
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