FOD8316R2 [ONSEMI]
2.5A 输出电流，IGBT 驱动光耦合器，带去饱和检测和隔离故障传感;
| 型号： | FOD8316R2 |
| 厂家： | 
ONSEMI |
| 描述： | 2.5A 输出电流，IGBT 驱动光耦合器，带去饱和检测和隔离故障传感 驱动 双极性晶体管 光电二极管 接口集成电路 驱动器 |
| 文件： | 总28页 (文件大小：458K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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2.5 A Output Current, IGBT
Drive Optocoupler with
Desaturation Detection and
Isolated Fault Sensing
SOIC16 W
CASE 751EN
FOD8316
MARKING DIAGRAM
Description
The FOD8316 is an advanced 2.5 A output current IGBT drive
optocoupler capable of driving most 1200 V /150 A IGBTs. It is ideally
suited for fast−switching driving of power IGBTs and MOSFETs used
in motor−control inverter applications and high−performance power
systems. The FOD8316 offers critical protection features necessary for
preventing fault conditions that lead to destructive thermal runaway of
IGBTs.
ON
8316
V
J
D X YY KK
8316 = Device Number, e.g., ‘8316’ for FOD8316
®
The device utilizes onsemi’s proprietary OPTOPLANAR coplanar
V
= DIN EN/IEC60747−5−5 Option (Only Appears
on Component Ordered with this Option)
= Plant Code, e.g., ‘D’
packaging technology, and optimized IC design to achieve high noise
immunity, characterized by high common−mode rejection and power
supply rejection specifications.
D
X
= Last Digit Year Code, e.g., ‘E’ for 2014
YY = Two Digit Work Week Ranging from ‘01’ to ‘53’
KK = Lot Traceability Code
The FOD8316 consists of an integrated gate drive optocoupler
featuring low R
CMOS transistors to drive the IGBT from
J
= Package Assembly Code, e.g., ‘J’
DS(ON)
rail−to−rail and an integrated high−speed isolated feedback for fault
sensing. The device is housed in a compact 16−pin small−outline plastic
package which meets the 8 mm creepage and clearance requirements.
ORDERING INFORMATION
See detailed ordering and shipping information on page 26 of
this data sheet.
Features
• High Noise Immunity Characterized by Common Mode Rejection −
35 kV/ms Minimum, V = 1500 V
CM
PEAK
• 2.5 A Peak Output Current Driving Capability for Most 1200 V /
150 A IGBTs
Features (continued)
• User−Configurable: Inverting, Non−inverting,
Auto−reset, Auto−shutdown
• 8 mm Creepage and Clearance Distances
• Optically Isolated Fault Sensing Feedback
• “Soft” IGBT Turn−off
• Built−in IGBT Protection
♦ Desaturation Detection
Applications
♦ Under−Voltage Lockout (UVLO) Protection
• Wide Supply Voltage Range: 15 V to 30 V
♦ P−Channel MOSFETs at Output Stage Enables Output Voltage
Swing Close to the Supply Rail (Rail−to−Rail Output)
• 3.3 V / 5 V, CMOS/TTL Compatible Inputs
• Industrial Inverter
• Induction Heating
• Isolated IGBT Drive
• High Speed
♦ 250 ns Maximum Propagation Delay Over Full Operating
Temperature Range
• Extended Industrial Temperate Range, −40°C to 100°C
• Safety and Regulatory Approvals
♦ UL1577, 4,243 V
for 1 Minute
RMS
♦ DIN EN/IEC 60747−5−5:
1,414 V
8,000 V
Working Insulation Voltage Rating
Transient Isolation Voltage Rating
PEAK
PEAK
• R
of 1 W (Typical) Offers Lower Power Dissipation
DS(ON)
© Semiconductor Components Industries, LLC, 2010
1
Publication Order Number:
February, 2023 − Rev. 3
FOD8316/D
FOD8316
TRUTH TABLE
V
V
UVLO (V
− V )
DESAT Detected?
FAULT
X
V
O
IN+
IN−
DD2
E
X
X
Active
X
Yes
X
LOW
LOW
LOW
LOW
HIGH
X
X
X
X
LOW
X
LOW
X
X
X
HIGH
LOW
X
X
HIGH
Not Active
No
HIGH
PIN CONFIGURATION
VIN+
VIN–
1
2
3
4
5
6
7
8
16 VE
VLED2+
15
VDD1
14 DESAT
GND1
RESET
FAULT
VLED1+
VLED1−
VDD2
13
12
11
10
9
VS
VO
VSS
VSS
Figure 1. Pin Configuration
PIN DEFINITIONS
Pin No.
Name
Description
1
2
3
4
V
V
Non−inverting Gate Drive Control Input
Inverting Gate−Drive Control Input
Positive Input Supply Voltage (3 V to 5.5 V)
Input Ground
IN+
IN−
V
DD1
GND1
5
6
RESET
FAULT
FAULT Reset Input
Fault Output (Open Drain)
7
V
LED 1 Anode (Do not connect. Leave floating.)
LED 1 Cathode (Must be connected to ground.)
Output Supply Voltage (Negative)
Output Supply Voltage (Negative)
Gate−Drive Output Voltage
LED1+
LED1−
8
V
9
V
V
SS
10
11
12
13
14
15
16
SS
V
O
V
S
Pull−up PMOS Transistor Source
Positive Output Supply Voltage
V
DD2
DESAT
Desaturation Voltage Input
V
LED2+
LED 2 Anode (Do not connect. Leave floating.)
Output Supply Voltage / IGBT Emitter
V
E
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2
FOD8316
BLOCK DIAGRAM
VLED1+
7
Output IC
13
12
Input IC
VDD2
VS
3
VDD1
1
2
6
VIN+
VIN–
FAULT
11
UVLO
VO
Gate Drive
Optocoupler
LED1
4
8
GND1
VLED1–
DESAT
Shield
9, 10
VSS
14
16
DESAT
VE
5
Fault
LED2
RESET
Fault Sense
Optocoupler
Shield
15
VLED2+
Figure 2. Block Diagram
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3
FOD8316
SAFETY AND INSULATION RATINGS (As per DIN EN/IEC 60747−5−5, this optocoupler is suitable for “safe electrical insulation”
only within the safety limit data. Compliance with the safety ratings must be ensured by means of protective circuits.)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Installation Classifications per DIN VDE 0110/1.89 Table 1
Rated Mains Voltage < 150 V
Rated Mains Voltage < 300 V
Rated Mains Voltage < 450 V
Rated Mains Voltage < 600 V
−
−
I−IV
−
−
−
−
−
−
−
−
−
RMS
RMS
RMS
RMS
I−IV
−
I−IV
−
I−IV
Rated Mains Voltage < 1000 V
Climatic Classification
−
I−III
RMS
−
40/100/21
Pollution Degree (DIN VDE 0110/1.89)
−
2
−
−
CTI
Comparative Tracking Index (DIN IEC 112/VDE 0303 Part 1)
175
2651
V
PR
Input−to−Output Test Voltage, Method b, V
x 1.875 = V
,
V
peak
IORM
PR
100% Production Test with t = 1 s, Partial Discharge < 5 pC
m
Input−to−Output Test Voltage, Method a, V
x 1.6 = V
,
2262
−
−
V
peak
IORM
PR
Type and Sample Test with t = 10 s, Partial Discharge < 5 pC
m
VI
Maximum Working Insulation Voltage
Highest Allowable Over Voltage
External Creepage
1414
8000
8.0
−
−
−
−
−
−
−
−
−
−
V
V
ORM
peak
V
IOTM
peak
mm
mm
mm
External Clearance
8.0
Insulation Thickness
0.5
Safety Limit Values − Maximum Values in Failure;
Case Temperature
T
150
100
600
−
−
−
−
°C
Case
Safety Limit Values − Maximum Values in Failure;
Input Power
P
mW
S,INPUT
Safety Limit Values − Maximum Values in Failure;
Output Power
P
−
−
−
−
mW
S,OUTPUT
9
R
Insulation Resistance at T , V = 500 V
10
W
IO
S
IO
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FOD8316
ABSOLUTE MAXIMUM RATINGS (T = 25°C unless otherwise noted)
A
Symbol
Parameter
Value
−40 to +125
Unit
°C
T
STG
Storage Temperature
Operating Temperature
Junction Temperature
T
OPR
−40 to +100
°C
T
J
−40 to +125
°C
T
SOL
Lead Wave Solder Temperature (No Solder Immersion)
Refer to Reflow Temperature Profile on Page 25.
260 for 10 seconds
°C
I
Fault Output Current
15
3
mA
A
FAULT
I
Peak Output Current (Note 1)
Negative Output Supply Voltage (Note 2)
Positive Output Supply Voltage
Gate Drive Output Voltage
Output Supply Voltage
O(PEAK)
V
E
− V
0 to 15
V
SS
V
− V
−0.5 to 35 − (V − V
)
SS
V
DD2
E
E
V
−0.5 to 35
−0.5 to 35
−0.5 to 6
V
O(peak)
V
− V
V
DD2
SS
V
Positive Input Supply Voltage
Input Voltages
V
DD1
V
IN+
, V
and V
−0.5 to V
V
IN−
RESET
DD1
DD1
V
Fault Pin Voltage
−0.5 to V
V
FAULT
V
Source of Pull−up PMOS Transistor Voltage
DESAT Voltage
V
SS
+ 6.5 to V
DD2
V
S
V
V to V + 25
V
DESAT
E
E
PD
Input Power Dissipation (Note 3, 5)
Output Power Dissipation (Note 4, 5)
100
mW
mW
I
PD
600
O
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Maximum pulse width = 10 ms, maximum duty cycle = 0.2%.
2. This negative output supply voltage is optional. It’s only needed when negative gate drive is implemented. Refer to “Dual Supply Operation −
Negative Bias at Vss” on page 23.
3. No derating required across temperature range.
4. Derate linearly above 64°C, free air temperature at a rate of 10.2 mW/°C
5. Functional operation under these conditions is not implied. Permanent damage may occur if the device is subjected to conditions outside
these ratings.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
−40
3
Max
+100
5.5
Unit
°C
V
T
A
Ambient Operating Temperature
Input Supply Voltage (Note 6)
Total Output Supply Voltage
Negative Output Supply Voltage
V
DD1
V
− V
15
0
30
V
DD2
SS
V − V
15
V
E
SS
V
DD2
− V
Positive Output Supply Voltage (Note 6)
15
30 − (V − V )
SS
V
E
E
V
S
Source of Pull−up PMOS Transistor Voltage
V
SS
+ 7.5
V
DD2
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. During power up or down, it is important to ensure that V
remains low until both the input and output supply voltages reaches the proper
IN+
recommended operating voltages to avoid any momentary instability at the output state. See also the discussion in the “Time to Good Power”
section on page 23.
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5
FOD8316
ISOLATION CHARACTERISTICS (Apply over all recommended conditions, typical value is measured at T = 25°C)
A
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
ISO
Input−Output Isolation Voltage T = 25°C, Relative Humidity < 50 %, t = 1.0 minute,
4,243
−
−
V
RMS
A
I
≤ 10 mA, 50 Hz (Note 7, 8, 9)
I−O
11
R
C
Isolation Resistance
Isolation Capacitance
V
V
= 500 V (Note 7)
−
−
10
−
−
W
ISO
I−O
= 0 V, Freq = 1.0 MHz (Note 7)
1
pF
ISO
I−O
7. Device is considered a two terminal device: pins 1 to 8 are shorted together and pins 9 to 16 are shorted together.
8. 4,243 VRMS for 1−minute duration is equivalent to 5,091 VRMS for 1−second duration.
9. The input−output isolation voltage is a dielectric voltage rating as per UL1577. It should not be regarded as an input−output continuous
voltage rating. For the continuous working voltage rating refer to your equipment−level safety specification or DIN EN/IEC 60747−5−5 Safety
and Insulation Ratings Table.
ELECTRICAL CHARACTERISTICS (Apply over all recommended conditions, typical value is measured at V
= 5 V,
DD1
V
DD2
− V = 30 V, V − V = 0 V, and T = 25°C; unless otherwise specified.)
SS E SS A
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Figure
V
V
,
,
Logic Low Input Voltages
Logic High Input Voltages
Logic Low Input Currents
−
−
0.8
V
IN+L
IN−L
V
RESETL
V
V
,
,
2.0
−
−
V
IN+H
IN−H
V
RESETH
I
, I
,
V
IN
= 0.4 V
−0.5
−0.001
−
mA
IN+L IN−L
I
RESETL
I
FAULT Logic Low Output Current
FAULT Logic High Output Current
High Level Output Current
V
V
V
V
V
V
V
= 0.4 V
5.0
−40
−1
12.0
0.002
−2.5
−
−
−
mA
mA
A
3, 34
34
FAULTL
FAULT
I
= V
FAULTH
FAULT
DD1
I
= V
= V
− 3 V
−
4, 9, 35
OH
O
O
O
O
O
DD2
DD2
− 6 V (Note 10)
−2.5
1
−
A
I
OL
Low Level Output Current
= V + 3 V
3
−
A
5, 36
6, 40
SS
= V + 6 V (Note 11)
2.5
70
−
−
A
SS
I
Low Level Output Current During
Fault Condition
− V = 14 V
125
170
mA
OLF
SS
V
High Level Output Voltage
Low Level Output Voltage
High Level Supply Current
Low Level Supply Current
High Level Output Supply Current
Low Level Output Supply Current
High Level Source Current
Low Level Source Current
I
I
= −100 mA (Note 12, 13, 14) V − 1.0 V V − 0.5 V
−
0.5
17
3
V
7, 9, 37
8, 10, 37
11, 38
OH
O
S
S
V
= 100 mA
−
−
0.1
14
V
OL
O
I
I
V
V
V
V
= V
= 5.5 V, V = 0 V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
DD1H
IN+
IN+
DD1
IN−
I
= V = 0 V, V = 5.5 V
DD1
−
2
DD1L
IN−
= Open (Note 14)
= Open
−
1.7
1.8
0.65
0.6
−0.5
3
12, 13,
39
DD2H
O
O
I
−
2.8
1.5
1.4
−
DD2L
I
I
O
I
O
= 0 mA
= 0 mA
−
39
39
SH
I
−
SL
EL
EH
I
V Low Level Supply Current
E
−0.8
−0.5
15, 39
I
V High Level Supply Current
E
−0.25
−0.25
36
−
I
Blanking Capacitor Charge Current
Blanking Capacitor Discharge Current
V
V
V
V
= 2 V (Note 14, 15)
−0.13
10
−0.33
−
14, 40
40
CHG
DESAT
I
= 7 V
DSCHG
DESAT
V
Under Voltage Lockout Threshold
(Note 14)
> 5 V @ 25°C
< 5 V @ 25°C
10.8
9.8
11.7
10.7
1.0
12.7
11.7
−
17, 31,
41
UVLO+
UVLO−
O
O
V
V
UVLO
Under Voltage Lockout Threshold
Hysteresis
@ 25°C
0.4
V
HYS
V
DESAT
DESAT Threshold (Note 14)
V
DD2
− V > V
, V < 5 V
6.0
6.5
7.2
V
18, 40
E
ULVO−
O
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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6
FOD8316
10.Maximum pulse width = 10 ms, maximum duty cycle = 0.2%.
11. Maximum pulse width = 4.99 ms, maximum duty cycle = 99.8%.
12.V is measured with the DC load current in this testing (Maximum pulse width = 1 ms, maximum duty cycle = 20%).When driving capacitive
OH
loads, V will approach V as I approaches zero units.
OH
DD
OH
13.Positive output supply voltage (V
− V ) should be at least 15 V to ensure adequate margin in excess of the maximum under−voltage
DD2
E
lockout threshold, V
, of 13.5 V.
UVLO+
14.When V
− V > V
and output state V is allowed to go high, the DESAT detection feature is active and provides the primary source
UVLO O
DD2
E
of IGBT protection. UVLO is needed to ensure DESAT detection is functional.
15.The blanking time, t , is adjustable by an external capacitor (C ), where t
= C
x (V / I
).
BLANK
BLANK
BLANK
BLANK
DESAT CHG
SWITCHING CHARACTERISTICS (Apply over all recommended conditions, typical value is measured at V
= 5 V,
DD1
V
DD2
− V = 30 V, V − V = 0 V, T = 25°C unless otherwise specified.)
SS E SS A
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Figure
t
Propagation Delay Time to Logic Low Rg = 10 W, Cg = 10 nF,
−
140
250
ns
ns
ns
ns
19, 20,
21, 22,
23, 24,
42, 50
PHL
Output (Note 17)
f = 10 kHz, Duty Cycle = 50%
(Note 16)
t
Propagation Delay Time to Logic High
Output (Note 18)
−
−
160
20
−
250
100
150
PLH
PWD
Pulse Width Distortion,
| t
PHL
− t
PLH
| (Note 19)
PDD Skew
Propagation Delay Difference
−150
between Any Two Parts or Channels,
(t
PHL
− t ) (Note 20)
PLH
t
Output Rise Time (10% to 90%)
Output Fall Time (90% to 10%)
−
−
−
25
25
−
−
ns
ns
ns
42, 50
25, 43
R
t
F
t
t
DESAT Sense to 90% V Delay
Rg = 10 W, Cg = 10 nF,
450
700
DESAT(90%)
O
(Note 21)
V
DD2
− V = 30 V
SS
DESAT Sense to 10% V Delay
−
−
−
3
2.7
1.4
250
6
4
5
ms
ms
ns
ms
26, 28,
29, 43
DESAT(10%)
O
(Note 21)
t
DESAT Sense to Low Level FAULT
Signal Delay (Note 22)
27, 43,
51
DESAT(FAULT)
t
DESAT Sense to DESAT Low
Propagation Delay (Note 23)
−
43
DESAT(LOW)
t
RESET to High Level FAULT Signal
Delay (Note 24)
20
30, 44,
51
RESET(FAULT)
t
DESAT Input Mute
10
1.2
−
22
−
35
−
ms
ms
ms
ms
ms
DESAT(MUTE)
PW
RESET Signal Pulse Width
UVLO Turn On Delay (Note 25)
UVLO Turn Off Delay (Note 26)
Time to Good Power (Note 27)
RESET
t
V
V
= 20 V in 1.0 ms Ramp
4
−
31, 45
UVLO ON
DD2
t
−
3
−
UVLO OFF
t
= 0 to 30 V in 10 ms
−
2.5
−
32, 33,
45
GP
DD2
Ramp
| CM
|
Common Mode Transient Immunity at T = 25°C, V
= 5 V,
= 25 V, V = Ground,
35
35
50
50
−
−
kV/ms
kV/ms
47, 48
H
A
V
DD1
Output High
DD2 SS
V
CM
= 1500 Vpk (Note 28)
| CM |
Common Mode Transient Immunity at T = 25°C, V
= 5V,
46, 49
L
A
V
DD1
Output Low
= 25 V, V = Ground,
DD2 SS
V
CM
= 1500 Vpk (Note 29)
16.This load condition approximates the gate load of a 1200 V / 150 A IGBT.
17.Propagation delay t is measured from the 50% level on the falling edge of the input pulse (V , V ) to the 50% level of the falling edge
PHL
IN+ IN−
of the V signal. Refer to Figure 50.
O
18.Propagation delay t
is measured from the 50% level on the rising edge of the input pulse (V , V ) to the 50% level of the rising edge
PLH
IN+ IN−
of the V signal. Refer to Figure 50.
O
19.PWD is defined as | t
− t
PLH
| for any given device.
PHL
20.The difference between t
and t
between any two FOD8316 parts under same operating conditions with equal loads.
PHL
PLH
21.This is the amount of time the DESAT threshold must be exceeded before V begins to go LOW. This is supply voltage dependent. See
O
Figure 51.
22.This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes LOW. See Figure 51.
23.The length of time the DESAT threshold must be exceeded before V begins to go LOW, and the FAULT output begins to go LOW. See
O
Figure 51.
24.The length of time from when RESET is asserted LOW, until FAULT output goes HIGH. See Figure 51.
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FOD8316
25.The UVLO turn−on delay, t
, is measured from V
threshold voltage of the output supply voltage (V
threshold voltage of the output supply voltage (V
) to the 5 V level of the
) to the 5 V level of the
UVLO ON
UVLO+
DD2
rising edge of the V signal.
O
26.The UVLO turn−off delay, t
, is measured from V
UVLO−
UVLO OFF
DD2
falling edge of the V signal.
O
27.The time to good power, t , is measured from 13.5 V level of the rising edge of the output supply voltage (V
) to the 5 V level of the rising
GP
DD2
edge of the V signal.
O
28.Common−mode transient immunity at output HIGH state is the maximum tolerable negative dVCM/dt on the trailing edge of the
common−mode pulse, V , to assure the output will remain in HIGH state (i.e., V > 15 V or FAULT > 2 V).
CM
O
29.Common−mode transient immunity at output LOW state is the maximum positive tolerable dVCM/dt on the leading edge of the
common−mode pulse, V , to assure the output will remain in LOW state (i.e., V < 1.0 V or FAULT < 0.8 V).
CM
O
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FOD8316
TYPICAL PERFORMANCE CHARACTERISTICS
50
40
30
20
10
0
7
6
5
V
= V
= V
− 6 V
− 3 V
O
DD2
4
3
2
1
0
V
O
DD2
V
V
I
= 5 V
= 5 V
DD1
IN+
= 10 mA
V
V
− V = 30 V
LED2+
DD2
DD1
SS
= 5 V
T = 25°C
A
0
1
2
3
4
5
−40 −20
0
20
40
60
80
100
V
, FAULT VOLTAGE (V)
T , TEMPERATURE (°C)
A
FAULTL
Figure 3. FAULT Logic Low Output Current (IFAULTL
)
Figure 4. High Level Output Current (IOH) vs.
Temperature
vs. FAULT Logic Low Output Voltage (VFAULTL
)
7
6
150
T = −40 °C
V
V
= V + 6 V
A
O
SS
125
100
75
5
4
3
2
1
0
T = 25 °C
A
T = 100 °C
A
= V + 3 V
O
SS
V
DD2
V
DD1
− V = 30 V
SS
= 5 V
V
V
− V = 30 V
DD2
DD1
SS
= 5 V
50
−40 −20
0
20
40
60
80
100
0
5
10
15
20
25
30
T , TEMPERATURE (°C)
A
V , OUTPUT VOLTAGE (V)
O
Figure 5. Low Level Output Current (IOL) vs.
Temperature
Figure 6. Low Level Output Current During Fault
Condition (IOLF) vs. Output Voltage (VOL
)
0.1
0.25
I
= −650 mA
O
0.0
−0.1
−0.2
−0.3
−0.4
−0.5
0.20
0.15
0.10
0.05
0.00
I
O
= −100 mA
I
= 100 mA
O
V
V
V
− V = 30 V
V
V
V
− V = 30 V
DD2
DD1
IN+
SS
DD2
DD1
IN+
SS
= 5 V
= 5 V
= 5 V
= 0 V
−40 −20
0
20
40
60
80
100
−40 −20
0
20
40
60
80
100
T , TEMPERATURE (°C)
A
T , TEMPERATURE (°C)
A
Figure 7. High Level Output Voltage Drop
(VOH − VDD) vs. Temperature
Figure 8. Low Level Output Voltage (VOL) vs.
Temperature
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9
FOD8316
TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
30
29
28
27
26
25
4
V
DD2
V
DD1
V
IN+
− V = 30 V
= 5 V
= 0 V
SS
3
2
1
0
T = −40 °C
A
T = 100 °C
A
25 °C
25 °C
100 °C
−40 °C
V
DD2
V
DD1
V
IN+
− V = 30 V
= 5 V
= 5 V
SS
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
I
, HIGH LEVEL OUTPUT CURRENT (A)
I
OL
, LOW LEVEL OUTPUT CURRENT (A)
OH
Figure 9. High Level Output Voltage (VOH) vs.
High Level Output Current (IOH
Figure 10. Low Level Output Voltage (VOL) vs.
)
Low Level Output Current (IOL
)
2.2
2.0
1.8
1.6
1.4
1.2
1.0
20
15
10
5
V
V
= 5 V
= 0 V (I
V
V
V
− V = 30 V
= 5 V
DD1
IN+
DD2
DD1
IN+
SS
) / 5 V (I
)
DD1L
DD1H
= 0 V (I
) / 5 V (I
)
DD2L
DD2H
I
I
DD2L
I
DD1H
DD2H
I
DD1L
0
−40 −20
0
20
40
60
80
100
−40 −20
0
20
40
60
80
100
T , TEMPERATURE (°C)
A
T , TEMPERATURE (°C)
A
Figure 11. Supply Current (IDD1) vs. Temperature
Figure 12. Output Supply Current (IDD2) vs.
Temperature
2.2
−0.15
−0.20
−0.25
−0.30
V
DD1
V
IN+
= 5 V
= 0 V (I
V
V
V
V
− V = 30 V
= 5 V
= 5 V
DD2
SS
) / 5 V (I
)
DD1
DD2L
DD2H
2.0
1.8
1.6
1.4
1.2
1.0
IN+
= 0 to 6 V
DESAT
I
DD2L
I
DD2H
15
20
25
30
−40 −20
0
20
40
60
80
100
V
DD2
, OUTPUT SUPPLY VOLTAGE (V)
T , TEMPERATURE (°C)
A
Figure 13. Output Supply Current (IDD2) vs.
Output Supply Voltage (VDD2
Figure 14. Blanking Capacitor Charge Current
(ICHG) vs. Temperature
)
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10
FOD8316
TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
0.0
−0.2
−0.4
−0.6
−0.8
3.0
V
V
V
− V = 30 V
SS
= 5 V
DD2
DD1
IN+
−40°C
2.5
2.0
1.5
1.0
0.5
0.0
25°C
= 0 V (I ) / 5 V (I
)
EL
EH
100°C
I
EH
I
EL
V
DD2
V
DD1
V
IN+
− V = 30 V
= 5 V
= 5 V
SS
−40 −20
0
20
40
60
80
100
0.0
0.5
1.0
1.5
2.0
T , TEMPERATURE (°C)
A
I , OUTPUT CURRENT (mA)
O
Figure 15. Supply Current (IE) vs. Temperature
Figure 16. Source Current (IS) vs.
Output Current (IO)
15
7.0
6.8
6.6
6.4
6.2
6.0
V
V
UVLO+
10
5
UVLO−
V
V
V
− V = 30 V
= 5 V
= 5 V
DD2
DD1
IN+
SS
V
V
= 5 V
= 5 V
DD1
IN+
0
−40 −20
0
20
40
60
80
100
−40 −20
0
20
40
60
80
100
T , TEMPERATURE (°C)
A
T , TEMPERATURE (°C)
A
Figure 17. Under Voltage Lockout Threshold
(VUVLO) vs. Temperature
Figure 18. DESAT Threshold (VDESAT) vs.
Temperature
0.25
0.20
0.25
0.20
0.15
0.10
0.05
t
t
PLH
t
t
PLH
0.15
0.10
0.05
PHL
PHL
V
V
− V = 30 V
= 5 V
DD2
SS
V
DD1
= 5 V
DD1
f = 10 kHz 50% Duty Cycle
R = 10 W C = 10 nF
f = 10 kHz 50% Duty Cycle
R = 10 W C = 10 nF
L
L
L
L
−40 −20
0
20
40
60
80
100
15
20
, SUPPLY VOLTAGE (V)
DD2
25
30
T , TEMPERATURE (°C)
A
V
Figure 19. Propagation Delay (tP) vs. Temperature
Figure 20. Propagation Delay (tP) vs.
Supply Voltage (VDD2
)
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11
FOD8316
TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
0.20
0.18
0.16
0.14
0.12
0.18
V
− V = 30 V
V
− V = 30 V
DD2
SS
DD2 SS
f = 10 kHz 50% Duty Cycle
R = 10 W C = 10 nF
f = 10 kHz 50% Duty Cycle
R = 10 W C = 10 nF
L
L
L
L
0.16
0.14
0.12
0.10
V
V
V
= 4.5 V
= 5.0 V
= 5.5 V
V
V
V
= 4.5 V
= 5.0 V
= 5.5 V
DD1
DD1
DD1
DD1
DD1
DD1
−40 −20
0
20
40
60
80
100
−40 −20
0
20
40
60
80
100
T , TEMPERATURE (°C)
A
T , TEMPERATURE (°C)
A
Figure 21. Propagation Delay Time to Logic High
Output (tPLH) vs. Temperature
Figure 22. Propagation Delay Time to Logic Low
Output (tPHL) vs. Temperature
0.20
0.18
0.20
0.18
t
t
PLH
0.16
0.14
0.12
0.10
0.16
0.14
0.12
0.10
t
t
PLH
PHL
PHL
V
V
− V = 30 V
= 5 V
V
V
− V = 30 V
= 5 V
DD2
SS
DD2
SS
DD1
DD1
f = 10 kHz 50% Duty Cycle
R = 10 W
f = 10 kHz 50% Duty Cycle
C = 10 nF
L
L
0
20
40
60
80
100
0
10
20
30
40
50
C , LOAD CAPACITANCE (nF)
L
R , LOAD RESISTANCE (W)
L
Figure 23. Propagation Delay (tP) vs.
Load Capacitance (CL)
Figure 24. Propagation Delay (tP) vs.
Load Resistance (RL)
0.8
0.6
0.4
0.2
0.0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
V
V
V
− V = 30 V
= 5 V
= 5 V
V
V
= 5 V
= 5 V
DD2
DD1
IN+
SS
DD1
IN+
R = 10 W C = 10 nF
L
L
R = 10 W C = 10 nF
L
L
V
V
− V = 30 V
SS
DD2
− V = 15 V
DD2
SS
−40 −20
0
20
40
60
80
100
−40 −20
0
20
40
60
80
100
T , TEMPERATURE (°C)
A
T , TEMPERATURE (°C)
A
Figure 25. DESAT Sense to 90% VO Delay
(tDESAT(90%)) vs. Temperature
Figure 26. DESAT Sense to 10% VO Delay
(tDESAT(10%)) vs. Temperature
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12
FOD8316
TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
1.8
1.6
1.4
1.2
1.0
0.8
10
V
V
V
− V = 30 V
= 5 V
= 5 V
V
V
= 5 V
= 5 V
DD2
DD1
IN+
SS
DD1
IN+
8
6
4
2
0
R = 10 W
L
R = 10 W C = 10 nF
L
L
V
E
− V = 0 V
SS
V
− V = 30 V
DD2
SS
V
E
− V = 15 V
SS
V
DD2
− V = 15 V
SS
−40 −20
0
20
40
60
80
100
0
5
10
15
20
25
30
T , TEMPERATURE (°C)
A
C , LOAD CAPACITANCE (nF)
L
Figure 27. DESAT Sense to Low Level FAULT
Signal Delay (tDESAT(FAULT)) vs. Temperature
Figure 28. DESAT Sense to 10% VO Delay
(tDESAT(10%)) vs. Load Capacitance (CL)
4.0
9
V
V
= 5 V
= 5 V
V
V
− V = 30 V
SS
DD1
DD2
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
= V
IN+
IN+
DD1
8
7
6
5
4
3
C = 10 nF
R = 10 W C = 10 nF
L
L
L
V
V
− V = 30 V
SS
DD2
V
= 4.5 V
DD1
− V = 15 V
DD2
SS
V
DD1
= 5.5 V
V
= 5.0 V
DD1
10
20
30
40
50
−40 −20
0
20
40
60
80
100
R , LOAD RESISTANCE (W)
L
T , TEMPERATURE (°C)
A
Figure 29. DESAT Sense to 10% VO Delay
(tDESAT(10%)) vs. Load Resistance (RL)
Figure 30. RESET to High Level FAULT Signal Delay
(tRESET(FAULT)) vs. Temperature
5.0
5
V
V
V
− V = 20 V
= 5 V
= 5 V
V
V
= 5 V
= 5 V
DD2
DD1
IN+
SS
DD1
IN+
4.5
4.0
3.5
3.0
2.5
2.0
4
3
2
1
0
f = 50 Hz 50% Duty Cycle
f = 50 Hz 50% Duty Cycle
t
UVLO ON
t
UVLO OFF
−40 −20
0
20
40
60
80
100
15
20
25
30
T , TEMPERATURE (°C)
A
V
DD2
, SUPPLY VOLTAGE (V)
Figure 31. Under Voltage Lockout Threshold Delay
(tUVLO) vs. Temperature
Figure 32. Time to Good Power (tGP) vs.
Supply Voltage (VDD2
)
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13
FOD8316
TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
5
V
V
V
− V = 30 V
= 5 V
= 5 V
DD2
DD1
IN+
SS
4
3
2
1
0
f = 50 Hz 50% Duty Cycle
−40 −20
0
20
40
60
80
100
T , TEMPERATURE (°C)
A
Figure 33. Time to Good Power (tGP) vs.
Temperature
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14
FOD8316
TEST CIRCUITS
FOD8316
VE
A
1
2
3
4
5
6
7
8
VIN+
16
15
14
13
12
11
10
9
10 mA
0.1 mF
VLED2+
DESAT
VDD2
VS
VIN–
+
–
5 V
0.1 mF
VDD1
GND1
RESET
FAULT
VLED1+
–
+
VFAULT
VO
IFAULT
VSS
Switch A closed for I
Switch A opened for I
FAULTL
FAULTH
VSS
VLED1−
*
V
FAULT
V
FAULT
= 0.4 V for I
= 5.0 V for I
FAULTL
FAULTH
Figure 34. Fault Output Current (IFAULTL) and (IFAULTH) Test Circuit
FOD8316
VE
VLED2+
DESAT
VDD2
VS
1
2
3
4
5
6
7
8
VIN+
16
15
14
13
12
11
10
9
Pulse Gen
PW = 10 ms
Period = 5 ms
+
–
+
–
VIN–
VE
0.1 mF
–
+
5 V
0.1 mF
VDD1
0.1 mF 47 mF
0.1 mF 47 mF
GND1
RESET
FAULT
VLED1+
VO
+
–
+
–
30 V
VO
3 kW
VSS
VSS
VLED1−
*
Figure 35. High Level Output Current (IOH) Test Circuit
FOD8316
VE
VLED2+
DESAT
VDD2
VS
1
2
3
4
5
6
7
8
VIN+
16
15
14
13
12
11
10
9
Pulse Gen
PW = 4.99 ms
Period = 5 ms
+
–
+
VIN–
VE
0.1 mF
–
–
+
5 V
VDD1
0.1 mF
GND1
RESET
FAULT
VLED1+
+
–
0.1 mF 47 mF
30 V
VO
VO
3 kW
+
–
VSS
VSS
VLED1−
*
0.1 mF 47 mF
Figure 36. Low Level Output Current (IOL) Test Circuit
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15
FOD8316
TEST CIRCUITS (CONTINUED)
A
FOD8316
VE
VLED2+
DESAT
VDD2
VS
1
2
3
4
5
6
7
8
VIN+
16
15
14
13
12
11
10
9
B
+
–
VIN–
VE
0.1 mF
+
–
5 V
VDD1
0.1 mF
GND1
RESET
FAULT
VLED1+
100 mA
pulsed
VO
30 V
+
–
B
VO
0.1 mF
A
3 kW
100 mA
pulsed
VSS
VSS
VLED1−
*
Switch A for V
test
OH
Switch B for V test
OL
Figure 37. High Level (VOH) and Low Level (VOL) Output Voltage Test Circuit
A
FOD8316
VE
VLED2+
DESAT
VDD2
VS
1
2
3
4
5
6
7
8
VIN+
16
15
14
13
12
11
10
9
B
VIN–
+
–
5 V
VDD1
0.1 mF
IDD1
GND1
RESET
FAULT
VLED1+
VO
VSS
VSS
VLED1−
*
Switch A for I
Switch B for I
test
test
DD1H
DD1L
Figure 38. High Level (IDD1H) and Low Level (IDD1L) Supply Current Test Circuit
IE
A
FOD8316
VE
VLED2+
DESAT
VDD2
VS
1
2
3
4
5
6
7
8
VIN+
16
15
14
13
12
11
10
9
B
+
–
VIN–
VE
0.1 mF
+
–
5 V
VDD1
0.1 mF
IDD2
IS
GND1
RESET
FAULT
VLED1+
VO
+
–
30 V
VO
0.1 mF
VSS
VSS
VLED1−
*
Switch A for I
Switch B for I
, I and I test
EH
DD2H SH
, I and I test
DD2L SL
EL
Figure 39. High Level (IDD2H), Low Level (IDD2L) Output Supply Current,
High Level (ISH), Low Level (ISL) Source Current,
VE High Level (IEH), and VE Low Level (IEL) Supply Current Test Circuit
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16
FOD8316
TEST CIRCUITS (CONTINUED)
FOD8316
VE
VLED2+
DESAT
VDD2
VS
1
2
3
4
5
6
7
8
VIN+
16
15
14
13
12
11
10
9
VDESAT
ICHG/DSCHG
–
+
+
–
VIN–
VE
0.1 mF
+
–
5 V
VDD1
0.1 mF
GND1
RESET
FAULT
VLED1+
VRL
VO
IOLF
+
–
RL
30 V
VO
0.1 mF
3 kW
10 nF
VSS
VSS
VLED1−
*
Figure 40. Low Level Output Current During Fault Conditions (IOLF), Blanking Capacitor Charge Current (ICHG),
Blanking Capacitor Discharging Current (IDSCHG) and DESAT Threshold (VDESAT) Test Circuit
FOD8316
VE
VLED2+
DESAT
VDD2
VS
1
2
3
4
5
6
7
8
VIN+
16
15
14
13
12
11
10
9
VIN–
+
–
5 V
VDD1
0.1 mF
GND1
RESET
FAULT
VLED1+
DC Sweep
0 to 15 V
(100 steps)
Parameter
Analyzer
VO
+
–
VO
0.1 mF
VSS
VSS
VLED1−
*
Figure 41. Under Voltage Lockout Threshold (VUVLO) Test Circuit
F = 10 kHz
DC = 50 %
+
FOD8316
VE
VLED2+
DESAT
VDD2
VS
1
2
3
4
5
6
7
8
VIN+
16
15
14
13
12
11
10
9
–
+
VIN–
VE
–
0.1 mF
+
5 V
VDD1
0.1 mF
–
GND1
RESET
FAULT
VLED1+
VCL
VO
+
30 V
–
VO
0.1 mF
RL
3 kW
VSS
10 nF
VSS
VLED1−
*
Figure 42. Propagation Delay (tPLH, tPHL), Pulse Width Distortion (PWD),
Rise Time (tR) and Fall Time (tF) Test Circuit
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17
FOD8316
TEST CIRCUITS (CONTINUED)
Low to High
+
–
FOD8316
VE
VLED2+
DESAT
VDD2
VS
1
2
3
4
5
6
7
8
VIN+
16
15
14
13
12
11
10
9
+
–
100 pF
VIN–
VE
0.1 mF
+
5 V
VDD1
–
0.1 mF
GND1
RESET
FAULT
VLED1+
VO
+
–
30 V
VO
0.1 mF
RL
10 nF
3 kW
VSS
VFAULT
VSS
VLED1−
*
Figure 43. DESAT Sense (tDESAT(90%), tDESAT(10%)), DESAT Fault (tDESAT(FAULT)), and (tDESAT(LOW)) Test Circuit
FOD8316
VE
VLED2+
1
2
3
4
5
6
7
8
VIN+
16
15
14
13
12
11
10
9
+
–
Strobe 8 V
VIN–
VE
0.1 mF
+
–
5 V
DESAT
VDD2
VS
VDD1
0.1 mF
GND1
RESET
FAULT
VLED1+
VO
+
–
30 V
VO
0.1 mF
RL
3 kW
VFAULT
+
–
VSS
10 nF
VSS
VLED1−
*
Figure 44. Reset Delay (tRESET(FAULT)) Test Circuit
FOD8316
VE
VLED2+
DESAT
VDD2
VS
1
2
3
4
5
6
7
8
VIN+
16
15
14
13
12
11
10
9
+
–
VIN–
VE
0.1 mF
+
5 V
VDD1
–
0.1 mF
GND1
RESET
FAULT
VLED1+
VO
+
VDD2**
–
VO
0.1 mF
3 kW
VSS
VSS
VLED1−
*
**1.0 ms ramp for t
UVLO
**10 ms ramp for t
GP
Figure 45. Under Voltage Lockout Delay (tUVLO) and Time to Good Power (tGP) Test Circuit
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18
FOD8316
TEST CIRCUITS (CONTINUED)
FOD8316
VE
VLED2+
DESAT
VDD2
VS
1
2
3
4
5
6
7
8
VIN+
16
15
14
13
12
11
10
9
VIN–
5 V
25 V
VDD1
0.1 mF
0.1 mF
GND1
RESET
FAULT
VLED1+
1 kW
SCOPE
VO
10 W
VSS
300 pF
10 nF
VSS
VLED1−
*
VCM
Floating GND
Figure 46. Common Mode Low (CML) Test Circuit @ LED1 Off
FOD8316
VE
VLED2+
DESAT
VDD2
VS
1
2
3
4
5
6
7
8
VIN+
16
15
14
13
12
11
10
9
VIN–
5 V
25 V
VDD1
0.1 mF
GND1
RESET
FAULT
VLED1+
0.1 mF
1 kW
VO
SCOPE
10 W
VSS
300 pF
VSS
VLED1−
*
10 nF
VCM
Floating GND
Figure 47. Common Mode High (CMH) Test Circuit @ LED1 On
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19
FOD8316
TEST CIRCUITS (CONTINUED)
FOD8316
VE
VLED2+
DESAT
VDD2
VS
1
2
3
4
5
6
7
8
VIN+
16
15
14
13
12
11
10
9
VIN–
5 V
25 V
VDD1
0.1 mF
GND1
RESET
FAULT
VLED1+
0.1 mF
1 kW
VO
SCOPE
10 W
10 nF
VSS
300 pF
VSS
VLED1−
*
VCM
Floating GND
Figure 48. Common Mode High (CMH) Test Circuit @ LED2 Off
FOD8316
VE
VLED2+
DESAT
VDD2
VS
1
2
3
4
5
6
7
8
VIN+
16
15
14
13
12
11
10
9
VIN–
5 V
750 W
25 V
VDD1
0.1 mF
+
–
GND1
RESET
FAULT
VLED1+
9 V
0.1 mF
1 kW
VO
SCOPE
10 W
VSS
300 pF
VSS
VLED1−
*
10 nF
VCM
Floating GND
Figure 49. Common Mode Low (CML) Test Circuit @ LED2 On
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20
FOD8316
TIMING DIAGRAMS
2.5 V
0 V
2.5 V
VIN+
VIN–
tR
tF
90%
50%
10%
VO
tPLH
tPHL
Figure 50. Propagation Delay (tPLH, tPHL), Rise Time (tR), and Fall Time (tF) Timing Diagram
RESET
50%
tDESAT (LOW)
7 V
VDESAT
tRESET (FAULT)
50%
tDESAT (90%)
90%
VO
10%
tDESAT (10%)
50% (0.5 x VDD1
)
FAULT
tDESAT (FAULT)
Figure 51. Definitions for Fault Reset Input (RESET), Desaturation Voltage Input (DESAT), Output Voltage (VO),
and Fault Output (FAULT) Timing Waveforms
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21
FOD8316
APPLICATION INFORMATION
FOD8316
V
VE
VLED2+ 15
1
2
3
4
5
6
7
8
16
IN+
C3
10 mF
C2
1 mF
V
IN–
100 pF
DDESAT
VDD1
14
13
12
11
10
9
DESAT
VDD2
VS
+
–
0.1 mF
5 V
100 W
+
–
VF
GND1
RESET
FAULT
VLED1+
VLED1−
+
–
Q1
Q2
1 kW
VDD2 = 15 V
+
–
C1
1 mF
VCE
Rg
VO
3−Phase
Output
330 pF
+
–
VSS
VSS = –8 V
D1
+
–
VSS
VCE
Figure 52. Recommended Application Circuit
Functional Description
The typical application circuit is shown in Figure 52 and
the functional behavioral of the FOD8316 is illustrated by
the detailed internal schematic shown in Figure 53. This
helps explain the interaction and sequence of internal and
external signals, together with the timing diagrams.
The relationship between the inputs and output are
illustrated in the Figure 54.
During normal operation, when no fault is detected, the
FAULT output, which is an open−drain configuration, will
be latched to HIGH state. This allows the gate driver to be
controlled by the input logic signal.
Non−Inverting and Inverting Inputs
When a fault is detected, the FAULT output will be latched
to LOW state. This condition will remain until the RESET
There are two CMOS/TTL compatible inputs, V
and
IN+
V
IN−
to control the IGBT, in non−inverting and inverting
pin is also pulled low for a period longer than PW
.
RESET
configurations respectively. When V is set to LOW, V
IN−
IN+
While setting the RESET pin to a low state, the input pins
must be pulled to low to ensure an output state (V is low
controls the driver output, V , in non−inverting con−
O
IN+
figuration. When V
is set to HIGH, V
controls the
IN+
IN−
or V is HIGH).
IN−
driver output in inverting configuration.
250 mA
14
16
+
–
DESAT
VDESAT
VLED+
3
VDD1
7
Gate Drive
Optocoupler
1
VIN+
VE
2
VIN–
UVLO Comparator
6
13
12
FAULT
VDD2
VS
–
+
12 V
4
GND1
Delay
8
VLED1–
Q
11
VO
R
S
Fault Sense
Optocoupler
50x
9, 10
5 ms Pulse
5
RESET
Generator
1x
VSS
15
VLED2+
Figure 53. Detailed Internal Schematic
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22
FOD8316
Gate Driver Output
see a heavy spike on the collector, resulting in a permanent
damage to the device when it’s turned off immediately.
A pair of PMOS and NMOS transistors made up the
output driver stage, which facilitates close to rail−to−rail
output swing. This feature allows a tight control of gate
voltage during on−state and short circuit condition. The
output driver is typically capable of sinking 2 A and sourcing
2 A at room temperature. Due to the low RDS
MOSFETs, the power dissipation is reduced as compared to
those bipolar−type driver output stages. The absolute
“Under Voltage Lockout (UVLO)
Under voltage detection prevents the application of
insufficient gate voltage to the IGBT. This could be
dangerous, as it would drive the IGBT out of saturation and
into the linear operation where the losses are very high and
quickly overheats. This feature ensures proper operating of
of the
(ON)
the IGBTs. The output voltage, V , remains LOW
O
maximum rating of the output peak current, I
thus the careful selection of the gate resistor, Rg, is required
to limit the short circuit current of the IGBT.
is 3 A,
O(PEAK)
irregardless of the inputs, as long as the supply voltage,
V
DD2
− V , is less than V
. When the supply voltage
E
ULVO+
falls below V
Figure 56.
, V goes LOW, as illustrated in
ULVO−
O
As shown in Figure 53, the gate driver output is influenced
by signals from the photodetector circuitry, the UVLO
comparator, and the DESAT signals. Under no fault
condition, normal operation resumes while the supply
voltage is above the UVLO threshold, the output of the
photodetector will drive the MOSFETs of the output stage.
The logic circuitry of the output stage will ensure that the
push−pull devices will never be turned “ON” simultaneously.
When the output of the photodetector is HIGH, the output, V
will be pulled to HIGH state by turning on the PMOS. When
the output of the photodetector is LOW, V will be pulled to
LOW state by turning on the NMOS.
Time to Good Power
At initial power up, the LED is off and the output of the
gate driver should be in the LOW or OFF state. Sometimes
race conditions exist that cause the output to follow V
D
(assuming V
and V are connected externally), until all
DD2
E
of the circuits in the output IC have stabilized. This
condition can result in output transitions or transients that
are coupled to the driven IGBT. These transients can cause
the high− and low−side IGBTs to conduct shoot−through
current that can damage power semiconductor devices.
ON has introduced an initial turn−on delay, called “time
to good power”. This delay, typically 2.5 ms, is only present
during the initial power−up of the device. Once powered, the
“time to good power” delay is determined by the delay of the
UVLO circuitry. If the LED is ON during the initial turn−on
activation, low−to−high transition at the output of the gate
O
O
When V
supply goes below V
, which is the
DD2
UVLO
designated ULVO threshold at the comparator, V will be
pulled down to LOW state regardless of photodetector
output.
When desaturation is detected, V will turn off slowly as
it is pulled low by the 1XNMOS device, the input to the Fault
Sense circuitry will be latched to HIGH state and turns on the
O
O
driver will only occur 2.5 ms after the V
power is applied.
DD2
LED. When V goes below 2 V, the 50XNMOS device turns
O
Dual Supply Operation − Negative Bias at V
SS
on again, clamping the IGBT gate firmly to V . The Fault
SS
The IGBT’s off−state noise immunity can be enhanced by
providing a negative gate−to−emitter bias when the IGBT is
in the OFF state. This static off−state bias can be supplied by
connecting a separate negative voltage source between the
Sense signal will remain latched in the HIGH state until the
LED of the gate driver circuitry turns off.
Desaturation Protection, FAULT Output
V (pin 16) and V (pin 9 & 10). Figure 53 illustrates the
E
SS
Desaturation detection protection ensures the protection
of the IGBT at short circuit by monitoring the
collector−emitter voltage of the IGBT in the half bridge.
When the DESAT voltage goes up and reaches above the
threshold voltage, a short circuit condition is detected and
the driver output stage will execute a “soft” IGBT turn−off
and will be eventually driven low. This sequence is
illustrated in Figure 55. The FAULT open−drain output is
triggered active low to report a desaturation error. It could
only be cleared by activating active low by the external
controller to the RESET input.
The DESAT fault detector should be disabled for a short
time period (blanking time) before the IGBT turns on to
allow the collector voltage to fall below DESAT threshold.
This blanking period protects against false trigger of the
DESAT while the IGBT is turning on.
two distinct grounds. The primary ground reference is the
IGBT’s emitter connection. V (pin 16). The under−voltage
E
threshold and desaturation voltage detection are referenced
to the IGBT’s emitter (V ) ground.
E
The recommended application circuit, Figure 52, shows
the interconnection of the V
and V supplies. The
DD2
E
IGBT’s gate to emitter voltage is the absolute value sum of
the V supply and the V reverse bias. The negative
DD2
SS
voltage supply at V appears at the gate drive input, V ,
SS
O
when the FOD8316 is in the LOW state. When the input
drives the output high, the output voltage, V , will have the
O
potential of the V
and V .
DD2
SS
Figure 52 shows the operation with a dual or split power
supply. The Vss supply provides the negative gate bias, and
V
V
+ V supplies power to the output IC. The V and
supplies require three power supply bypass
DD2
SS SS
DD2
“Soft” Turn−Off
capacitors. These capacitors provide the low equivalent
series resistant (ESR) paths for the instantaneous gate
charging and discharging currents. Selecting capacitors with
The soft turn−off feature ensures the safe turn off of the
IGBT under fault condition. This reduces the voltage spike
on the collector of the IGBT. Without this, the IGBT would
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23
FOD8316
low ESR will optimize the available output current. C3 is a
low ESR 1812 style, 10 mF, multilayer ceramic capacitor.
This capacitor is the primary filter for the Vss and V
provide the primary gate charge and discharge paths. The
Schottky diode, D1, is connected between V and V to
E
SS
protect against a reverse voltage greater than 0.5 V.
DD2
supplies. C1 and C2 are also low ESR capacitors. They
VIN–
VIN+
VO
Figure 54. Input/Output Relationship
Normal
Operation
Fault Condition
Reset
VIN–
0 V
5 V
0 V
VIN+
Blanking
Time
RESET
VDESAT
7 V
VO
FAULT
Figure 55. Timing Relationship Among Desaturation Voltage (DESAT), Fault Output (FAULT) and
Fault Reset Input (RESET)
VIN–
5 V
0 V
VIN+
VUVLO+
VUVLO–
VDD2 − VE
VO
Figure 56. Under Voltage Lockout (UVLO) for Output Side
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24
FOD8316
REFLOW PROFILE
Max. Ramp−up Rate = 3°C/S
Max. Ramp−down Rate = 6°C/S
TP
TL
260
240
220
200
180
160
140
120
100
80
tP
Tsmax
tL
Preheat Area
Tsmin
ts
60
40
20
0
120
240
360
Time 25°C to Peak
Time (seconds)
Figure 57. Reflow Profile
Table 1.
Profile Freature
Pb−Free Assembly Profile
150°C
Temperature Minimum (T
)
smin
Temperature Maximum (T
)
200°C
smax
Time (t ) from (T
to T )
smax
60 to 120 seconds
3°C/second maximum
217°C
S
smin
Ramp−up Rate (t to t )
L
P
Liquidous Temperature (T )
L
Time (t ) Maintained Above (T )
60–150 seconds
260°C +0°C / –5°C
30 seconds
L
L
Peak Body Package Temperature
Time (t ) within 5°C of 260°C
P
Ramp−Down Rate (T to T )
6°C/second maximum
8 minutes maximum
P
L
Time 25°C to Peak Temperature
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25
FOD8316
ORDERING INFORMATION
Part Number
†
Package
Shipping
FOD8316
SOIC16 W, SO 16−Pin
(Pb−Free)
50 Units / Tube
750 Units / Tape & Reel
50 Units / Tube
FOD8316R2
FOD8316V
SOIC16 W, SO 16−Pin
(Pb−Free)
SOIC16 W, SO 16−Pin, DIN EN/IEC 60747−5−5 Option
(Pb−Free)
FOD8316R2V
SOIC16 W, SO 16−Pin, DIN EN/IEC 60747−5−5 Option
(Pb−Free)
750 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
30.All packages are lead free per JEDEC: J−STD−020B standard.
OPTOPLANAR is registered trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States
and/or other countries.
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26
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC16 W
CASE 751EN
ISSUE A
DATE 24 AUG 2021
GENERIC
MARKING DIAGRAM*
XXXX = Specific Device Code
*This information is generic. Please refer to
A
= Assembly Location
WL = Wafer Lot
= Year
WW = Work Week
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
AWLYWW
XXXXXXXXXX
XXXXXXXXXX
Y
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13751G
SOIC16 W
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
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相关型号：
FOD8318R2
2.5 A Output Current, IGBT Drive Optocoupler with Active Miller Clamp, Desaturation Detection, and Isolated Fault Sensing
FAIRCHILD
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