FOD8318R2V [ONSEMI]
2.5 A 输出电流，IGBT 驱动光耦合器，带有源米勒箝位、去饱和检测和隔离故障传感;
| 型号： | FOD8318R2V |
| 厂家： | 
ONSEMI |
| 描述： | 2.5 A 输出电流，IGBT 驱动光耦合器，带有源米勒箝位、去饱和检测和隔离故障传感 驱动 双极性晶体管 光电二极管 接口集成电路 驱动器 |
| 文件： | 总29页 (文件大小：550K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
2.5 A Output Current, IGBT
Drive Optocoupler with
Active Miller Clamp,
SOIC16 W
CASE 751EN
Desaturation Detection,
and Isolated Fault Sensing
MARKING DIAGRAM
FOD8318
ON
Description
8318
V
J
The FOD8318 is an advanced 2.5 A output current IGBT drive
optocoupler capable of driving most 1200 V / 150 A IGBTs. It is
ideally suited for fast−switching driving of power IGBTs and
MOSFETs used in motor control inverter applications and
high−performance power systems. It consists of an integrated gate
D X YY KK
8318 = Device Number, e.g., ‘8318’ for FOD8318
drive optocoupler featuring low R
CMOS transistors to drive
V
= DIN EN/IEC60747−5−5 Option (Only Appears
on Component Ordered with this Option)
= Plant code, e.g., ‘D’
DS(ON)
the IGBT from rail to rail and an integrated high−speed isolated
feedback for fault sensing. The FOD8318 has an active Miller clamp
fuction to shut off the IGBT during a high dv/dt situation without the
need of a negative supply voltage. It offers critical protection features
necessary for preventing fault conditions that lead to destructive
thermal runaway of IGBTs.
D
X
= Last−digit Year Code, e.g., ‘B’ for 2011
YY = Two−digit Work Week Ranging from ‘01’ to ‘53’
KK = Lot Traceability Code
J
= Package Assembly Code, J
®
It utilizes onsemi’s proprietary OPTOPLANAR coplanar
packaging technology and optimized IC design to achieve high noise
immunity, characterized by high common mode rejection and power
supply rejection specifications.
ORDERING INFORMATION
See detailed ordering and shipping information on page 27 of
this data sheet.
The device is housed in a compact 16−pin small outline plastic
package that meets the 8 mm creepage and clearance requirements.
Features (continued)
Features
• Extended Industrial Temperate Range,
−40°C to 100°C Temperature Range
• Safety and Regulatory Approvals
• High Noise Immunity Characterized by Common Mode Rejection
♦ 35 kV / ms Minimum Common Mode Rejection
(Vcm = 1500 V
)
peak
• 2.5 A Peak Output Current Driving Capability for Most 1200 V /
150 A IGBT
♦ UL1577, 4,243 V
for 1 min.
RMS
♦ DIN EN/IEC 60747−5−5,1,414 V
peak
Working Insulation Voltage, 8000 V
Transient Isolation Voltage Ratings
• Optically Isolated Fault Sensing Feedback
• Active Miller Clamp to Shut Off the IGBT During High dv/dt
without Needing a Negative Supply Voltage
• “Soft” IGBT Turn−off
peak
• R
of 1 W (Typ.) Offers Lower Power
DS(ON)
Dissipation
• User Configurable: Inverting, Non−inverting,
Auto−reset, Auto−shutdown
• 8 mm Creepage and Clearance Distances
• Built−in IGBT Protection
♦ Desaturation Detection
♦ Under−voltage Lock Out (UVLO) Protection
• Wide Supply Voltage Range from 15 V to 30 V
Applications
♦ Use of P−Channel MOSFETs at Output Stage Enables Output
Voltage Swing Close to the Supply Rail (Rail−to−rail Output)
• Industrial Inverter
• Induction Heating
• Isolated IGBT Drive
• 3.3 V / 5 V, CMOS/TTL−compatible Inputs
• High Speed
♦ 250 ns Max. Propagation Delay over Full Operating
Temperature Range
© Semiconductor Components Industries, LLC, 2010
1
Publication Order Number:
January, 2023 − Rev. 4
FOD8318/D
FOD8318
TRUTH TABLE
V
V
UVLO (V
– V )
DESAT Detected?
FAULT
X
V
*
IN+
IN–
DD2
E
OUT
X
X
Active
X
Yes
X
LOW
LOW
LOW
LOW
HIGH
X
X
X
X
LOW
X
LOW
X
X
X
HIGH
LOW
X
X
HIGH
Not Active
No
HIGH
*V
OUT
is always LOW with ‘clamp’ being active (gate voltage < 2 V above V ).
SS
PIN DEFINITIONS
Pin No.
Name
Description
1
2
3
4
V
V
Non−inverting gate drive control input
IN+
IN–
Inverting gate drive control input
V
DD1
Positive input supply voltage (3 V to 5.5 V)
Input ground
GND1
5
6
RESET
FAULT
Fault reset input
Fault output
7
V
V
LED 1 anode (must be left unconnected)
LED1+
8
LED 1 cathode (must be connected to ground)
Output supply voltage (negative)
Active Miller clamp supply voltage
Gate drive output voltage
LED1−
9
V
SS
10
11
12
13
14
15
16
V
CLAMP
V
O
V
S
Source of pull−up PMOS transistor
Positive output supply voltage
V
DD2
DESAT
Desaturation voltage input
V
LED2+
LED 2 anode (must be left unconnected)
Output supply voltage / IGBT emitter
V
E
VIN+
VIN–
1
2
3
4
5
6
7
8
16 VE
VLED2+
15
VDD1
14 DESAT
GND
VDD2
VS
13
12
11
10
9
RESET
FAULT
VLED1+
VO
VCLAMP
VSS
VLED1−
*
Figure 1.
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2
FOD8318
BLOCK DIAGRAM
VLED1+
7
Output IC
13
12
Input IC
VDD2
VS
3
VDD1
1
2
VIN+
VIN–
6
FAULT
11
UVLO
VO
Gate Drive
Optocoupler
LED1
4
8
GND1
VLED1–
DESAT
Shield
9
VSS
14
16
DESAT
VE
5
Fault
LED2
RESET
10
VCLAMP
Miller
Clamp
Fault Sense
Optocoupler
VSS
Shield
15
VLED2+
Figure 2. Block Diagram
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3
FOD8318
SAFETY AND INSULATION RATINGS (As per DIN EN/IEC 60747−5−5. This optocoupler is suitable for “safe electrical insulation”
only within the safety limit data. Compliance with the safety ratings shall be ensured by means of protective circuits.)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Installation Classifications per DIN VDE 0110/1.89 Table 1
For Rated Mains Voltage < 150 Vrms
−
I–IV
−
−
−
−
−
−
−
−
−
For Rated Mains Voltage < 300 Vrms
For Rated Mains Voltage < 450 Vrms
For Rated Mains Voltage < 600 Vrms
For Rated Mains Voltage < 1000 Vrms
Climatic Classification
−
−
I–IV
I–IV
−
I–IV
−
I–III
−
40/100/21
Pollution Degree (DIN VDE 0110/1.89)
Comparative Tracking Index
−
2
−
−
CTI
175
2,651
V
PR
Input to Output Test Voltage, Method b,
V
peak
V
x 1.875 = V , 100 % Production Test with t = 1 s,
IORM
PR m
Partial Discharge < 5 pC
Input to Output Test Voltage, Method a,
2,121
−
−
V
peak
V
x 1.5 = V , Type and Sample Test with t = 60 s,
IORM
PR m
Partial Discharge < 5 pC
Maximum Working Insulation Voltage
Highest Allowable Over Voltage
External Creepage
V
1,414
8,000
8
−
−
−
−
−
−
−
−
−
−
−
−
V
V
IORM
peak
V
IOTM
peak
mm
mm
mm
°C
External Clearance
8
Insulation Thickness
0.5
150
T
Safety Limit Values – Maximum Values Allowed in the Event of a Failure Case
Temperature
Case
P
Input Power
100
600
−
−
−
−
−
−
mW
mW
W
S,INPUT
P
Output Power
S,OUTPUT
R
Insulation Resistance at T , V = 500 V
10
9
IO
S
IO
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FOD8318
ABSOLUTE MAXIMUM RATINGS (T = 25°C unless otherwise noted)
A
Symbol
Parameter
Value
Unit
°C
T
Storage Temperature
Operating Temperature
Junction Temperature
−40 to +125
−40 to +100
−40 to +125
260 for 10 s
STG
OPR
T
°C
T
J
°C
T
SOL
Lead Wave Solder Temperature (No Solder Immersion)
Refer to page 26 for reflow temperature profile.
°C
I
Fault Output Current
15
3
mA
A
FAULT
I
Peak Output Current (Note 1)
Negative Output Supply Voltage (Note 2)
Positive Output Supply Voltage
Gate Drive Output Voltage
Output Supply Voltage
O(PEAK)
V – V
E
0 to 15
V
SS
V
– V
−0.5 to 35 – (V – V
)
SS
V
DD2
E
E
V
−0.5 to 35
−0.5 to 35
−0.5 to 6
V
O(peak)
V
– V
V
DD2
SS
V
Positive Input Supply Voltage
Input Voltages
V
DD1
V
IN+
, V and V
IN−
−0.5 to V
V
RESET
DD1
DD1
V
Fault Pin Voltage
−0.5 to V
V
FAULT
V
Source of Pull−up PMOS Transistor Voltage
DESAT Voltage
V
SS
+ 6.5 to V
DD2
V
S
V
V to V +25
V
DESAT
CLAMP
E
E
I
Peaking Clamping Sinking Current
Miller Clamping Voltage
1.7
A
V
−0.5 to V
100
V
CLAMP
DD2
PD
Input Power Dissipation (Note 3, 5)
Output Power Dissipation (Note 4, 5)
mW
mW
I
PD
600
O
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Maximum pulse width = 10 ms, maximum duty cycle = 0.2 %.
2. This negative output supply voltage is optional. It’s only needed when negative gate drive is implemented. A schottky diode is recommended
to be connected between V and V to protect against a reverse voltage greater than 0.5 V. Refer to application information, “Active Miller
E
SS
Clamp Function” on page 24.
3. No derating required across temperature range.
4. Derate linearly above 64°C, free air temperature at a rate of 10.2 mW/°C.
5. Functional operation under these conditions is not implied. Permanent damage may occur if the device is subjected to conditions outside
these ratings.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
−40
3
Max
+100
5.5
Unit
°C
V
T
A
Ambient Operating Temperature
Input Supply Voltage (Note 6)
Total Output Supply Voltage
Negative Output Supply Voltage
V
DD1
V
– V
15
0
30
V
DD2
SS
V – V
15
V
E
SS
V
DD2
– V
Positive Output Supply Voltage (Note 6)
15
30 – (V – V )
SS
V
E
E
V
S
Source of Pull−up PMOS Transistor Voltage
V
SS
+ 7.5
V
DD2
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. During power up or down, it is important to ensure that VIN+ remains LOW until both the input and output supply voltages reach the proper
recommended operating voltage to avoid any momentary instability at the output state. Refer to “Time to Good Power” section on page 24.
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5
FOD8318
ISOLATION CHARACTERISTICS (Apply over all recommended conditions, typical value is measured at T = 25°C)
A
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
ISO
Input−Output Isolation Voltage
T = 25°C, R.H.< 50 %, t = 1.0 min, I
< 10 mA,
4,243
−
−
V
RMS
A
I−O
50 Hz (Note 7, 8, 9)
11
R
C
Isolation Resistance
Isolation Capacitance
V
I−O
V
I−O
= 500 V (Note 7)
−
−
10
−
−
W
ISO
= 0 V, freq = 1.0 MHz (Note 7)
1
pF
ISO
7. Device is considered a two terminal device: pins 1 to 8 are shorted together and pins 9 to 16 are shorted together.
8. 4,243 V for 1−minute duration is equivalent to 5,091 V for 1−second duration.
RMS
RMS
9. The Input−Output Isolation Voltage is a dielectric voltage rating as per UL1577. It should not be regarded as an input−output continuous
voltage rating. For the continuous working voltage rating, refer to the equipment level safety specification or DIN EN/IEC 60747−5−5 Safety
and Insulation Ratings Table on page 4.
ELECTRICAL CHARACTERISTICS (Apply over all recommended conditions, typical value is measured at V
= 5 V,
DD1
V
– V = 30 V, V – V = 0 V, T = 25°C unless otherwise specified.)
DD2
SS E SS A
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Figure
V
V
,
Logic Low Input Voltages
Logic High Input Voltages
Logic Low Input Currents
−
−
0.8
V
IN+L
IN−L
,
V
RESETL
V
V
,
,
2.0
−
−
−
V
IN+H
IN−H
V
RESETH
I
, I
,
V
IN
= 0.4 V
−0.5
−0.001
mA
IN+L IN−L
RESETL
I
I
FAULT Logic Low Output Current
FAULT Logic High Output Current
High Level Output Current
V
V
V
V
V
V
V
= 0.4 V
5.0
−40
−1
12.0
0.002
−2.5
−
−
−
mA
mA
A
3, 37
37
FAULTL
FAULT
I
= V
FAULTH
FAULT
DD1
I
= V
= V
– 3 V
−
4, 9, 38
OH
O
O
O
O
O
DD2
DD2
– 6 V (Note 10)
−2.5
1
−
A
I
OL
Low Level Output Current
= V + 3 V
3
−
A
5, 39
SS
= V + 6 V (Note 11)
2.5
70
−
−
A
SS
I
Low Level Output Current During
Fault Condition
– V = 14 V
125
170
mA
6, 43
OLF
SS
V
High Level Output Voltage
Low Level Output Voltage
I
I
= –100 mA (Note 12, 13, 14) V – 1.0 V V – 0.5 V
−
V
V
7, 9, 40
OH
O
S
S
V
= 100 mA
−
0.1
0.5
8, 10,
40
OL
O
I
I
High Level Supply Current
Low Level Supply Current
V
V
V
V
= V
= 5.5 V, V = 0 V
−
−
14
2
17
3
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
11, 41
DD1H
IN+
DD1
IN–
I
= V = 0 V, V
= 5.5 V
DD1L
DD2H
IN+
IN−
DD1
High Level Output Supply Current
Low Level Output Supply Current
High Level Source Current
Low Level Source Current
= Open (Note 14)
= Open
−
1.7
1.8
0.65
0.6
−0.5
3
12, 13,
42
O
O
I
−
2.8
1.5
1.4
−
DD2L
I
I
= 0 mA
= 0 mA
−
42
42
SH
O
O
I
I
I
−
SL
EL
EH
V Low Level Supply Current
E
−0.8
−0.5
15, 42
I
V High Level Supply Current
E
−0.25
−0.25
36
−
I
Blanking Capacitor Charge Current
Blanking Capacitor Discharge Current
V
V
V
V
= 2 V (Note 14, 15)
−0.13
10
−0.33
−
14, 43
43
CHG
DESAT
I
= 7 V
DSCHG
DESAT
V
V
Under−Voltage Lockout Threshold
(Note 14)
> 5 V at 25°C
< 5 V at 25°C
10.8
9.8
11.7
10.7
1.0
12.7
11.7
−
17, 31,
44
UVLO+
O
O
V
UVLO−
UVLO
Under−Voltage Lockout Threshold
Hysteresis
At 25°C
0.4
V
HYS
V
DESAT
DESAT Threshold (Note 14)
V
DD2
– V > V
, V < 5 V
6.0
6.5
7.2
V
18, 43
E
UVLO−
O
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FOD8318
ELECTRICAL CHARACTERISTICS (Apply over all recommended conditions, typical value is measured at V
= 5 V,
DD1
V
– V = 30 V, V – V = 0 V, T = 25°C unless otherwise specified.) (continued)
DD2
SS E SS A
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Figure
V
Clamping Threshold Voltage
−
2.2
−
V
35, 54
CLAMP_
THRES
I
Clamp Low Level Sinking Current
VO = VSS + 2.5 V
0.35
1.2
−
A
34, 53
CLAMPL
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
10.Maximum pulse width = 10 ms, maximum duty cycle = 0.2 %.
11. Maximum pulse width = 4.99 ms, maximum duty cycle = 99.8 %.
12.V is measured with the DC load current in this testing (maximum pulse width = 1 ms, maximum duty cycle = 20 %). When driving capacitive
OH
loads, V approaches V as I approaches zero units.
OH
DD
OH
DD2
13.Positive output supply voltage (V
– V ) should be at least 15 V. This ensures adequate margin in excess of the maximum under−voltage
E
lockout threshold V
of 13.5 V.
UVLO+
14.When V
– V > V
and output state V of the FOD8318 is allowed to go HIGH, the DESAT detection feature is active and provides
DD2
E
UVLO O
the primary source of IGBT protection. UVLO is needed to ensure DESAT detection is functional.
15.The blanking time, t , is adjustable by an external capacitor (C ) where t = C
x (V / I
).
BLANK
BLANK
BLANK
BLANK
DESAT CHG
SWITCHING CHARACTERISTICS (Apply over all recommended conditions, typical value is measured at V
= 5 V,
DD1
V
– V = 30 V, V – V = 0 V, T = 25°C unless otherwise specified.)
DD2
SS E SS A
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Figure
t
Propagation Delay Time to Logic Low Rg = 10 W Cg = 10 nF,
−
140
250
ns
ns
ns
ns
19, 20,
21, 22,
23, 24,
45, 53
PHL
Output (Note 17)
f = 10 kHz,
Duty Cycle = 50 % (Note 16)
t
Propagation Delay Time to Logic High
Output (Note 18)
−
−
160
20
−
250
100
150
PLH
PWD
PDD Skew
Pulse Width Distortion, | t
(Note 19)
– t
PLH
|
PHL
Propagation Delay Difference
between Any Two Parts or Channels,
(t – t ) (Note 20)
–150
PHL
PLH
t
Output Rise Time (10 % – 90 %)
Output Fall Time (90 % – 10 %)
−
−
−
25
25
−
−
ns
ns
ns
45, 55
25, 46
R
t
F
t
t
DESAT Sense to 90 % V Delay
Rg = 10 W, Cg = 10 nF,
450
700
DESAT(90 %)
O
(Note 21)
V
– V = 30 V
DD2
SS
DESAT Sense to 10 % V Delay
−
−
−
3
2.7
1.4
250
6
4.0
5.0
−
ms
ms
ns
ms
26, 28,
29, 46
DESAT(10 %)
O
(Note 21)
t
DESAT Sense to Low Level FAULT
Signal Delay (Note 22)
27, 46,
56
DESAT(FAULT)
t
DESAT Sense to DESAT Low
Propagation Delay (Note 23)
46
DESAT(LOW)
FAULT
t
RESET to High Level
Delay (Note 24)
Signal
20
30, 47,
56
RESET(FAULT)
t
DESAT Input Mute
10
1.2
−
22
−
35
−
ms
ms
ms
ms
ms
DESAT(MUTE)
PW
RESET Signal Pulse Width
RESET
t
UVLO Turn On Delay (Note 25)
UVLO Turn Off Delay (Note 26)
Time to Good Power (Note 27)
V
V
= 20 V in 1.0 ms Ramp
4
−
31, 48
UVLO ON
DD2
t
−
3
−
UVLO OFF
t
= 0 to 30 V in 10 ms Ramp
−
2.5
−
32, 33,
48
GP
DD2
| CM
|
Common Mode Transient Immunity at T = 25°C, V
= 5 V,
35
35
50
50
−
−
kV/ms
kV/ms
50, 51
H
A
V
DD1
Output High
= 25 V, V = Ground,
DD2 SS
CM
V
= 1500 V
(Note 28)
peak
| CM |
Common Mode Transient Immunity at T = 25°C, V
= 5 V,
49, 52
L
A
V
DD1
Output Low
= 25 V, V = Ground,
DD2 SS
V
= 1500 V
(Note 29)
CM
peak
16.This load condition approximates the gate load of a 1200 V / 150 A IGBT.
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FOD8318
17.t
propagation delay is measured from the 50 % level on the falling edge of the input pulse (V , V ) to the 50 % level of the falling edge
IN+ IN−
PHL
of the V signal. Refer to Figure 55.
O
18.t
propagation delay is measured from the 50 % level on the rising edge of the input pulse (V , V ) to the 50 % level of the rising edge
PHL
IN+ IN−
of the V signal. Refer to Figure 55.
O
19.PWD is defined as | t
20.The difference between t
– t
PHL
| for any given device.
PLH
PHL
PLH
and t
between any two FOD8318 parts under same operating conditions, with equal loads.
21.This is the amount of time the DESAT threshold must be exceeded before V begins to go LOW. This is supply voltage dependent. Refer
O
to Figure 56.
22.This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes LOW. Refer to Figure 56.
23.This is the amount of time the DESAT threshold must be exceeded before V begins to go LOW and the FAULT output to go LOW. Refer
O
to Figure 56.
24.This is the amount of time from when RESET is asserted LOW, until FAULT output goes HIGH. Refer to Figure 56.
25.t
UVLO turn−on delay is measured from V
threshold voltage of the output supply voltage (V
) to the 5 V level of the rising
UVLO ON
UVLO+
DD2
edge of the V signal.
O
26.t
UVLO turn−off delay is measured from V
threshold voltage of the output supply voltage (V
) to the 5 V level of the falling
UVLO OFF
UVLO–
DD2
edge of the V signal.
O
27.t time to good power is measured from 13.5 V level of the rising edge of the output supply voltage (V
) to the 5 V level of the rising edge
GP
DD2
of the V signal.
O
28.Common mode transient immunity at output HIGH state is the maximum tolerable negative dVcm / dt on the trailing edge of the common mode
pulse, V , to assure that the output remains in HIGH state (i.e., V > 15 V or FAULT > 2 V).
CM
O
29.Common mode transient immunity at output LOW state is the maximum positive tolerable dVcm / dt on the leading edge of the common mode
pulse, V , to assure that the output remains in a LOW state (i.e., V < 1.0 V or FAULT < 0.8 V).
CM
O
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FOD8318
TYPICAL PERFORMANCE CHARACTERISTICS
50
40
30
20
10
0
7
6
5
V
= V
= V
− 6 V
− 3 V
O
DD2
4
3
2
1
0
V
O
DD2
V
V
I
= 5 V
= 5 V
DD1
IN+
= 10 mA
V
V
− V = 30 V
LED2+
DD2
DD1
SS
= 5 V
T = 25°C
A
0
1
2
3
4
5
−40 −20
0
20
40
60
80
100
V
, FAULT VOLTAGE (V)
T , TEMPERATURE (°C)
A
FAULTL
Figure 3. FAULT Logic Low Output Current (IFAULTL
)
Figure 4. High Level Output Current (IOH) vs.
Temperature
vs. FAULT Logic Low Output Voltage (VFAULTL
)
7
6
150
T = −40 °C
V
V
= V + 6 V
A
O
SS
125
100
75
5
4
3
2
1
0
T = 25 °C
A
T = 100 °C
A
= V + 3 V
O
SS
V
DD2
V
DD1
− V = 30 V
SS
= 5 V
V
V
− V = 30 V
DD2
DD1
SS
= 5 V
50
−40 −20
0
20
40
60
80
100
0
5
10
15
20
25
30
T , TEMPERATURE (°C)
A
V , OUTPUT VOLTAGE (V)
O
Figure 5. Low Level Output Current (IOL) vs.
Temperature
Figure 6. Low Level Output Current During Fault
Condition (IOLF) vs. Output Voltage (VOL
)
0.1
0.25
I
= −650 mA
= −100 mA
O
0.0
−0.1
−0.2
−0.3
−0.4
−0.5
0.20
0.15
0.10
0.05
0.00
I
O
I
= 100 mA
O
V
V
V
− V = 30 V
V
V
V
− V = 30 V
DD2
DD1
IN+
SS
= 5 V
= 5 V
DD2
DD1
IN+
SS
= 5 V
= 0 V
−40 −20
0
20
40
60
80
100
−40 −20
0
20
40
60
80
100
T , TEMPERATURE (°C)
A
T , TEMPERATURE (°C)
A
Figure 7. High Level Output Voltage Drop
Figure 8. Low Level Output Voltage (VOL) vs.
Temperature
(VOH − VDD) vs. Temperature
www.onsemi.com
9
FOD8318
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
30
29
28
27
26
25
4
V
DD2
V
DD1
V
IN+
− V = 30 V
= 5 V
= 0 V
SS
3
2
1
0
T = −40 °C
A
T = 100 °C
A
25 °C
25 °C
100 °C
−40 °C
V
DD2
V
DD1
V
IN+
− V = 30 V
= 5 V
= 5 V
SS
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
I
, HIGH LEVEL OUTPUT CURRENT (A)
I
OL
, LOW LEVEL OUTPUT CURRENT (A)
OH
Figure 9. High Level Output Voltage (VOH) vs.
High Level Output Current (IOH
Figure 10. Low Level Output Voltage (VOL) vs.
)
Low Level Output Current (IOL
)
2.2
2.0
1.8
1.6
1.4
1.2
1.0
20
15
10
5
V
V
= 5 V
= 0 V (I
V
V
V
− V = 30 V
= 5 V
DD1
IN+
DD2
DD1
IN+
SS
) / 5 V (I
)
DD1L
DD1H
= 0 V (I
) / 5 V (I
)
DD2L
DD2H
I
I
DD2L
I
DD1H
DD2H
I
DD1L
0
−40 −20
0
20
40
60
80
100
−40 −20
0
20
40
60
80
100
T , TEMPERATURE (°C)
A
T , TEMPERATURE (°C)
A
Figure 11. Supply Current (IDD1) vs. Temperature
Figure 12. Output Supply Current (IDD2) vs.
Temperature
2.2
−0.15
−0.20
−0.25
−0.30
V
DD1
V
IN+
= 5 V
= 0 V (I
V
V
V
V
− V = 30 V
= 5 V
= 5 V
DD2
DD1
IN+
SS
) / 5 V (I
)
DD2L
DD2H
2.0
1.8
1.6
1.4
1.2
1.0
= 0 to 6 V
DESAT
I
DD2L
I
DD2H
15
20
25
30
−40 −20
0
20
40
60
80
100
V
DD2
, OUTPUT SUPPLY VOLTAGE (V)
T , TEMPERATURE (°C)
A
Figure 13. Output Supply Current (IDD2) vs.
Output Supply Voltage (VDD2
Figure 14. Blanking Capacitor Charge Current
(ICHG) vs. Temperature
)
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10
FOD8318
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
0.0
−0.2
−0.4
−0.6
−0.8
3.0
V
V
V
− V = 30 V
SS
= 5 V
DD2
DD1
IN+
−40°C
2.5
2.0
1.5
1.0
0.5
0.0
25°C
= 0 V (I ) / 5 V (I
)
EL
EH
100°C
I
EH
I
EL
V
DD2
V
DD1
V
IN+
− V = 30 V
= 5 V
= 5 V
SS
−40 −20
0
20
40
60
80
100
0.0
0.5
1.0
1.5
2.0
T , TEMPERATURE (°C)
A
I , OUTPUT CURRENT (mA)
O
Figure 15. Supply Current (IE) vs. Temperature
Figure 16. Source Current (IS) vs.
Output Current (IO)
15
7.0
6.8
6.6
6.4
6.2
6.0
V
V
UVLO+
10
5
UVLO−
V
V
V
− V = 30 V
= 5 V
= 5 V
DD2
DD1
IN+
SS
V
V
= 5 V
= 5 V
DD1
IN+
0
−40 −20
0
20
40
60
80
100
−40 −20
0
20
40
60
80
100
T , TEMPERATURE (°C)
A
T , TEMPERATURE (°C)
A
Figure 17. Under Voltage Lockout Threshold
(VUVLO) vs. Temperature
Figure 18. DESAT Threshold (VDESAT) vs.
Temperature
0.25
0.20
0.25
0.20
0.15
0.10
0.05
t
t
PLH
t
t
PLH
0.15
0.10
0.05
PHL
PHL
V
V
− V = 30 V
= 5 V
DD2
SS
V
DD1
= 5 V
DD1
f = 10 kHz 50% Duty Cycle
R = 10 W C = 10 nF
f = 10 kHz 50% Duty Cycle
R = 10 W C = 10 nF
L
L
L
L
−40 −20
0
20
40
60
80
100
15
20
, SUPPLY VOLTAGE (V)
DD2
25
30
T , TEMPERATURE (°C)
A
V
Figure 19. Propagation Delay (tP) vs. Temperature
Figure 20. Propagation Delay (tP) vs.
Supply Voltage (VDD2
)
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11
FOD8318
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
0.20
0.18
0.16
0.14
0.12
0.18
V
− V = 30 V
V
− V = 30 V
DD2
SS
DD2 SS
f = 10 kHz 50% Duty Cycle
R = 10 W C = 10 nF
f = 10 kHz 50% Duty Cycle
R = 10 W C = 10 nF
L
L
L
L
0.16
0.14
0.12
0.10
V
V
V
= 4.5 V
= 5.0 V
= 5.5 V
V
V
V
= 4.5 V
= 5.0 V
= 5.5 V
DD1
DD1
DD1
DD1
DD1
DD1
−40 −20
0
20
40
60
80
100
−40 −20
0
20
40
60
80
100
T , TEMPERATURE (°C)
A
T , TEMPERATURE (°C)
A
Figure 21. Propagation Delay Time to Logic High
Output (tPLH) vs. Temperature
Figure 22. Propagation Delay Time to Logic Low
Output (tPHL) vs. Temperature
0.20
0.18
0.20
0.18
t
t
PLH
0.16
0.14
0.12
0.10
0.16
0.14
0.12
0.10
t
t
PLH
PHL
PHL
V
V
− V = 30 V
= 5 V
V
V
− V = 30 V
= 5 V
DD2
SS
DD2
SS
DD1
DD1
f = 10 kHz 50% Duty Cycle
R = 10 W
f = 10 kHz 50% Duty Cycle
C = 10 nF
L
L
0
20
40
60
80
100
0
10
20
30
40
50
C , LOAD CAPACITANCE (nF)
L
R , LOAD RESISTANCE (W)
L
Figure 23. Propagation Delay (tP) vs.
Load Capacitance (CL)
Figure 24. Propagation Delay (tP) vs.
Load Resistance (RL)
0.8
0.6
0.4
0.2
0.0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
V
V
V
− V = 30 V
= 5 V
= 5 V
V
V
= 5 V
= 5 V
DD2
DD1
IN+
SS
DD1
IN+
R = 10 W C = 10 nF
L
L
R = 10 W C = 10 nF
L
L
V
V
− V = 30 V
SS
DD2
− V = 15 V
DD2
SS
−40 −20
0
20
40
60
80
100
−40 −20
0
20
40
60
80
100
T , TEMPERATURE (°C)
A
T , TEMPERATURE (°C)
A
Figure 25. DESAT Sense to 90% VO Delay
(tDESAT(90%)) vs. Temperature
Figure 26. DESAT Sense to 10% VO Delay
(tDESAT(10%)) vs. Temperature
www.onsemi.com
12
FOD8318
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
1.8
1.6
1.4
1.2
1.0
0.8
10
V
V
V
− V = 30 V
= 5 V
= 5 V
V
V
= 5 V
= 5 V
DD2
DD1
IN+
SS
DD1
IN+
8
6
4
2
0
R = 10 W
L
R = 10 W C = 10 nF
L
L
V
E
− V = 0 V
SS
V
− V = 30 V
DD2
SS
V
E
− V = 15 V
SS
V
DD2
− V = 15 V
SS
−40 −20
0
20
40
60
80
100
0
5
10
15
20
25
30
T , TEMPERATURE (°C)
A
C , LOAD CAPACITANCE (nF)
L
Figure 27. DESAT Sense to Low Level FAULT
Signal Delay (tDESAT(FAULT)) vs. Temperature
Figure 28. DESAT Sense to 10% VO Delay
(tDESAT(10%)) vs. Load Capacitance (CL)
4.0
9
V
V
= 5 V
= 5 V
V
V
− V = 30 V
SS
DD1
DD2
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
= V
IN+
IN+
DD1
8
7
6
5
4
3
C = 10 nF
R = 10 W C = 10 nF
L
L
L
V
V
− V = 30 V
SS
DD2
V
= 4.5 V
DD1
− V = 15 V
DD2
SS
V
DD1
= 5.5 V
V
= 5.0 V
DD1
10
20
30
40
50
−40 −20
0
20
40
60
80
100
R , LOAD RESISTANCE (W)
L
T , TEMPERATURE (°C)
A
Figure 29. DESAT Sense to 10% VO Delay
(tDESAT(10%)) vs. Load Resistance (RL)
Figure 30. RESET to High Level FAULT Signal Delay
(tRESET(FAULT)) vs. Temperature
5.0
5
V
V
V
− V = 20 V
= 5 V
= 5 V
V
V
= 5 V
= 5 V
DD2
DD1
IN+
SS
DD1
IN+
4.5
4.0
3.5
3.0
2.5
2.0
4
3
2
1
0
f = 50 Hz 50% Duty Cycle
f = 50 Hz 50% Duty Cycle
t
UVLO ON
t
UVLO OFF
−40 −20
0
20
40
60
80
100
15
20
25
30
T , TEMPERATURE (°C)
A
V
DD2
, SUPPLY VOLTAGE (V)
Figure 31. Under Voltage Lockout Threshold Delay
(tUVLO) vs. Temperature
Figure 32. Time to Good Power (tGP) vs.
Supply Voltage (VDD2
)
www.onsemi.com
13
FOD8318
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
5
4
3
2
1
0
3.0
V
V
V
− V = 30 V
= 5 V
= 5 V
V
V
V
V
– V = 30 V
= 5 V
= 5 V
DD2
DD1
IN+
SS
DD2
SS
DD1
2.5
2.0
1.5
1.0
0.5
0
IN+
f = 50 Hz 50% Duty Cycle
= 2.5 V
CLAMP
−40 −20
0
20
40
60
80
100
−40 −20
0
20
40
60
80
100
T , TEMPERATURE (°C)
A
T , TEMPERATURE (°C)
A
Figure 33. Time to Good Power (tGP) vs.
Temperature
Figure 34. Clamp Low Level Sinking Current
(ICLAMPL) vs. Temperature
2.6
3.0
V
V
V
– V = 30 V
= 5 V
= 0 V
V
DD2
V
DD1
V
IN+
– V = 30 V
= 5 V
= 0 V
DD2
DD1
IN+
SS
SS
2.4
2.2
2.0
1.8
1.6
1.4
2.5
2.0
1.5
1.0
0.5
0
−40 −20
0
20
40
60
80
100
0
0.5
V
1.0
, CLAMP VOLTAGE (V)
CLAMP
1.5
2.0
2.5
3.0
T , TEMPERATURE (°C)
A
Figure 35. Clamping Threshold Voltage (VCLAMP
vs. Temperature
)
Figure 36. Clamp Low Level Sinking Current
(ICLAMPL) vs. Clamp Voltage (VCLAMP
)
www.onsemi.com
14
FOD8318
TEST CIRCUITS
FOD8318
VE
A
1
2
3
4
5
6
7
8
VIN+
16
15
14
13
12
11
10
9
10 mA
0.1 mF
VLED2+
DESAT
VDD2
VS
VIN–
+
–
5 V
0.1 mF
VDD1
GND1
RESET
FAULT
VLED1+
–
+
VFAULT
VO
IFAULT
VCLAMP
VSS
Switch A closed for I
Switch A opened for I
FAULTL
FAULTH
VLED1−
*
V
FAULT
V
FAULT
= 0.4 V for I
= 5.0 V for I
FAULTL
FAULTH
Figure 37. Fault Output Current (IFAULTL) and (IFAULTH) Test Circuit
FOD8318
VE
VLED2+
DESAT
VDD2
1
2
3
4
5
6
7
8
VIN+
16
15
14
13
12
11
10
9
Pulse Gen
PW = 10 ms
Period = 5 ms
+
–
+
–
VIN–
VE
0.1 mF
–
+
5 V
0.1 mF
VDD1
0.1 mF 47 mF
0.1 mF 47 mF
GND1
RESET
FAULT
VLED1+
V
O
+
–
VS
+
–
30 V
VO
3 kW
VCLAMP
VSS
VLED1−
*
Figure 38. High Level Output Current (IOH) Test Circuit
FOD8318
VE
VLED2+
DESAT
VDD2
1
2
3
4
5
6
7
8
VIN+
16
15
14
13
12
11
10
9
Pulse Gen
PW = 4.99 ms
Period = 5 ms
+
–
+
VIN–
VE
0.1 mF
–
–
+
5 V
VDD1
0.1 mF
GND1
RESET
FAULT
VLED1+
VS
+
–
0.1 mF 47 mF
30 V
VO
VO
3 kW
+
VCLAMP
VSS
–
VLED1−
*
0.1 mF 47 mF
Figure 39. Low Level Output Current (IOL) Test Circuit
www.onsemi.com
15
FOD8318
TEST CIRCUITS (Continued)
A
FOD8318
VE
VLED2+
DESAT
VDD2
1
2
3
4
5
6
7
8
VIN+
16
15
14
13
12
11
10
9
B
+
–
VIN–
VE
0.1 mF
+
–
5 V
VDD1
0.1 mF
GND1
RESET
FAULT
VLED1+
100 mA
pulsed
VS
VO
30 V
+
–
B
VO
0.1 mF
A
3 kW
100 mA
pulsed
VCLAMP
VSS
VLED1−
*
Switch A for V
test
OH
Switch B for V test
OL
Figure 40. High Level (VOH) and Low Level (VOL) Output Voltage Test Circuit
A
FOD8318
VE
VLED2+
DESAT
VDD2
1
2
3
4
5
6
7
8
VIN+
16
15
14
13
12
11
10
9
B
VIN–
+
–
5 V
VDD1
0.1 mF
IDD1
GND1
RESET
FAULT
VLED1+
VS
VO
VCLAMP
VSS
VLED1−
*
Switch A for I
Switch B for I
test
test
DD1H
DD1L
Figure 41. High Level (IDD1H) and Low Level (IDD1L) Supply Current Test Circuit
IE
A
FOD8318
VE
VLED2+
DESAT
VDD2
1
2
3
4
5
6
7
8
VIN+
16
15
14
13
12
11
10
9
B
+
–
VIN–
VE
0.1 mF
+
–
5 V
VDD1
0.1 mF
IDD2
IS
GND1
RESET
FAULT
VLED1+
VS
VO
+
–
30 V
VO
0.1 mF
VCLAMP
VSS
VLED1−
*
Switch A for I
Switch B for I
, I and I test
DD2H SH
EH
, I and I test
DD2L SL
EL
Figure 42. High Level (IDD2H), Low Level (IDD2L) Output Supply Current,
High Level (ISH), Low Level (ISL) Source Current,
VE High Level (IEH), and VE Low Level (IEL) Supply Current Test Circuit
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16
FOD8318
TEST CIRCUITS (Continued)
FOD8318
VE
16
1
2
3
4
5
6
7
8
VIN+
VDESAT
ICHG/DSCHG
–
+
+
–
VLED2+
15
VIN–
VE
0.1 mF
+
–
5 V
DESAT
VDD2
VS
VDD1
14
13
12
11
10
9
0.1 mF
GND1
RESET
FAULT
VLED1+
VRL
VO
IOLF
+
–
RL
30 V
VO
0.1 mF
3 kW
10 nF
VCLAMP
VSS
VLED1−
*
Figure 43. Low Level Output Current During Fault Conditions (IOLF), Blanking Capacitor Charge Current (ICHG),
Blanking Capacitor Discharging Current (IDSCHG), and DESAT Threshold (VDESAT) Test Circuit
FOD8318
VE
VLED2+
DESAT
VDD2
1
2
3
4
5
6
7
8
VIN+
16
15
14
13
12
11
10
9
VIN–
+
–
5 V
VDD1
0.1 mF
GND1
RESET
FAULT
VLED1+
VS
DC Sweep
0 to 15 V
(100 steps)
Parameter
Analyzer
VO
+
–
VO
0.1 mF
VCLAMP
VSS
VLED1−
*
Figure 44. Under−Voltage Lockout Threshold (VUVLO) Test Circuit
F = 10 kHz
DC = 50 %
+
–
FOD8318
VE
VLED2+
DESAT
VDD2
1
2
3
4
5
6
7
8
VIN+
16
15
14
13
12
11
10
9
+
VIN–
VE
–
0.1 mF
+
5 V
VDD1
0.1 mF
–
GND1
RESET
FAULT
VLED1+
VCL
VS
VO
+
30 V
–
VO
0.1 mF
RL
3 kW
VCLAMP
VSS
10 nF
VLED1−
*
Figure 45. Propagation Delay (tPLH, tPHL), Pulse Width Distortion (PWD),
Rise Time (tR), and Fall Time (tF) Test Circuit
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17
FOD8318
TEST CIRCUITS (Continued)
LOW to HIGH
+
–
FOD8318
VE
VLED2+
DESAT
VDD2
1
2
3
4
5
6
7
8
VIN+
16
15
14
13
12
11
10
9
+
–
100 pF
VIN–
VE
0.1 mF
+
5 V
VDD1
–
0.1 mF
GND1
RESET
FAULT
VLED1+
VS
VO
+
–
30 V
VO
0.1 mF
RL
10 nF
3 kW
VCLAMP
VSS
VFAULT
VLED1−
*
Figure 46. DESAT Sense (tDESAT(90 %), tDESAT(10 %)), DESAT Fault (tDESAT(FAULT)), and (tDESAT(LOW)) Test Circuit
FOD8318
VE
VLED2+
1
2
3
4
5
6
7
8
VIN+
16
15
14
13
12
11
10
9
+
–
Strobe 8 V
VIN–
VE
0.1 mF
+
–
5 V
DESAT
VDD2
VS
VDD1
0.1 mF
GND1
RESET
FAULT
VLED1+
VO
+
–
30 V
VO
0.1 mF
RL
3 kW
VFAULT
+
–
VCLAMP
VSS
10 nF
VLED1−
*
Figure 47. Reset Delay (tRESET(FAULT)) Test Circuit
FOD8318
VE
VLED2+
DESAT
VDD2
1
2
3
4
5
6
7
8
VIN+
16
15
14
13
12
11
10
9
+
–
VIN–
VE
0.1 mF
+
5 V
VDD1
–
0.1 mF
GND1
RESET
FAULT
VLED1+
VS
VO
+
VDD2**
–
VO
0.1 mF
3 kW
VCLAMP
VSS
VLED1−
*
**1.0 ms ramp for t
UVLO
**10 ms ramp for t
GP
Figure 48. Under−Voltage Lockout Delay (tUVLO) and Time to Good Power (tGP) Test Circuit
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18
FOD8318
TEST CIRCUITS (Continued)
FOD8318
VE
VLED2+
DESAT
VDD2
1
2
3
4
5
6
7
8
VIN+
16
15
14
13
12
11
10
9
VIN–
5 V
25 V
VDD1
0.1 mF
0.1 mF
GND1
RESET
FAULT
VLED1+
1 kW
VS
SCOPE
VO
10 W
VCLAMP
VSS
300 pF
10 nF
VLED1−
*
VCM
Floating GND
Figure 49. Common Mode Low (CML) Test Circuit at LED1 Off
FOD8318
VE
VLED2+
DESAT
VDD2
1
2
3
4
5
6
7
8
VIN+
16
15
14
13
12
11
10
9
VIN–
5 V
25 V
VDD1
0.1 mF
GND1
RESET
FAULT
VLED1+
0.1 mF
1 kW
VS
VO
SCOPE
10 W
VCLAMP
VSS
300 pF
VLED1−
*
10 nF
VCM
Floating GND
Figure 50. Common Mode High (CMH) Test Circuit at LED1 On
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19
FOD8318
TEST CIRCUITS (Continued)
FOD8318
VE
VLED2+
DESAT
VDD2
1
2
3
4
5
6
7
8
VIN+
16
15
14
13
12
11
10
9
VIN–
5 V
25 V
VDD1
0.1 mF
GND1
RESET
FAULT
VLED1+
0.1 mF
1 kW
VS
VO
SCOPE
10 W
VCLAMP
VSS
300 pF
VLED1−
*
10 nF
VCM
Floating GND
Figure 51. Common Mode High (CMH) Test Circuit at LED2 Off
FOD8318
VE
VLED2+
DESAT
VDD2
1
2
3
4
5
6
7
8
VIN+
16
15
14
13
12
11
10
9
VIN–
5 V
750 W
25 V
VDD1
0.1 mF
+
–
GND1
RESET
FAULT
VLED1+
9 V
0.1 mF
1 kW
VS
VO
SCOPE
10 W
VCLAMP
VSS
300 pF
VLED1−
*
10 nF
VCM
Floating GND
Figure 52. Common Mode Low (CML) Test Circuit at LED2 On
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20
FOD8318
TEST CIRCUITS (Continued)
FOD8318
VE
16
1
2
3
4
5
6
7
8
VIN+
+
–
VLED2+
15
VIN–
0 V
0.1 mF
+
–
5 V
0.1 mF
DESAT
14
VDD1
VDD2
13
GND1
RESET
FAULT
VLED1+
0.1 mF
VS
VO
12
11
10
9
+
–
ICLAMPL
+
–
3 kW
Pulsed
VCLAMP
VCLAMP
VSS
VLED1−
*
Figure 53. Clamp Low Level Sinking Current (ICLAMPL
)
FOD8318
S1
A
B
VE
VLED2+
DESAT
VDD2
1
2
3
4
5
6
7
8
VIN+
16
15
14
13
12
11
10
9
+
–
VIN–
+
0 V
0.1 mF
5 V
–
0.1 mF
VDD1
GND1
RESET
FAULT
VLED1+
0.1 mF
VS
+
30 V
–
50 W
VO
3 kW
Sweep from 3 V
+
VCLAMP
VSS
–
to V
CLAMP_THRES
VLED1−
*
Initially set S1 to A before connecting 3 V to clamp pin. Then switch to B before sweeping down
to get the V , clamping threshold voltage.
CLAMP_THRES
Figure 54. Clamp Pin Threshold Voltage (VCLAMP
)
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21
FOD8318
TIMING DIAGRAMS
2.5 V
0 V
2.5 V
VIN+
VIN–
tR
tF
90%
50%
10%
VO
tPLH
tPHL
Figure 55. Propagation Delay (tPLH, tPHL), Rise Time (tR), and Fall Time (tF) Timing Diagram
50%
tDESAT (LOW)
7 V
RESET
VDESAT
tRESET (FAULT)
50%
tDESAT (90%)
90%
VO
10%
tDESAT (10%)
50% (0.5 x VDD1
)
FAULT
tDESAT (FAULT)
Figure 56. Definitions for Fault Reset Input (RESET), Desaturation Voltage Input (DESAT), Output Voltage (VO),
and Fault Output (FAULT) Timing Waveforms
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22
FOD8318
APPLICATION INFORMATION
FOD8318
VIN+
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VE
VLED2+
DESAT
VDD2
CBLANK
100 pF
VIN–
1 mF
1 mF
10 mF
DDESAT
VDD1
GND1
–
+
5 V
1 kW
+
–
0.1 mF
VF
+
–
3 kW
Q1
Q2
VDD2 = 15 V
+
–
VCE
RESET
FAULT
VS
Rg
VO
3−Phase
330 pF
VLED1+
VCLAMP
VSS
Output
+
–
VLED1−
*
VCE
Figure 57. Recommended Application Circuit
Functional Description
The functional behavioral of FOD8318 is illustrated by
the detailed internal schematic shown in Figure 58. This
explains the interaction and sequence of internal and
external signals, together with the timing diagrams.
The relationship between the inputs and output are
illustrated in the Figure 59.
During normal operation, when no fault is detected, the
FAULT output, which is an open−drain configuration, is
latched to HIGH state. This allows the gate driver to be
controlled by the input logic signal.
When a fault is detected, the FAULT output is latched to
LOW state. This condition remains until the input logic is
pulled to LOW and the RESET pin is also pulled LOW for
Non−Inverting and Inverting Inputs
There are two CMOS/TTL−compatible inputs, V and
IN+
V , to control the IGBT in non−inverting and inverting
IN−
configurations, respectively. When V is set to LOW state,
IN−
V
IN+
controls the driver output, VO, in non−inverting
a period longer than PW
.
RESET
configuration. When VIN+ is set to HIGH state, V
controls the driver output in inverting configuration.
IN−
250 mA
14
16
+
–
DESAT
VDESAT
VLED+
3
VDD1
7
Gate Drive
Optocoupler
1
2
VIN+
VIN–
VE
UVLO Comparator
–
6
13
12
FAULT
GND1
VDD2
VS
+
12 V
4
Delay
8
5
11
VLED1–
VO
Q
R S
Fault Sense
Optocoupler
50x
5 ms Pulse
Generator
RESET
9, 10
1x
VSS
15
VLED2+
Figure 58. Detailed Internal Schematic
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23
FOD8318
Gate Driver Output
external capacitance (C ), FAULT threshold voltage
BLANK
A pair of PMOS and NMOS comprise the output driver
stage, which facilitates close to rail−to−rail output swing.
This feature allows a tight control of gate voltage during
on−state and short−circuit condition. The output driver is
typically to sink 2 A and source 2 A at room temperature.
(V
), and DESAT charge current (I
) as:
DESAT
tBLANK + CBLANK VDESAT ń ICHG
CHG
(eq. 1)
With a recommended 100 pF DESAT capacitor, the
nominal blanking time is:
Due to the low R
of the MOSFETs, the power
100 pF 7 V ń 250 mA + 2.8 ms
DS(ON)
dissipation is reduced as compared to those bipolar−type
driver output stages. The absolute maximum rating of the
“Soft” Turn−Off
The soft turn−off feature ensures the safe turn off of the
IGBT under fault conditions. This reduces the voltage spike
on the collector of the IGBT. Without this, the IGBT would
see a heavy spike on the collector and result in permanent
damage to the device.
output peak current, I
selection of the gate resistor, Rg, is required to limit the
short−circuit current of the IGBT.
), is 3 A; therefore the careful
O(PEAK
As shown in Figure 58, gate driver output is influenced by
signals from the photodetector circuitry, the UVLO
comparator, and the DESAT signals. Under no−fault
condition, normal operation resumes while the supply
voltage is above the UVLO threshold, the output of the
photodetector drives the MOSFETs of the output stage.
The logic circuitry of the output stage ensures that the
push−pull devices are never “ON” simultaneously. When
the output of the photodetector is HIGH, the output, V , is
pulled to HIGH state by turning on the PMOS. When the
output of the photodetector is LOW, V is pulled to LOW
state by turning on the NMOS.
Under−Voltage Lockout
Under−voltage detection prevents the application of
insufficient gate voltage to the IGBT. This could be
dangerous, as it would drive the IGBT out of saturation and
into the linear operation where the losses are very high and
quickly overheated. This feature ensures the proper
operating of the IGBTs. The output voltage, V , remains
O
O
LOW regardless of the inputs as long as the supply voltage,
V
DD2
– V , is less than V
. When the supply voltage
O
E
UVLO+
falls below V
Figure 61.
, V goes LOW, as illustrated in
UVLO−
O
When V
supply goes below V
, which is the
DD2
UVLO
designated UVLO threshold at the comparator, V is pulled
down to LOW state regardless of photodetector output.
When desaturation is detected, V turns off slowly as it is
pulled LOW by the 1XNMOS device. The input to the fault
sense circuitry is latched to HIGH state and turns on the
O
Active Miller Clamp Function
An active Miller clamp feature allows the sinking of the
Miller current to the ground or emitter of the IGBT during
a high−dV/dt situation. Instead of driving the IGBT gate to
a negative supply voltage to increase the safety margin, the
O
LED. When V goes below 2 V, the 50XNMOS device turns
O
device has a dedicated V
pin to control the Miller
CLAMP
on again, clamping the IGBT gate firmly to V . The Fault
Sense signal remains latched in the HIGH state until the
LED of the gate driver circuitry turns off.
SS
current. During turn−off, the gate voltage of the IGBT is
monitored and the V output is activated when the gate
CLAMP
voltage goes below 2 V (relative to V ). The Miller clamp
SS
Desaturation Protection, FAULT Output
NMOS transistor is then turned on and provides a low
resistive path for the Miller current. This helps prevent a
self−turn−on due to the parasitic Miller capacitor in power
Desaturation detection protection ensures the protection
of the IGBT at short−circuit by monitoring the
collector−emitter voltage of the IGBT in the half bridge.
When the DESAT voltage goes up and reaches above the
threshold voltage, a short−circuit condition is detected and
the driver output stage executes a “soft” IGBT turn−off and
is eventually driven LOW, as illustrated in Figure 60. The
FAULT open−drain output is triggered active LOW to report
a desaturation error. It is only cleared by activating active
LOW by the external controller to the RESET input with the
input logic is pulled to LOW.
The DESAT fault detector should be disabled for a short
period (blanking time) before the IGBT turns on to allow the
collector voltage to fall below DESAT threshold. This
blanking period protects against false trigger of the DESAT
while the IGBT is turning on.
switches. The clamp voltage is V + 2.5 V maximum for
OL
a Miller current up to 1200 mA. In this way, the V
CLAMP
function does not affect the turn−off characteristic. It helps
to clamp the gate to the LOW level throughout the turn−off
time. During turn−on, where the input of the driver is
activated, the V
function is disabled or opened.
CLAMP
Time to Good Power
At initial power up, the LED is off and the output of the
gate driver should be in the LOW state. Sometimes race
conditions exist that causes the output to follow the V
E
(assuming V
and V are connected externally), until all
DD2
E
of the circuits in the output IC have stabilized. This
condition can result in output transitions or transients that
are coupled to the driven IGBT. These glitches can cause the
high−side and low−side IGBTs to conduct shoot−through
current that may result in destructive damage to the power
semiconductor devices. ON has introduced a initial turn−on
The blanking time is controlled by the internal DESAT
charge current, the DESAT voltage threshold, and the
external DESAT capacitor (capacitor between DESAT and
V pin). The nominal blanking time can be calculated using
E
www.onsemi.com
24
FOD8318
delay, generally called “time−to−good power”. This delay,
If the LED is “ON” during the initial turn−on activation,
LOW−to−HIGH transition at the output of the gate driver
typically 2.5 ms, is only present during the initial power−up
of the device. Once powered, the “time−to−good power”
delay is determined by the delay of the UVLO circuitry.
only occurs 2.5 ms after the V
power is applied.
DD2
VIN–
VIN+
VO
Figure 59. Input/Output Relationship
Normal
Operation
Fault Condition
Reset
VIN–
0 V
5 V
0 V
VIN+
Blanking
Time
RESET
VDESAT
7 V
VO
FAULT
Figure 60. Timing Relationship Among DESAT, FAULT, and RESET
VIN–
5 V
0 V
VIN+
VUVLO+
VUVLO–
V
−V
E
DD2
VO
Figure 61. UVLO for Output Side
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25
FOD8318
REFLOW PROFILE
Max. Ramp−up Rate = 3°C/S
Max. Ramp−down Rate = 6°C/S
TP
TL
260
240
220
200
180
160
140
120
100
80
tP
Tsmax
tL
Preheat Area
Tsmin
ts
60
40
20
0
120
240
360
Time 25°C to Peak
Time (seconds)
Profile Freature
Temperature Minimum (T
Pb−Free Assembly Profile
150°C
)
smin
Temperature Maximum (T
)
200°C
smax
Time (t ) from (T
to T )
smax
60 − 120 seconds
3°C/second max.
217°C
S
smin
Ramp−up Rate (t to t )
L
P
Liquidous Temperature (T )
L
Time (t ) Maintained Above (T )
60 – 150 seconds
260°C +0°C / –5°C
30 seconds
L
L
Peak Body Package Temperature
Time (t ) within 5°C of 260°C
P
Ramp−down Rate (T to T )
6°C/second max.
8 minutes max.
P
L
Time 25°C to Peak Temperature
Figure 62. Reflow Profile
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26
FOD8318
ORDERING INFORMATION
Part Number
†
Package
Shipping
FOD8318
SOIC16 W, SO 16−Pin
(Pb−Free)
50 Units / Tube
750 Units / Tape & Reel
50 Units / Tube
FOD8318R2
FOD8318V
SOIC16 W, SO 16−Pin
(Pb−Free)
SOIC16 W, SO 16−Pin, DIN EN/IEC 60747−5−5 Option
(Pb−Free)
FOD8318R2V
SOIC16 W, SO 16−Pin, DIN EN/IEC 60747−5−5 Option
(Pb−Free)
750 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
30.All packages are lead free per JEDEC: J−STD−020B standard.
OPTOPLANAR is registered trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States
and/or other countries.
www.onsemi.com
27
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC16 W
CASE 751EN
ISSUE A
DATE 24 AUG 2021
GENERIC
MARKING DIAGRAM*
XXXX = Specific Device Code
*This information is generic. Please refer to
A
= Assembly Location
WL = Wafer Lot
= Year
WW = Work Week
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
AWLYWW
XXXXXXXXXX
XXXXXXXXXX
Y
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13751G
SOIC16 W
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
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A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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