FOD8384R2V [ONSEMI]
采用 Optoplanar® 宽体 SOP 5 引脚的 2.5 A 输出电流、高速、MOSFET/IGBT 栅极驱动光电耦合器;
| 型号： | FOD8384R2V |
| 厂家： | 
ONSEMI |
| 描述： | 采用 Optoplanar® 宽体 SOP 5 引脚的 2.5 A 输出电流、高速、MOSFET/IGBT 栅极驱动光电耦合器 栅极驱动 双极性晶体管 光电 |
| 文件： | 总18页 (文件大小：311K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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June 2014
FOD8384
2.5 A Output Current, High-Speed, MOSFET/IGBT Gate
Drive Optocoupler in Optoplanar® Wide-Body SOP 5-Pin
Features
Description
■ Reliable and High-Voltage Insulation with Greater
than 8 mm Creepage and Clearance Distance and
0.5 mm Internal Insulation Distance
The FOD8384 is a 2.5 A output current gate drive
optocoupler capable of driving medium-power IGBT/
MOSFETs. It is ideally suited for fast-switching driving of
power IGBT and MOSFET used in motor-control inverter
applications and high-performance power systems.
■ 2.5 A Output Current Driving Capability for Medium-
Power IGBT/MOSFET
®
– P-Channel MOSFET at Output Stage Enables
Output Voltage Swing Close to Supply Rail
The FOD8384 utilizes Fairchild’s Optoplanar coplanar
packaging technology and optimized IC design to
achieve reliable high-insulation voltage and high-noise
immunity.
■ 35 kV/µs Minimum Common Mode Rejection
■ Wide Supply Voltage Range: 15 V to 30 V
■ Fast Switching Speed Over Full Operating
It consists of an Aluminum Gallium Arsenide (AlGaAs)
Light-Emitting Diode (LED) optically coupled to an
integrated circuit with a high-speed driver for push-pull
MOSFET output stage. The device is housed in a wide
body, 5-pin, small-outline, plastic package.
Temperature Range
– 210 ns Maximum Propagation Delay
– 65 ns Maximum Pulse-Width Distortion
■ Under-Voltage Lockout (UVLO) with Hysteresis
■
Extended Industrial Temperate Range: -40°C to 100°C
■ Safety and Regulatory Approvals:
– UL1577, 5,000 VAC for 1 Minute
Functional Schematic
RMS
– DIN-EN/IEC60747-5-5, 1,414 V Peak Working
Insulation Voltage
V
V
V
1
6
5
4
ANODE
DD
O
Applications
■ AC and Brushless DC Motor Drives
■ Industrial Inverter
■ Uninterruptible Power Supply
■ Induction Heating
3
CATHODE
SS
■ Isolated IGBT/Power MOSFET Gate Drive
Related Resources
Figure 1. Schematic
■ FOD3184—3 A Output Current, High-Speed
MOSFET/IGBT Gate Drive Optocoupler Datasheet
■ www.fairchildsemi.com/products/opto/
Figure 2. Package Outline
©2014 Fairchild Semiconductor Corporation
FOD8384 Rev. 1.0.0
www.fairchildsemi.com
Truth Table
V
– V “Positive Going”
V
V
“Positive Going”
(Turn-off)
DD
SS
DD– SS
V
LED
(Turn-on)
O
Off
On
On
On
0 V to 30 V
0 V to 11.5 V
11.5 V to 14.5 V
14.5 V to 30 V
0 V to 30 V
0 V to 10 V
LOW
LOW
10 V to 13 V
13 V to 30 V
Transition
HIGH
Pin Configuration
1
6
V
ANODE
DD
5
V
V
O
3
4
CATHODE
SS
Figure 3. Pin Configuration
Pin Definitions
Pin #
Name
Description
1
3
4
5
6
Anode
Cathode
LED Anode
LED Cathode
V
Negative Supply Voltage
Output Voltage
SS
V
O
V
Positive Supply Voltage
DD
©2014 Fairchild Semiconductor Corporation
FOD8384 Rev. 1.0.0
www.fairchildsemi.com
2
Safety and Insulation Ratings
As per DIN EN/IEC60747-5-5, this optocoupler is suitable for “safe electrical insulation” only within the safety limit
data. Compliance with the safety ratings shall be ensured by means of protective circuits.
Symbol
Parameter
Min.
Typ.
Max. Unit
Installation Classifications per DIN VDE 0110/1.89 Table 1
For Rated Mains Voltage < 150 V
For Rated Mains Voltage < 300 V
For Rated Mains Voltage < 450 V
For Rated Mains Voltage < 600 V
Climatic Classification
I–IV
I–IV
RMS
RMS
RMS
RMS
I–IIII
I–III
40/100/21
2
Pollution Degree (DIN VDE 0110/1.89)
Comparative Tracking Index
CTI
175
V
Input-to-Output Test Voltage, Method b, V
x 1.875 = V ,
PR
2651
PR
IORM
100% Production Test with t = 1 s, Partial Discharge < 5 pC
m
Input-to-Output Test Voltage, Method a, V
x 1.6 = V
,
2262
IORM
PR
Type and Sample Test with t = 10 s, Partial Discharge < 5 pC
m
V
Maximum Working Insulation Voltage
Highest Allowable Over Voltage
External Creepage
1414
8000
8.0
V
V
IORM
peak
V
IOTM
peak
mm
mm
mm
External Clearance
8.0
Insulation Thickness
0.5
Safety Limit Values – Maximum Values Allowed in the
Event of a Failure
T
Case Temperature
Input Current
150
200
600
°C
mA
mW
Ω
S
I
S,INPUT
P
Output Power
S,OUTPUT
9
R
Insulation Resistance at T , V = 500 V
10
IO
S
IO
©2014 Fairchild Semiconductor Corporation
FOD8384 Rev. 1.0.0
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only. T = 25ºC unless otherwise specified.
A
Symbol
Parameter
Value
Units
T
Storage Temperature
-40 to +125
-40 to +100
-40 to +125
260 for 10 s
°C
°C
°C
°C
STG
T
Operating Temperature
OPR
T
Junction Temperature
J
T
Lead Solder Temperature
Refer to Reflow Temperature Profile on page 15.
Average Input Current
SOL
I
25
5.0
mA
V
F(AVG)
V
Reverse Input Voltage
R
(1)
I
Peak Output Current
3.0
A
O(PEAK)
V
– V
Supply Voltage
-0.5 to 35
V
DD
SS
V
Peak Output Voltage
0 to V
45
V
O(PEAK)
DD
(2)(4)
PD
Input Power Dissipation
mW
mW
I
(3)(4)
PD
Output Power Dissipation
500
O
Notes:
1. Maximum pulse width = 10 µs, maximum duty cycle = 0.2%.
2. No derating required across operating temperature range.
3. Derate linearly from 25°C at a rate of 5.2 mW/°C.
4. Functional operation under these conditions is not implied. Permanent damage may occur if the device is subjected
to conditions outside these ratings.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Min.
Max.
Unit
T
Ambient Operating Temperature
Supply Voltage
-40
15
10
0
100
30
°C
V
A
V
– V
DD
SS
I
Input Current (ON)
16
mA
V
F(ON)
V
Input Voltage (OFF)
0.8
F(OFF)
©2014 Fairchild Semiconductor Corporation
FOD8384 Rev. 1.0.0
www.fairchildsemi.com
4
Isolation Characteristics
Apply over all recommended conditions; typical value is measured at T = 25ºC.
A
Symbol
Parameter
Conditions
Min.
Typ.
Max. Units
V
Input-Output Isolation
Voltage
T = 25ºC, R.H. < 50%, t = 60 s,
5,000
V
RMS
ISO
A
(5)(6)
I
≤ 20 µA, 50 Hz
I-O
(5)
11
R
C
Isolation Resistance
Isolation Capacitance
V
= 500 V
I-O
10
Ω
ISO
(6)
V
= 0 V, Frequency = 1.0 MHz
1
pF
ISO
I-O
Notes:
5. Device is considered a two-terminal device: pins 1 and 3 are shorted together and pins 4, 5 and 6 are shorted
together.
6. 5,000 VAC
for 1 minute duration is equivalent to 6,000 VAC
for 1 second duration.
RMS
RMS
Electrical Characteristics
Apply over all recommended conditions, typical value is measured at V = 30 V, V = Ground, T = 25°C unless
DD
SS
A
otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units Figure
V
Input Forward Voltage
I = 10 mA
1.10
1.43
-1.5
1.80
V
19
F
F
Δ(V / T )
Temperature Coefficient
of Forward Voltage
mV/°C
F
A
BV
Input Reverse
I
= 10 µA
5
V
R
R
Breakdown Voltage
C
Input Capacitance
f = 1 MHz, V = 0 V
60
pF
A
IN
F
I
High Level Output
V
V
V
V
= V – 1 V
-0.9
-0.5
-2.5
4, 6
4, 6, 22
7, 9
OH
OH
OH
OL
OL
DD
(1)
Current
= V – 6 V
A
DD
I
Low Level Output
= V + 1 V
0.5
2.5
1.0
A
OL
SS
(1)
Current
= V + 6 V
A
7, 9, 21
4
SS
V
High Level Output
Voltage
I = 10 mA, I = -2.5 A
V
V
– 7.0
V
OH
F
O
DD
DD
(7)(8)
I = 10 mA, I = -100 mA
– 0.5
V
4, 5, 23
7
F
O
V
Low Level Output
I = 0 mA, I = 2.5 A
V
V
+ 7.0
+ 0.5
V
OL
F
O
SS
SS
(7)(8)
Voltage
I = 0 mA, I = 100 mA
V
8, 24
F
O
I
High Level Supply
Current
V
= Open,
2.9
2.8
3.1
3.5
mA
10, 11,
25
DDH
O
I = 7 to 16 mA
F
I
Low Level Supply
Current
V
Open,
3.5
7.5
mA
mA
V
10, 11,
26
DDL
O =
V = 0 to 0.8 V
F
I
Threshold Input Current
Low-to-High
I
I
= 0 mA, V > 5 V
12, 18,
27
FLH
O
O
O
V
Threshold Input Voltage
High-to-Low
= 0 mA, V < 5 V
0.8
28
FHL
O
V
Under-Voltage Lockout
Threshold
I = 10 mA, V > 5 V
11.5
10.0
13.0
11.5
1.5
14.5
13.0
V
V
V
20, 29
20, 29
UVLO+
F
O
V
I = 10 mA, V < 5 V
F O
UVLO-
UVLO
Under-Voltage Lockout
Threshold Hysteresis
HYS
Notes:
7. In this test, V is measured with a dc load current of 100 mA. When driving capacitive load V will approach V
OH
OH
DD
as I approaches 0 A.
OH
8. Maximum pulse width = 1 ms, maximum duty cycle = 20%.
©2014 Fairchild Semiconductor Corporation
FOD8384 Rev. 1.0.0
www.fairchildsemi.com
5
Switching Characteristics
Apply over all recommended conditions, typical value is measured at V = 30 V, V = Ground, T = 25°C unless
DD
SS
A
otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ.
Max. Units Figure
t
Propagation Delay Time to Logic I = 7 mA to 16 mA,
50
145
135
25
210
ns
ns
ns
13, 14,
15, 16,
17, 30
PHL
PLH
F
(9)
LOW Output
Rg = 10 Ω, Cg =10 nF,
f = 250 kHz,
Duty Cycle = 50%
t
Propagation Delay Time to Logic
HIGH Output
50
210
13, 14,
15, 16,
17, 30
(10)
(11)
PWD
Pulse Width Distortion
65
90
| t
– t
|
PHL
PLH
PDD
(Skew)
Propagation Delay Difference
-90
(12)
Between Any Two Parts
t
Output Rise Time
(10% to 90%)
35
25
ns
ns
30
30
R
t
Output Fall Time
(90% to 10%)
F
t
ULVO Turn-On Delay
ULVO Turn-Off Delay
I = 10 mA, V > 5 V
1.7
0.1
50
µs
µs
ULVO ON
F
O
t
I = 10 mA, V < 5 V
F O
ULVO OFF
| CM |
Common Mode Transient
Immunity at Output HIGH
T = 25°C, V = 30 V,
35
35
kV/µs
31
31
H
A
DD
I = 10 to 16 mA,
F
(13)
V
= 1500 V
CM
| CM |
Common Mode Transient
Immunity at Output LOW
T = 25°C, V = 30 V,
50
kV/µs
L
A
DD
(14)
V = 0 V, V
= 1500 V
F
CM
Notes:
9. Propagation delay t
is measured from the 50% level on the falling edge of the input pulse to the 50% level of the
PHL
falling edge of the V signal.
O
10. Propagation delay t
is measured from the 50% level on the rising edge of the input pulse to the 50% level of the
PLH
rising edge of the V signal.
O
11. PWD is defined as | t
– t
| for any given device.
PHL
PLH
12. The difference between t
equal loads.
and t
between any two FOD8384 parts under the same operating conditions, with
PHL
PLH
13. Common mode transient immunity at output high is the maximum tolerable negative dVcm/dt on the trailing edge of
the common mode impulse signal, V , to ensure that the output remains high (i.e., V > 15.0 V).
CM
O
14. Common mode transient immunity at output low is the maximum tolerable positive dVcm/dt on the leading edge of
the common pulse signal, V , to ensure that the output remains low (i.e., V < 1.0 V).
CM
O
©2014 Fairchild Semiconductor Corporation
FOD8384 Rev. 1.0.0
www.fairchildsemi.com
6
Typical Performance Characteristics
0
-0.05
-0.10
-0.15
-0.20
-0.25
-0.30
0
-0.5
-1.0
-1.5
T
= -40°C
A
-2.0
-2.5
-3.0
-3.5
-4.0
25°C
100°C
V
V
= 15 V to 30 V
= 0 V
= 10 mA to 16 mA
= -100mA
DD
SS
V
V
= 15 V to 30 V
= 0 V
= 10 mA to 16 mA
DD
SS
I
I
F
O
I
F
f = 200 Hz 0.2% Duty Cycle
-40
-20
0
20
40
60
80
100
0
0.5 1.0
1.5
2.0
2.5
TA – AMBIENT TEMPERATURE (°C)
IOH – OUTPUT HIGH CURRENT (A)
Figure 5. Output High Voltage Drop
vs. Ambient Temperature
Figure 4. Output High Voltage Drop
vs. Output High Current
4
3
2
1
0
8
7
6
5
4
3
2
1
0
V
V
= 15 V to 30 V
= 0 V
= 0 mA
DD
SS
V
V
= 15 V to 30 V
= 0 V
= 10 mA to 16mA
DD
SS
I
F
I
F
f = 200 Hz 99.8% Duty Cycle
f = 200Hz 0.2% Duty Cycle
T
A
= -40°C
25°C
V
= V
– 6 V
DD
O
100°C
V
= V
– 1 V
DD
O
0
0.5
1.0
1.5
2.0
2.5
-40
-20
0
20
40
60
80
100
IOL – OUTPUT LOW CURRENT (A)
TA – AMBIENT TEMPERATURE (°C)
Figure 7. Output Low Voltage
vs. Output Low Current
Figure 6. Output High Current
vs. Ambient Temperature
0.25
8
7
6
5
4
3
2
1
0
V
DD
V
SS
= 15 V to 30 V
= 0 V
V
V
V
= 15 V to 30 V
= 0 V
= 0 V or 0.8 V
= 100 mA
DD
SS
F
I
F
= 0 mA
0.20
0.15
0.10
0.05
0
f = 200 Hz 99.8% Duty Cycle
I
O
V
V
= V
+ 6 V
DD
O
= V + 1 V
DD
O
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
TA – AMBIENT TEMPERATURE (°C)
TA – AMBIENT TEMPERATURE (°C)
Figure 8. Output Low Voltage
vs. Ambient Temperature
Figure 9. Output Low Current
vs. Ambient Temperature
©2014 Fairchild Semiconductor Corporation
FOD8384 Rev. 1.0.0
www.fairchildsemi.com
7
Typical Performance Characteristics (Continued)
3.6
3.6
3.2
2.8
2.4
2.0
I
F
I
F
= 10 mA (for I
= 0 mA (for I
)
V
V
I
= 30 V
= 0 V
= 10 mA (for I
= 0 mA (for I
DDH
)
DD
SS
F
DDL
V
T
= 0 V
= 25°C
)
SS
A
DDH
)
I
F
DDL
3.2
2.8
2.4
2.0
I
DDH
I
DDH
I
DDL
I
DDL
-40
-20
0
20
40
60
80
100
15
20
25
30
TA – AMBIENT TEMPERATURE (°C)
VDD – SUPPLY VOLTAGE (V)
Figure 10. Supply Current
vs. Ambient Temperature
Figure 11. Supply Current
vs. Supply Voltage
5.0
4.5
4.0
3.5
3.0
2.5
2.0
400
300
200
100
0
I
R
C
= 10 mA
V
V
= 15 V to 30 V
= 0 V
F
DD
SS
= 10 Ω
= 10 nF
g
g
Output = Open
T
= 25°C
A
f = 10 kHz 50% Duty Cycle
t
PHL
t
PLH
-40
-20
0
20
40
60
80
100
15
18
21
24
27
30
TA – AMBIENT TEMPERATURE (°C)
VDD – SUPPLY VOLTAGE (V)
Figure 13. Propagation Delay
vs. Supply Voltage
Figure 12. Low-to-High Input Current Threshold
vs. Ambient Temperature
400
400
300
200
100
0
V
V
= 30 V
= 0 V
V
V
= 30 V
= 0 V
DD
SS
DD
SS
f = 10 kHz 50% Duty Cycle
R
C
I = 10 mA
F
= 10 Ω
= 10 nF
= 25°C
f = 10 kHz 50% Duty Cycle
R
C
g
g
300
200
100
0
= 10 Ω
= 10 nF
g
g
T
A
t
PHL
t
PHL
t
PLH
t
PLH
6
8
10
12
14
16
-40
-20
0
20
40
60
80
100
IF – FORWARD LED CURRENT (mA)
TA – AMBIENT TEMPERATURE (°C)
Figure 15. Propagation Delay
vs. Ambient Temperature
Figure 14. Propagation Delay
vs. LED Forward Current
©2014 Fairchild Semiconductor Corporation
FOD8384 Rev. 1.0.0
www.fairchildsemi.com
8
Typical Performance Characteristics (Continued)
400
400
300
200
100
0
V
DD
V
SS
= 30 V
= 0 V
V
DD
V
SS
= 30 V
= 0 V
I
F
= 10 mA
I = 10 mA
F
f = 250 kHz 50% Duty Cycle
f = 250 kHz 50% Duty Cycle
300
200
100
0
C
= 10 nF
R
= 10 Ω
= 25°C
g
g
T
A
= 25°C
T
A
t
PHL
t
PHL
t
PLH
t
PLH
0
10
20
30
40
50
0
20
40
60
80
100
Rg – SERIES LOAD RESISTANCE (Ω)
Cg – LOAD CAPACITANCE (nF)
Figure 16. Propagation Delay
vs. Series Load Resistance
Figure 17. Propagation Delay
vs. Load Capacitance
35
30
25
20
15
10
5
100
10
V
= 30 V
DD
= 25°C
T
A
100°C
-40°C
25°C
1
0.1
0.01
0.001
0
0
1
2
3
4
5
0.6
0.8
1.0
1.2
1.4
1.6
1.8
IF – FORWARD LED CURRENT (mA)
VF – FORWARD VOLTAGE (V)
Figure 18. Transfer Characteristics
Figure 19. Input Forward Current
vs. Forward Voltage
14
I
F
= 10 mA
T
A
= 25°C
12
10
8
V
= 11.74 V
V
UVLO
= 13.33 V
UVLO
6
4
2
0
0
5
10
15
20
V
–V – SUPPLY VOLTAGE (V)
DD SS
Figure 20. Under-Voltage Lockout
©2014 Fairchild Semiconductor Corporation
FOD8384 Rev. 1.0.0
www.fairchildsemi.com
9
Test Circuit
Power Supply
+
+
V
= 15 V to 30 V
+
DD
C2
47 μF
C1
0.1 μF
Pulse Generator
PW = 4.99 ms
Period = 5 ms
Pulse-In
R
= 50 Ω
OUT
1
6
5
4
I
OL
R2
100 Ω
Power Supply
V = 6 V
+
C4
47 μF
C3
0.1 μF
D1
VOL
3
LED-IFmon
To Scope
R1
100 Ω
Test Conditions:
Frequency = 200 Hz
Duty Cycle = 99.8%
V
V
= 15 V to 30 V
= 0 V
DD
SS
I
F
= 0 mA
Figure 21. I Test Circuit
OL
Power Supply
+
V
= 15 V to 30 V
+
DD
C2
47 μF
C1
0.1 μF
Pulse Generator
PW = 10 μs
Period = 5 ms
Pulse-In
R
= 50 Ω
OUT
+
–
1
6
Power Supply
V = 6 V
+
C4
47 μF
C3
I
OH
0.1 μF
R2
100 Ω
5
4
D1
VOH
Current
Probe
3
LED-IFmon
To Scope
R1
100 Ω
Test Conditions:
Frequency = 200 Hz
Duty Cycle = 0.2%
V
DD
V
SS
= 15 V to 30 V
= 0 V
I
F
= 10 mA to 16 mA
Figure 22. I Test Circuit
OH
©2014 Fairchild Semiconductor Corporation
FOD8384 Rev. 1.0.0
www.fairchildsemi.com
10
Test Circuit (Continued)
1
6
5
4
0.1 μF
+
–
V
V
= 15 V to 30 V
O
DD
I
= 10 mA to 16 mA
F
100 mA
3
Figure 23. V Test Circuit
OH
1
3
6
0.1 μF
100 mA
+
–
V
= 15 V to 30 V
DD
V
O
5
4
Figure 24. V Test Circuit
OL
1
6
5
4
0.1 μF
+
–
V
= 30 V
I
= 10 mA to 16 mA
V
O
DD
F
3
Figure 25. I
Test Circuit
DDH
1
6
5
4
0.1 μF
+
–
V
= 30 V
DD
+
–
V
V
= 0 V to 0.8 V
O
F
3
Figure 26. I
Test Circuit
DDL
©2014 Fairchild Semiconductor Corporation
FOD8384 Rev. 1.0.0
www.fairchildsemi.com
11
Test Circuit (Continued)
1
3
6
5
4
0.1 μF
+
–
V
= 15 V to 30 V
DD
V
> 5 V
O
IF
Figure 27. I
Test Circuit
FLH
1
3
6
5
4
0.1 μF
+
–
+
–
V
O
V
= 15 V to 30 V
V
= 0 V to 0.8 V
DD
F
Figure 28. V
Test Circuit
FHL
1
3
6
5
4
0.1 μF
+
–
15 V or 30 V
V
= 5 V
I
= 10 mA
O
F
V
Ramp
DD
Figure 29. UVLO Test Circuit
©2014 Fairchild Semiconductor Corporation
FOD8384 Rev. 1.0.0
www.fairchildsemi.com
12
Test Circuit (Continued)
1
3
6
5
4
0.1 μF
V
O
+
–
V
= 15 V to 30 V
+
–
DD
Rg = 10 Ω
Probe
f = 10 kHz
DC = 50%
Cg = 10 nF
50 Ω
I
F
t
t
F
R
90%
50%
10%
V
OUT
t
t
PHL
PLH
Figure 30. t
, t
, t , and t Test Circuit and Waveforms
PHL PLH R F
I
F
A
1
6
5
4
B
0.1 μF
+
–
+
–
V
5 V
O
V
= 30 V
DD
3
+ –
= 1500 V
V
CM
V
CM
0V
V
Δt
V
O
O
OH
Switch at A: I = 10 mA
F
V
V
OL
Switch at B: I = 0 mA
F
Figure 31. CMR Test Circuit and Waveforms
©2014 Fairchild Semiconductor Corporation
FOD8384 Rev. 1.0.0
www.fairchildsemi.com
13
Reflow Profile
Max. Ramp-up Rate = 3°C/S
Max. Ramp-down Rate = 6°C/S
T
P
260
240
220
200
180
160
140
120
100
80
t
P
T
L
Tsmax
t
L
Preheat Area
Tsmin
t
s
60
40
20
0
120
Time 25°C to Peak
240
360
Time (seconds)
Profile Freature
Pb-Free Assembly Profile
150°C
Temperature Minimum (T
)
smin
Temperature Maximum (T
)
200°C
smax
Time (t ) from (T
to T )
smax
60 s to 120 s
S
smin
Ramp-up Rate (t to t )
3°C/second maximum
217°C
L
P
Liquidous Temperature (T )
L
Time (t ) Maintained Above (T )
60 s to 150 s
L
L
Peak Body Package Temperature
Time (t ) within 5°C of 260°C
260°C +0°C / –5°C
30 s
P
Ramp-Down Rate (T to T )
6°C/s maximum
8 minutes maximum
P
L
Time 25°C to Peak Temperature
Figure 32. Reflow Profile
©2014 Fairchild Semiconductor Corporation
FOD8384 Rev. 1.0.0
www.fairchildsemi.com
14
Ordering Information
Part Number
Package
Packing Method
Tube (100 units per tube)
FOD8384
Wide Body SOP 5-Pin
Wide Body SOP 5-Pin
FOD8384R2
FOD8384V
FOD8384R2V
Tape and Reel (1,000 units per reel)
Wide Body SOP 5-Pin, DIN EN/IEC60747-5-5 Option Tube (100 units per tube)
Wide Body SOP 5-Pin, DIN EN/ IEC60747-5-5 Option Tape and Reel (1,000 units per reel)
All packages are lead free per JEDEC: J-STD-020B standard.
Marking Information
1
2
3
V
8384
8
D X YY KK W
6
4
5
7
Definitions
1
2
3
Fairchild logo
Device number, e.g., ‘8384’ for FOD8384
DIN EN/IEC60747-5-5 Option (only appears on
component ordered with this option)
4
5
6
7
8
Plant code, e.g., ‘D’
Last digit year code, e.g., ‘C’ for 2012
Two-digit work week ranging from ‘01’ to ‘53’
Lot traceability code
Package assembly code, W
©2014 Fairchild Semiconductor Corporation
FOD8384 Rev. 1.0.0
www.fairchildsemi.com
15
0.60
4.15
3.15
6
4
1.27
A
2.05
4.33
D
6
4
1.27
11.80
10.80
9.30
8.30
2.54
1
3
LAND PATTERN
RECOMMENDATION
3
1
0.33 C
5 TIPS
PIN ONE
2.54
INDICATOR
0.51
0.31
B
5X
0.25
C A-B D
SEATING
PLANE
2.65
2.45
A
0.10 C
2.95 MAX
0.10 C
0.30
0.10
5X
C
NOTES: UNLESS OTHERWISE SPECIFIED
(1.25)
A) THIS PACKAGE DOES NOT
CONFORM TO ANY STANDARD.
B) ALL DIMENSIONS ARE IN
MILLIMETERS.
(R0.54)
C) DIMENSIONS ARE EXCLUSIVE OF
BURRS, MOLD FLASH AND TIE BAR
PROTRUSIONS
D) DRAWING CONFORMS TO ASME
Y14.5M-1994
GAUGE
PLANE
0.25
0.19
8°
0°
E) DRAWING FILE NAME:
MKT-M05BREV2
1.04
0.44
0.25
(R1.29)
C
SEATING
PLANE
SCALE: 3.2:1
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