FPF2260ATMX [ONSEMI]
Over-Voltage/Under-Voltage Protection controller with negative voltage protection;
| 型号： | FPF2260ATMX |
| 厂家： | 
ONSEMI |
| 描述： | Over-Voltage/Under-Voltage Protection controller with negative voltage protection |
| 文件： | 总9页 (文件大小：489K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
28 V Rated OVLO/UVLO
Controller with Negative
Stress Protection
FPF2260ATMX
Description
FPF2260ATMX is an OVP and UVLO controller with reverse /
negative voltage protection. The device controls and drives a pair of
external N−MOSFET that can operate over an input voltage range of
2.8 V to 23 V. In that way, with OVP feature implemented, the system
can allow huge current as long as the external MOSFET can handle.
When the input voltage exceeds the over−voltage threshold or lower
than under−voltage threshold, the external FET is turned off
immediately to prevent damage to the protected downstream
components.
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When the input voltage is stressed a negative voltage, the external
FET will also be turned off and prevent OUT dropping to negative
voltage.
X2QFN12 1.6x1.6, 0.4P
CASE 722AG
FPF2260ATMX is available in a small X2QFN12 package and
operate over the free−air temperature range of −40°C to +85°C.
MARKING DIAGRAM
Features
• Over−voltage Protection Up to 28V
1
6BKK
_XYZ
• Programmable Over−voltage Lockout (OVLO)
♦ Externally Adjustable via OVLO Pin
♦ Default OVLO Level without Additional Components
• Programmable Under−voltage Lockout (UVLO)
♦ Externally Adjustable via UVLO Pin
6B = Specific Device Code
KK = 2−Digits Lot Run Traceability Code
_
= Pin 1 Identifier
XY = 2−Digit Date Code
• Active−high Enable Pin (EN) for Device
Z
= Assembly Pant Code
• Super−fast OVLO Response Time: Typical 150 ns
• Negative Voltage Blocking
PIN CONNECTIONS
• Short Circuit Protection and Auto−restart
• Selectable Gate Driver Voltage
• USB OTG Support Mode
• Open−Drain Output Indicators
12
11
10
9
♦ OVFLGB for Over Voltage Stress
♦ UVFLAG for Under Voltage Lockout
1
2
8
7
GND
OVFLGB
UVFLAG
• Robust ESD Performance
OVLO
♦ 2 kV Human Body Model (HBM)
♦ 1 kV Charged Device Model (CDM)
3
4
5
6
Typical Applications
• Mobile Phones
• PDAs
• Notebooks
• Desktops
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information on page 7 of
this data sheet.
© Semiconductor Components Industries, LLC, 2020
1
Publication Order Number:
July, 2020 − Rev. 3
FPF2260ATMX/D
FPF2260ATMX
HV Battery
Charger
NTTFSC02N NTTFSC02N
VBUS
Travel
Adapter
1 mF
1 mF
GT1
GT2
OUT
EN
IN
Legacy USB /
USB Type C connector
R1
R2
FPF2260A
UVLO
OVLO
OVFLGB
UVFLAG
Processor
RPU
RPU
GND
GT_CON TRCB
R3
VIO
VIO
Figure 1. Schematic − Adjustable Option
IN
OUT
GT1
GT2
Gate Driver, Charge Pump,
Bandgap, Oscillator
UVLO
OVP
UVLO
OVLO
OVFLGB
UVFLAG
LOGIC
GT_CON
EN
TRCB
GND
Figure 2. Simplified Block Diagram
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2
FPF2260ATMX
PIN FUNCTION DESCRIPTION
Pin No.
Name
GND
OVLO
IN
Description
1
2
3
4
5
6
7
Ground
OVLO Input: Over Voltage Lockout Adjustment Input
Power Input: External FET Input and Device Supply
Gate 1 Output:
GT1
GT2
Gate 2 Output:
OUT
Power Output: External FET Output and Device Supply(More Description)
UVFLAG
UVLO Flag Output: Open−drain output, turn ON the internal MOS to pull down this pin to indicate no
Under−Voltage condition on IN
8
OVFLGB
OVP Flag Output: Open−drain output, turn ON the internal MOS to pull down this pin to indicate
Over−Voltage condition on IN
9
EN
Enable Input: Active HIGH with internal 500 kW pull down resistor
10
GT_CON
Gate Voltage Control Input: VGS select Pin 0: Vgs = 12 V; 1/floating: Vgs = 6V with internal 500 kW
pull up resistor
11
12
UVLO
TRCB
UVLO Input: Under Voltage Lockout Adjustment Input
True RCB Enable Input: 0: no TRCB; 1/floating: Block Reverse Current Entirely with internal 500 kW
pull up resistor
MAXIMUM RATINGS
Symbol
Parameter
Value
−28 to +28
−0.3 to +28
−0.3 to +6
−0.3 to +28
150
Unit
V
V
Input Voltage Range (Note 1)
Output Voltage Range
IN
V
OUT
V
V
Standard I/O Range (UVFLAG, OVFLGB, TRCB, GT_CON)
HV I/O Range (OVLO, UVLO, EN)
V
I/O
V
HVIO
V
T
Maximum Junction Temperature
°C
°C
kV
kV
°C
J(max)
TSTG
Storage Temperature Range
−65 to 150
2
ESDHBM
ESDCDM
ESD Capability, Human Body Model (Note 2)
ESD Capability, Charged Device Model (Note 2)
1
T
SLD
Lead Temperature Soldering
Reflow (SMD Styles Only), Pb−Free Versions (Note 3)
260
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Charged Device Model tested per AEC−Q100−011 (EIA/JESD22−C101)
Latch−up Current Maximum Rating: v150 mA per JEDEC standard: JESD78
3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
THERMAL CHARACTERISTICS
Symbol
Rating
Value
Unit
R
Thermal Characteristics, X2QFN12 (Note 4)
Thermal Resistance, Junction−to−Air (Note 5)
139.3
°C/W
q
JA
4. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
5. Values based on 2S2P JEDEC std. PCB.
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3
FPF2260ATMX
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Supply Voltage on VIN (GT_CON floating)
Min
Max
22
Unit
V
in
4.0
V
Supply Voltage on VIN (GT_CON grounded)
I/O pins
16
V
0
5.5
V
OVLO, UVLO, EN,
TRCB, GT_CON,
OVFLAG, UVFLAG
C
IN Capacitor
1
1
−
−
mF
mF
°C
in
C
OUT Capacitor
Ambient Temperature
out
T
A
−40
85
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
ELECTRICAL CHARACTERISTICS (V = 2.9 to 23 V, C = 0.1 mF, C
= 0.1 mF, T = −40 to 85°C; For typical values V = 5.0 V,
≤ 3 A, C = 0.1 mF, T = 25°C, for min/max values T = −40°C to 85°C; unless otherwise noted. (Note 6)
IN
IN
OUT
A
IN
I
IN
IN A A
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
LEAKAGE AND QUIESCENT CURRENTS
I
Q
Input Quiescent Current on VIN
V
V
= 5 V, V = 1 V, TRCB = 0,
OVLO
OUT
−
−
160
400
−
−
mA
IN
floating
V
V
= 20 V, V
= 1 V, TRCB = 0,
IN
OUT
OVLO
floating
I
Device turned off current
V
V
V
= 5 V, V = 0 V, V = 0 V
OUT
−
−
120
180
−
−
−
mA
mA
nA
OFF
IN
EN
I
Supply Current during Over Voltage
OVLO Input Leakage Current
= 20 V, V
= 1.8 V, V
= 0 V
IN_Q
IN
OVLO
OVLO_TH
OUT
I
= V
−100
100
OVLO
OVLO
OVER VOLTAGE AND UNDER VOLTAGE LOCKOUT
V
Default Over−Voltage Trip Level
Default Under−Voltage Trip Level
OVLO set threshold
V
V
V
rising, T = −40 to 85°C
5.9
1.8
6.1
2.0
6.3
2.2
V
V
V
DEF_OVLO
DEF_UVLO
IN
A
V
falling, T = −40 to 85°C
IN
A
V
rising from 1.1 V to 1.3 V, the OVLO
1.15
1.19
1.23
OVLO_TH
OVLO
voltage to switch off power FET
V
OVLO threshold hysteresis
UVLO set threshold
−
2
−
%
V
HYS_OVLO
V
V
falling from 1.3 V to 1.1 V, the UVLO
1.15
1.17
1.23
UVLO_TH
UVLO
voltage to switch off power FET
V
UVLO threshold hysteresis
Adjustable OVLO range
−
2
−
%
V
HYS_UVLO
V
V
OVLO
> 0.5 V
4
−
22
OV_RNG
TRCB (IN TRCB MODE ONLY, I.E. VTRCB = HIGH/FLOAT)
V
TRCB trigger level
TRCB release time
V
IN
V
IN
= 5 V, I = 100 mA
LOAD
−
−
35
1
−
−
mV
ms
DROP
t
= 5 V
REL
I/O THRESHOLDS
OVLO Input Threshold Voltage
Voltage Increasing, Logic High
Voltage Decreasing, Logic Low
V
High
Low
0.3
−
−
−
V
V
IH_OVLO
IL_OVLO
V
0.15
GATE DRIVER
V
Turn on status gate positive voltage over
OUT (Note 8)
V
V
= V
= V
= 5 V, V
= 5 V, V
= 0 V
−
−
−
12
6
−
−
V
GS
IN
OUT
GT_CON
= 1.8 V
IN
OUT
GT_CON
I
Turn on status gate positive current
OVP turn off gate current (Note 9)
V
V
= 0 V, V = V = 5 V,
OUT
−
10
mA
GS
TRCB
GT_CON
IN
= 1.8 V, I
= 10 mA
LOAD
V
IN
= 5 V, V
= 1.8 V, V from 1.1 V
OVLO
−
−
3
A
GT_CON
to 1.3 V
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4
FPF2260ATMX
ELECTRICAL CHARACTERISTICS (V = 2.9 to 23 V, C = 0.1 mF, C
= 0.1 mF, T = −40 to 85°C; For typical values V = 5.0 V,
≤ 3 A, C = 0.1 mF, T = 25°C, for min/max values T = −40°C to 85°C; unless otherwise noted. (Note 6) (continued)
IN
IN
OUT
A
IN
I
IN
IN A A
Symbol
I/O AND LOGIC CONTROL
I/O Logic High Voltage
Parameter
Test Condition
Min
Typ
Max
Unit
V
IH
Pins: EN, TRCB, GT_CON
1.2
−
−
−
−
−
V
V
V
V
IL
I/O Logic Low Voltage
0.5
0.4
V
OL
Output Low Voltage of Open−Drain pins
V
I/O
= 3.3 V, I = 1 mA,
SINK
Pins: UVFLAG, OVFLGB
−
I
Leakage Current of I/O pins
V
= 3.3 V, Logic de−asserted,
−0.5
−
0.5
mA
LKG
I/O
Pins: UVFLAG, OVFLGB, GT_CON
TIMING
t
De−bounce Time of Power FET turned on Time from 2.5 V < V < V to
IN_OVLO
−
15
−
ms
SW_DEB
IN
V
= 0.1 x V
OUT
IN
t
De−bounce Time of OTG turned on
De−bounce Time of UVFLAG flag
De−bounce Time of OVFLGB flag
Switch Turn−On rising Time (Note 9)
Time from V
> 2.8 V to V = 0.1 x V
−
−
−
−
15
130
1
−
−
−
−
ms
ms
OTG_DEB
OUT
IN
OUT
t
Time from V > V
to UVFLAG < 0.4 V
UV_DEB
IN
IN_UVLO
IN_OVLO
t
Time from V < V
to OVFLGB > 1.8 V
ms
ms
OV_DEB
IN
t
R
V
= 5 V, R = 100 W, C = 22 mF, V from
OUT
2
IN
L
L
0.1 x V to 0.9 x V
IN
IN
t
Switch Turn−Off Time (Note 8, 9)
R = 10 W, C = 0 μF, time from V > V
OFF
L
to V
L
IN
OVLO
= 0.9 x V
OUT
IN
Internal OVP level
−
−
50
100
−
−
ns
ns
External OVP level (Note 10)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T = T = 25°C. Low
J
A
duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
7. Refer to the APPLICATION INFORMATION section.
8. Based on the recommended MOSFET devices.
9. Values based on design and/or characterization
10.Depends on the capacitance on OVLO pin.
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5
FPF2260ATMX
TYPICAL CHARACTERISTICS
Figure 3. Quiescent Current over Temperature
Figure 4. Quiescent Current over VIN
Figure 5. Power−Up Transient
(VIN = 5 V, COUT = 0.1 mF)
Figure 6. Power−Down Transient
(VIN = 5 V, COUT = 0.1 mF)
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6
FPF2260ATMX
FUNCTION DESCRIPTION
The external resistor ladder can be decided according to
the following equation:
General
VIN_UVLO + VUVLO_TH [1 ) R1 ń (R2 ) R3)]
(eq. 1)
FPF2260A is an OVP controller to drive external N−type
MOSFETs. The device can protect next stage system which
is optimized to lower voltage working condition, especially
with ultra−high charging current. The device includes
multi−functions including OVP, Advanced TRCB, and
Negative Stress protection.
where R1, R2 and R3 are the resistors in figure 1.
Over Voltage Lockout
The power FET will be turned off whenever IN voltage
higher than V . The value of V can be set by
IN_OVLO
IN_OVLO
external resistor ladder or just be default value V
.
IN_OVLO
Power MOSFET Driver
When V
≤ 0.3 V, V
is decided by default value.
> 0.3 V, the power switch will be turned off
OVLO
OVLO
The FPF2260A integrates charge pump driver to control
external N−type MOSFET pair. The drive voltage can be
configured by GPIO for different MOSFET.
The drive voltage for MOSFET can be configured by
When V
OVLO
once V
> V
. The external resistor ladder can
OVLO
OVLO_TH
be decided according to the following equation:
VIN_OVLO + VOVLO_TH [1 ) (R1 ) R2) ń R3]
GPIO pin GT_CON. V could be set to 6 V by pull
(eq. 2)
GS
GT_CON to high or floating. Or, V will be set to 12 V by
pulling GT_CON to ground.
GS
where R1, R2 and R3 are the resistors in figure 1.
Negative Voltage Protection
True Reverse Current Blocking and USB OTG
FPF2260 support negative voltage protection to help
system avoid unexpected negative stress. The gate of first
external power FET, GT1, will be pulled down with the
voltage on IN when it is negative. This behavior can keep the
external FET at off status till −28 V.
The FPF2260A support advanced TRCB mode by pulling
TRCB pin to high or floating it. In the advanced TRCB
mode, no reverse current will be seen from OUT to IN
through the external MOSFETs if V
– V > 30 mV.
OUT
IN
When advanced TRCB mode is active, OTG operation is
not supported. If OTG is needed, TRCB pin needs to be
pulled down to ground.
APPLICATIONS INFORMATION
Input Decoupling (C )
in
Enable Control
A ceramic or tantalum at least 0.1 mF capacitor is
recommended and should be put before and close the
connection point of MOSFET and FPF2260A IN. Higher
capacitance and lower ESR will improve the overall line and
load transient response.
The GPIO EN is an active high control pin. When the
voltage is pulled low, FPF2260A will disable the external
MOSFETs by connecting GT1 to IN and GT2 to OUT.
When EN is logic high, FPF2260A will close external
MOSFET if there are no over stressed condition.
Output Decoupling (C
)
out
Under Voltage Lockout
The FPF2260A is a stable component and does not require
a minimum Equivalent Series Resistance (ESR) for the
output capacitor. The minimum output decoupling value is
0.1 mF and can be augmented to fulfill stringent load
transient requirements.
FPF2260A will turn the FETs off when the voltage on IN
is lower than the UVLO threshold V
.
IN_UVLO
Whenever IN voltage ramps up to higher than the
threshold, the power FET will be turned on automatically
after t
de−bounce time if there is no other over stressed
DEB
condition.
Hints for PCB Layout
The external MOSFET is an important part to FPF2260A.
The connection of gate should be as short as possible to
avoid parasitic resistance and inductance for better OVP
performance.
ORDERING INFORMATION
Part Number
†
Marking
Package
Shipping
FPF2260ATMX
6B
X2QFN12
5000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
X2QFN12 1.6x1.6, 0.4P
CASE 722AG
ISSUE A
DATE 26 SEP 2017
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13772G
X2QFN12 1.6x1.6, 0.4P
PAGE 1 OF 1
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