FQU2N50BTU-WS [ONSEMI]
N 沟道 QFET® MOSFET;
| 型号： | FQU2N50BTU-WS |
| 厂家： | 
ONSEMI |
| 描述： | N 沟道 QFET® MOSFET 开关 脉冲 晶体管 |
| 文件： | 总9页 (文件大小：909K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws,
regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/
or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized
for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for
implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and holdonsemi and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
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Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others.
FQU2N50B
N-Channel QFET® MOSFET
500 V, 1.6 A, 5.3 Ω
Description
Features
This N-Channel enhancement mode power MOSFET is
•
1.6 A, 500 V, RDS(on) = 5.3 Ω (Max.) @ VGS = 10 V,
ID = 0.8 A
produced
using
ON Semiconductor’s
proprietary
planar stripe and DMOS technology. This advanced
MOSFET technology has been especially tailored to
reduce on-state resistance, and to provide superior
switching performance and high avalanche energy
strength. These devices are suitable for switched mode
power supplies, audio amplifier, DC motor control, and
variable switching power applications.
•
•
•
•
•
Low Gate Charge (Typ. 6.0 nC)
Low Crss (Typ. 4.3 pF)
Fast Switching
100% Avalanche Tested
Improved dv/dt Capability
D
G
G
D
S
I-PAK
Absolute Maximum Ratings TC = 25oC unless otherwise noted.
S
Symbol
Parameter
FQU2N50BTU-WS
Units
V
V
I
Drain-Source Voltage
500
1.6
DSS
- Continuous (T = 25°C)
Drain Current
A
D
C
- Continuous (T = 100°C)
1.0
A
C
I
(Note 1)
Drain Current
- Pulsed
6.4
A
DM
V
E
I
Gate-Source Voltage
± 30
120
V
GSS
(Note 2)
(Note 1)
(Note 1)
(Note 3)
Single Pulsed Avalanche Energy
Avalanche Current
mJ
A
AS
1.6
AR
E
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
3.0
mJ
V/ns
W
AR
dv/dt
4.5
Power Dissipation (T = 25°C) *
2.5
P
A
D
Power Dissipation (T = 25°C)
30
W
C
- Derate above 25°C
0.24
-55 to +150
W/°C
°C
T , T
Operating and Storage Temperature Range
Maximum Lead Temperature for Soldering,
1/8" from Case for 5 Seconds
J
STG
T
300
°C
L
Thermal Characteristics
Symbol
Parameter
Unit
oC/W
FQU2N50BTU_WS
RJC
RJA
Thermal Resistance, Junction to Case, Max.
4.17
110
50
Thermal Resistance, Junction to Ambient (Minimum Pad of 2-oz Copper), Max.
Thermal Resistance, Junction to Ambient (*1 in2 Pad of 2-oz Copper), Max.
Publication Order Number:
©2000 Semiconductor Components Industries, LLC.
October-2017,Rev. 3
FQU2N50B/D
Package Marking and Ordering Information
Part Number
Top Mark
Package
Packing Method Reel Size
N/A
Tape Width
Quantity
FQU2N50BTU-WS
FQU2N50B
I-PAK
N/A
75 units
Tube
Electrical Characteristics TC = 25oC unless otherwise noted.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV
V
I
= 0 V, I = 250 µA
Drain-Source Breakdown Voltage
500
--
--
--
--
V
DSS
GS
D
∆BV
Breakdown Voltage Temperature
Coefficient
DSS
= 250 µA, Referenced to 25°C
0.48
V/°C
D
/
∆T
J
I
V
V
V
V
= 500 V, V = 0 V
--
--
--
--
--
--
--
--
1
µA
µA
nA
nA
DSS
DS
GS
Zero Gate Voltage Drain Current
= 400 V, T = 125°C
10
DS
GS
GS
C
I
= 30 V, V = 0 V
Gate-Body Leakage Current, Forward
Gate-Body Leakage Current, Reverse
100
-100
GSSF
DS
I
= -30 V, V = 0 V
GSSR
DS
On Characteristics
V
V
= V , I = 250 µA
2.3
3.6
3.0
4.3
3.7
5.0
V
V
V
Gate Threshold Voltage
DS
GS
D
GS(th)
= V , I = 250 mA
DS
GS
D
R
g
Static Drain-Source
On-Resistance
DS(on)
V
V
= 10 V, I = 0.8 A
--
--
4.2
1.3
5.3
--
Ω
GS
DS
D
= 50 V, I = 0.8 A
Forward Transconductance
S
FS
D
Dynamic Characteristics
C
C
C
Input Capacitance
--
--
--
180
30
4
230
40
6
pF
pF
pF
iss
V
= 25 V, V = 0 V,
GS
DS
Output Capacitance
oss
rss
f = 1.0 MHz
Reverse Transfer Capacitance
Switching Characteristics
t
t
t
t
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
--
--
--
--
--
--
--
6
20
60
30
50
8.0
--
ns
ns
d(on)
V
= 250 V, I = 2.1 A,
DD
D
25
10
20
6.0
1.3
3.0
r
R
= 25 Ω
G
ns
d(off)
f
(Note 4)
(Note 4)
ns
Q
Q
Q
nC
nC
nC
g
V
V
= 400 V, I = 2.1 A,
DS
D
= 10 V
gs
gd
GS
--
Drain-Source Diode Characteristics and Maximum Ratings
I
Maximum Continuous Drain-Source Diode Forward Current
--
--
--
--
--
--
--
1.6
6.4
1.4
--
A
A
S
I
Maximum Pulsed Drain-Source Diode Forward Current
SM
V
t
V
V
= 0 V, I = 1.6 A
Drain-Source Diode Forward Voltage
Reverse Recovery Time
--
V
SD
GS
S
= 0 V, I = 2.1 A,
195
0.69
ns
µC
rr
GS
S
dI / dt = 100 A/µs
Q
Reverse Recovery Charge
--
F
rr
ꢀꢁꢂꢃꢄꢅ
1. Repetitive rating : pulse-width limited by maximum junction temperature.
2. L = 85 mH, IAS = 1.6 A, VDD = 50 V, RG = 25 Ω, starting TJ = 25oC.
3. ISD ≤ 2.1 A, di/dt ≤ 200 A/μs, VDD ≤ BVDSS, starting TJ = 25oC.
4. Essentially independent of operating temperature.
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2
ꢀ !ꢁꢂꢃꢄꢅꢆꢇꢃꢈꢃꢂꢉꢊꢈꢁꢋꢉꢁꢂꢋ
VGS
Top
:
15 V
10 V
8.0 V
7.0 V
6.5 V
6.0 V
100
℃
150
Bottom : 5.5 V
100
℃
25
-1
10
℃
-55
※
Notes :
μ
※
Notes :
1. 250 s Pulse Test
2. TC = 25
1. VDS = 50V
℃
μ
2. 250 s Pulse Test
-2
-1
10
10
10-1
100
VDS , Drain-Source Voltage [V]
101
2
4
6
8
10
VGS , Gate-Source Voltage [V]
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
18
15
12
9
VGS = 10V
VGS = 20V
100
6
℃
25
℃
150
※
Notes :
3
1. VGS = 0V
※
℃
Note : T = 25
μ
2. 250 s Pulse Test
J
10-1
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0.2
0.4
0.6
0.8
1.0
1.2
1.4
ID , Drain Current [A]
VSD , Source-Drain Voltage [V]
Figure 3. On-Resistance Variation vs.
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
350
300
250
200
150
100
50
12
10
8
C
iss = Cgs + Cgd (Cds = shorted)
oss = Cds + Cgd
rss = Cgd
C
VDS = 100V
VDS = 250V
VDS = 400V
C
C
iss
Coss
6
※
4
Notes :
1. VGS = 0 V
2. f = 1 MHz
C
rss
2
※
Note : ID = 2.1 A
6
0
0
10-1
100
101
0
1
2
3
4
7
5
QG, Total Gate Charge [nC]
VDS, Drain-Source Voltage [V]
Figure 5. Capacitance Characteristics
Figure 6. Gate Charge Characteristics
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3
ꢀ !ꢁꢂꢃꢄꢅꢆꢇꢃꢈꢃꢂꢉꢊꢈꢁꢋꢉꢁꢂꢋꢅꢀꢀꢀꢀꢁꢂꢃꢄꢅꢆꢄꢇꢈꢉꢊ
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.2
1.1
1.0
※Notes :
1. VGS = 0 V
2. ID = 250 μA
0.9
0.8
※
Notes :
1. VGS = 10 V
2. ID = 1.05 A
-100
-50
0
50
100
150
200
-100
-50
0
50
100
150
200
TJ, Junction Temperature [oC]
TJ, Junction Temperature [oC]
Figure 7. Breakdown Voltage Variation
vs. Temperature
Figure 8. On-Resistance Variation
vs. Temperature
1.8
1.5
1.2
0.9
0.6
0.3
0.0
Operation in This Area
is Limited by R DS(on)
101
100
10µs
s
1 ms
10 ms
DC
-1
10
※
Notes :
1. TC = 25 o
2. TJ = 150 o
3. Single Pulse
C
C
-2
10
100
101
102
103
25
50
75
100
125
150
℃
TC, Case Temperature [
]
VDS, Drain-Source Voltage [V]
Figure 9. Maximum Safe Operating Area
Figure 10. Maximum Drain Current
vs. Case Temperature
D = 0 .5
※
N o te s
1 . Z θ J C(t)
2 . D u ty F a c to r, D = t1 /t2
:
1 0 0
0 .2
℃
/W M a x.
=
4 .1 7
3 . T J M
-
T C
=
P D
* Z θ J C(t)
M
0 .1
0 .0 5
PDM
0 .0 2
1 0 -1
0 .0 1
t1
s in g le p u ls e
t2
-3
-2
-1
1 0 -5
1 0 -4
1 0
1 0
1 0
1 0 0
1 0 1
t1 , R e c t a n g u l a r P u l s e D u r a t i o n [ s e c ]
Figure 11. Transient Thermal Response Curve
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4
VGS
Same Type
as DUT
50KΩ
Qg
12V
200nF
300nF
VDS
VGS
Qgs
Qgd
DUT
I
= const.
G
Charge
Figure 12. Gate Charge Test Circuit & Waveform
RL
VDS
90%
VDS
VDD
VGS
RG
10%
VGS
DUT
V
GS
td(on)
tr
td(off)
tf
t on
t off
Figure 13. Resistive Switching Test Circuit & Waveforms
BVDSS
--------------------
BVDSS - VDD
L
1
2
2
----
EAS
=
L IAS
VDS
I D
BVDSS
IAS
RG
VDD
ID (t)
V
VDS (t)
VDD
DUT
GS
t p
t p
Time
Figure 14. Unclamped Inductive Switching Test Circuit & Waveforms
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5
+
DUT
VDS
_
I SD
L
Driver
RG
Same Type
as DUT
VDD
VGS
• dv/dt controlled by RG
• ISD controlled by pulse period
Gate Pulse Width
--------------------------
VGS
D =
Gate Pulse Period
10V
( Driver )
IFM , Body Diode Forward Current
I SD
di/dt
( DUT )
IRM
Body Diode Reverse Current
Body Diode Recovery dv/dt
VSD
VDS
( DUT )
VDD
Body Diode
Forward Voltage Drop
Figure 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms
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6
Mechanical Dimensions
Figure 16. TO-251 (I-PAK), Molded, 3-Lead, Option AA
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any manner without notice. Please note the revision and/or date on the drawing and contact a ON Semiconductor representative to
verify or obtain the most recent revision. Package specifications do not expand the terms of ON Semiconductor’s worldwide
terms and conditions, specif-ically the warranty therein, which covers ON Semiconductor products.
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7
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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