FSA2267L10X [ONSEMI]

0.35Ω 低压双 SPDT 模拟开关;
FSA2267L10X
型号: FSA2267L10X
厂家: ONSEMI    ONSEMI
描述:

0.35Ω 低压双 SPDT 模拟开关

开关 光电二极管
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中文:  中文翻译
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March 2012  
FSA2267 / FSA2267A  
0.35Low-Voltage Dual-SPDT Analog Switch  
Features  
Description  
Typical 0.35On Resistance (RON) for +2.7V Supply  
FSA2267A Features <10µA ICCT Current  
The FSA2267 and FSA2267A are Dual Single Pole Dou-  
ble Throw (SPDT) analog switches. The FSA2267 oper-  
ates from a single 1.65V to 3.6V supply, while the  
FSA2267A operates from a single 2.3V to 4.3V supply.  
Each features an ultra-low On Resistance of 0.35at a  
+2.7V supply and 25°C. Both devices are fabricated with  
sub-micron CMOS technology to achieve fast switching  
speeds and designed for break-before-make operation.  
when S Input is Lower than VCC  
RON Fatness for +2.7V Supply: 0.25Maximum  
1.6mm x 2.1mm 10-Lead MicroPak™ Package  
Broad VCC Operating Range  
Low THD (0.02% Typical for 32Load)  
High Current Handling Capability (350mA Continuous  
FSA2267A features very low quiescent current, even  
when the control voltage is lower than the VCC supply.  
This feature services the mobile handset applications  
very well, allowing for the direct interface with baseband  
processor general-purpose I/Os.  
Current <3.3V Supply)  
Applications  
Cell phone  
PDA  
Portable Media Player  
Ordering Information  
Order Number  
Top Mark  
Package Description  
Packing Method  
5000 Units on Tape  
and Reel  
FSA2267L10X  
FC  
10-Lead MicroPak, 1.6 x 2.1mm, JEDEC MO-255  
5000 Units on Tape  
and Reel  
FSA2267AL10X  
FSA2267AMUX  
FD  
10-Lead MicroPak, 1.6 x 2.1mm, JEDEC MO-255  
FSA  
2267A  
10-Lead Molded Small Outline Package (MSOP),  
JEDEC MO-187, 3.0mm Wide  
4000 Units on Tape  
and Reel  
.
Figure 1. Application Diagram  
© 2005 Fairchild Semiconductor Corporation  
FSA2267 / FSA2267A Rev. 1.0.5  
www.fairchildsemi.com  
Analog Symbols  
1B0  
1B1  
2B0  
2B1  
1A  
1S  
2A  
2S  
Figure 2. Analog Symbol  
Connections Diagram  
Vcc  
10  
9
8
7
6
1B0  
1
2
3
4
1A  
1S  
2S  
2A  
1B0  
1B1  
1
2
3
4
5
10  
9
Vcc  
1A  
1S  
2S  
2A  
1B1  
2B0  
2B1  
2B0  
8
2B1  
7
5
GND  
6
GND  
Figure 3. 10-Lead MSOP  
Figure 4. 10-Lead Micropak  
Truth Table  
Control Input(s)  
LOW Logic Level  
HIGH Logic Level  
Function  
B0 Connected to A  
B1 Connected to A  
Pin Descriptions  
Pin  
Name  
Function  
Data Ports  
Control Input  
Supply Voltage  
Ground  
1, 2, 3, 4, 6, 9  
1B0, 1B1, 2B0, 2B1, 2A, 1A  
8, 7  
10  
5
1S, 2S  
VCC  
GND  
© 2005 Fairchild Semiconductor Corporation  
FSA2267 / FSA2267ARev. 1.0.5  
www.fairchildsemi.com  
2
Absolute Maximum Ratings  
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-  
ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-  
tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The  
absolute maximum ratings are stress ratings only..  
Symbol  
VCC  
VS  
Parameter  
Min.  
-0.5  
-0.5  
-0.5  
-50  
Max.  
+5.5  
Unit  
V
Supply Voltage  
Switch Voltage(1)  
VCC + 0.5  
5.5  
V
VIN  
Control Input Voltage(1)  
Input Diode Current(2)  
Switch Current  
V
IIK  
mA  
mA  
ISW  
350  
500  
Peak Switch Current  
ISWPEAK  
mA  
(Pulsed at 1ms Duration, <10% Duty Cycle)  
TSTG  
TJ  
Storage Temperature Range  
-65  
+150  
+150  
+260  
7500  
7000  
°C  
°C  
°C  
V
Maximum Junction Temperature  
TL  
Lead Temperature (Soldering, 10 Seconds)  
Human Body Model: FSA2267  
Human Body Model, JESD22-A114:FSA2267A  
V
ESD  
Charged Device Model, JESD22-C101:  
FSA2267/FSA2267A  
1000  
V
Notes:  
1. The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are  
observed.  
2. Minimums define the acceptable range of current. Negative current should not exceed minimun negative values.  
Recommended Operating Conditions  
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended  
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not  
recommend exceeding them or designing to absolute maximum ratings.  
Symbol  
Parameter  
Min.  
Max.  
Unit  
V
Supply Voltage  
VCC  
FSA2267  
1.65  
2.3  
0
3.6  
4.3  
V
FSA2267A  
VIN  
VSW  
TA  
Control Input Voltage(3)  
Switch Input Voltage  
Operating Temperature  
VCC  
VCC  
+85  
V
V
0
-40  
°C  
Note:  
3. Unused inputs must be held HIGH or LOW. They may not float.  
© 2005 Fairchild Semiconductor Corporation  
www.fairchildsemi.com  
FSA2267 / FSA2267ARev. 1.0.5  
3
ESD Protection  
ESD Performance of the FSA2267/FSA2267A  
FSA2267  
? HBM all pins 7.0kV  
? CDM all pins 1.0kV  
FSA2267A  
? HBM all pins 7.5kV  
? CDM all pins 1.0kV  
Figure 5. Human Body ESD Test Model  
Human Body Model  
Figure 5 shows the schematic representation of the  
Human Body Model ESD event. Figure 6 is the ideal  
waveform representation of the Human Body Model. The  
device is tested to JEDEC: JESD22-A114 Human Body  
Model.  
Charged Device Model  
In manufacturing test and handling environments, a  
more useful model is the Charged Device Model and the  
FSA2267/FSA2267A has a very good ESD immunity to  
this model. The device is tested to JEDEC: JESD22-  
C101 Charged Device Model.  
Figure 6. HBM Current Waveform  
IEC 61000-4-2  
The IEC 61000-4-2 standard covers ESD testing and  
performance of finished equipment and evaluates the  
equipment in its entirety for ESD immunity. Fairchild  
Semiconductor has evaluated this device using the  
IEC 6100-4-2 representative system model depicted in  
Figure 7.  
ESD values measured via the IEC 61000-4-2 evaluation  
method are influenced by the specific board layout,  
board size, and many other factors of the manufacturer’s  
product application. Measured system ESD values can-  
not be guaranteed by Fairchild Semiconductor to exactly  
correlate to a manufacturer’s in-house testing due to  
these application environment variables. Fairchild Semi-  
conductor has been able to determine that, for ultra-por-  
table applications, an enhanced ESD immunity, relative  
to the IEC 61000-4-2 specification, can be achieved with  
the inclusion of a 100series resistor in the VCC supply  
path to the analog switch (see Figure 8). Typical  
improvements of between 3-6kV of ESD immunity (I/O to  
GND) have been measured with the inclusion of the  
resistor with the IEC 61000-4-2 representative model.  
For more information on ESD testing methodologies,  
please refer to:  
Figure 7. IEC 61000-4-2 ESD Test Model  
Analog Switch Supply Rail  
100  
VCC  
1A  
1B0  
1B1  
2B0  
2B1  
AN-6019 Fairchild Analog Switch Products ESD Test  
Methodology Overview  
http://www.fairchildsemi.com/an/AN/AN-6019.pdf.  
ESD Event  
1S  
2A  
2S  
Additional ESD Test Conditions  
For information regarding test methodologies and perfor-  
mance levels, please contact Fairchild Semiconductor.  
Ultra-portable Connector  
Figure 8. ESD Immunity with 100Resistor  
© 2005 Fairchild Semiconductor Corporation  
FSA2267 / FSA2267A Rev. 1.0.5  
www.fairchildsemi.com  
4
FSA2267 DC Electrical Characteristics  
All typical values are at 25°C unless otherwise specified.  
TA= 40 to  
+85C  
VCC  
TA = +25C  
Symbol  
Parameter  
Conditions  
Units  
(V)  
Min. Typ. Max. Min. Max.  
2.7 to 3.6  
2.3 to 2.7  
2.0  
1.7  
Input Voltage High  
V
VIH  
0.65  
VCC  
1.65 to 1.95  
2.7 to 3.6  
2.3 to 2.7  
0.8  
0.7  
Input Voltage Low  
V
VIL  
0.35  
VCC  
1.65 to 1.95  
1.65 to 3.6  
3.6  
Control Input Leakage  
VIN = 0V to VCC  
-0.5  
-50  
0.5  
50  
A  
IIN  
nA = 0.3V, 3.3V, nB0 or nB1  
= 0.3V, 3.3V or floating  
-5.0  
-5.0  
-5.0  
-5.0  
-5.0  
-5.0  
5.0  
5.0  
5.0  
5.0  
5.0  
5.0  
INO(OFF)  
INC(OFF)  
,
Off-Leakage Current of  
Port nB0 and nB1  
nA = 0.3V, 2.4V, nB0 or nB1  
= 0.3V, 2.4V or floating  
2.7  
1.95  
3.6  
-50  
-50  
-50  
-50  
-50  
50  
50  
nA  
nA  
nA = 0.3V, 1.65V, nB0 or nB1  
= 0.3V, 1.65V or floating  
nA = 0.3V, 3.3V, nB0 or nB1  
= 0.3V, 3.3V or floating  
50  
On Leakage Current of  
Port 1A and 2A  
nA = 0.3V, 2.4V, nB0 or nB1  
= 0.3V, 2.4V or floating  
2.7  
50  
IA(ON)  
nA = 0.3V, 1.65V, nB0 or nB1  
= 0.3V, 1.65V or floating  
1.95  
2.7  
50  
IOUT = 100mA, nB0 or nB1  
= 0V, 0.7V, 2.0V, 2.7V  
0.35  
0.45  
1.0  
0.60  
0.75  
3.9  
Switch On Resistance(4) IOUT = 100mA, nB0 or nB1  
See Figure 9  
2.3  
RON  
= 0V, 0.7V, 1.6V, 2.3V  
IOUT = 100mA, nB0 or nB1  
= 0.8V  
1.65  
2.7  
2.3  
0.040  
0.040  
0.1  
0.075  
0.080  
On Resistance Matching IOUT = 100mA, nB0 or nB1  
RON  
Between Channels(5)  
= 0.7V  
1.65  
2.7  
0.25  
0.3  
IOUT = 100mA, nB0 or nB1  
= 0V to VCC  
On Resistance Flatness(6)  
2.3  
RFLAT(ON)  
1.65  
3.6  
0.3  
Quiescent Supply Current VIN = 0V or VCC, IOUT = 0A  
-100  
100 -500  
500  
nA  
ICC  
Notes:  
4. On resistance is determined by the voltage drop between A and B pins at the indicated current through the switch.  
5. RON = RONmax - RONmin measured at identical VCC, temperature, and voltage.  
6. Flatness is defined as the difference between the maximum and minimum value of RON over the specified range of  
conditions.  
© 2005 Fairchild Semiconductor Corporation  
FSA2267 / FSA2267A Rev. 1.0.5  
www.fairchildsemi.com  
5
FSA2267A DC Electrical Characteristics  
All typical values are at 25°C unless otherwise specified.  
TA= 40 to  
+85C  
VCC  
TA = +25C  
Symbol  
Parameter  
Conditions  
Units  
(V)  
Min. Typ. Max. Min. Max.  
3.6 to 4.3  
2.7 to 3.6  
2.3 to 2.7  
3.6 to 4.3  
2.7 to 3.6  
2.3 to 2.7  
2.3 to 4.3  
1.7  
1.5  
1.4  
0.7  
0.5  
0.4  
Input Voltage High  
V
VIH  
Input Voltage Low  
V
VIL  
Control Input Leakage  
VIN = 0V to VCC  
-0.5  
0.5  
µA  
IIN  
nA = 0.3V, 4.0V, nB0 or nB1  
= 4.0V, 0.3V or floating  
4.3  
3.6  
2.7  
4.3  
3.6  
2.7  
4.3  
3.0  
2.7  
-10.0  
-5.0  
10.0 -100  
100  
INO(OFF)  
INC(OFF)  
,
Off-Leakage Current of  
Port nB0 and nB1  
nA = 0.3V, 3.3V, nB0 or nB1  
= 0.3V, 3.3V or floating  
5.0  
5.0  
-50  
-50  
50  
50  
nA  
nA  
nA = 0.3V, 2.4V, nB0 or nB1 =  
0.3V, 2.4V or floating  
-5.0  
nA = 0.3V, 4.0V, nB0 or nB1 =  
0.3V, 4.0V or floating  
-20.0  
-5.0  
20.0 -200  
200  
50  
On Leakage Current of  
Port 1A and 2A  
nA = 0.3V, 3.3V, nB0 or nB1 =  
0.3V, 3.3V or floating  
5.0  
5.0  
-50  
-50  
IA(ON)  
nA = 0.3V, 3.3V, nB0 or nB1  
= 0.3V, 3.3V or floating  
-5.0  
50  
IOUT = 100mA, nB0 or nB1  
= 0V, 0.7V, 3.6V, 4.3V  
0.35  
0.35  
0.35  
0.6  
0.6  
0.6  
I
OUT = 100mA, nB0 or nB1  
Switch On Resistance(7)  
= 0V, 0.7V, 2.3V, 3.0V  
RON  
IOUT = 100mA, nB0 or nB1  
= 0V, 0.7V, 2.0V, 2.7V  
IOUT = 100mA, nB0 or nB1 = 0.8V  
1.65  
4.3  
1.0  
0.04  
0.04  
0.04  
0.1  
0.075  
0.075  
0.075  
On Resistance Matching  
Between Channels(8)  
See Figure 10  
3.0  
IOUT = 100mA, nB0 or nB1 = 0.7V  
RON  
2.7  
1.65  
4.3  
0.15  
0.15  
0.15  
0.3  
0.25  
0.25  
0.25  
3.0  
On Resistance  
Flatness(9)  
IOUT = 100mA, nB0 or nB1 = 0V  
to VCC  
RFLAT(ON)  
2.7  
1.65  
4.3  
Quiescent Supply Current VIN = 0V or VCC, IOUT = 0A  
-100  
80  
100 -500  
10.0  
500  
15.0  
7.0  
nA  
µA  
ICC  
VIN = 1.8V  
Increase in ICC per Input  
VIN = 2.6V  
7.0  
4.3  
ICCT  
0.5  
2.0  
Notes:  
7. On resistance is determined by the voltage drop between A and B pins at the indicated current through the switch.  
8. RON = RONmax - RONmin measured at identical VCC, temperature, and voltage.  
9. Flatness is defined as the difference between the maximum and minimum value of RON over the specified range of  
conditions.  
© 2005 Fairchild Semiconductor Corporation  
FSA2267 / FSA2267A Rev. 1.0.5  
www.fairchildsemi.com  
6
FSA2267 AC Electrical Characteristics  
All typical values are at 25°C unless otherwise specified.  
TA= -40 to  
+85°C  
Figure  
Units Number  
TA = +25°C  
VCC  
(V)  
Symbol  
tON  
Parameter  
Turn-On Time  
Turn-Off Time  
Conditions  
Min. Typ. Max. Min. Max.  
2.7 to 3.6  
2.3 to 2.7  
30.0 38.0  
29.0 37.0  
27.0 35.0  
13.0 16.0  
14.0 18.0  
15.0 21.0  
17.0  
42.0  
40.0  
38.0  
18.0  
20.0  
25.0  
nB0 or nB1 = 1.5V,  
RL = 50, CL = 35 pF  
ns  
ns  
ns  
Figure 11  
Figure 11  
Figure 12  
1.65 to 1.95  
2.7 to 3.6  
nB0 or nB1 = 1.5V,  
RL = 50, CL = 35 pF  
2.3 to 2.7  
tOFF  
1.65 to 1.95  
2.7 to 3.6  
2.0  
2.0  
2.0  
Break-Before-  
Make Time  
nB0 or nB1 = 1.5V,  
RL = 50, CL = 35 pF  
2.3 to 2.7  
15.0  
tBBM  
1.65 to 1.95  
12.0  
CL = 100 pF, VGEN = 0V,  
2.7 to 3.6  
2.3 to 2.7  
9.0  
9.0  
9.0  
R
GEN = 0  
CL = 100 pF, VGEN = 0V,  
GEN = 0  
CL = 100 pF, VGEN = 0V,  
GEN = 0  
Charge Injection  
Off Isolation  
pC  
Figure 14  
Q
R
1.65 to 1.95  
R
2.7 to 3.6  
2.3 to 2.7  
-80.0  
-80.0  
-80.0  
-80.0  
-80.0  
-80.0  
45.0  
f = 100kHz, RL = 50, CL = 5pF  
(Stray)  
dB  
dB  
Figure 13  
Figure 13  
OIRR  
1.65 to 1.95  
2.7 to 3.6  
f = 100kHz, RL = 50, CL = 5pF  
(Stray)  
Crosstalk  
2.3 to 2.7  
Xtalk  
BW  
1.65 to 1.95  
1.65 to 3.6  
-3db Bandwidth  
RL = 50  
MHz Figure 16  
RL = 32, VIN = 2Vpk-pk  
f = 20Hz to 20kHz  
,
2.7 to 3.6  
2.3 to 2.7  
0.024  
0.015  
0.35  
Total Harmonic  
Distortion  
RL = 32, VIN = 1.5Vpk-pk  
f = 20Hz to 20kHz  
,
,
%
Figure 17  
THD  
RL = 32, VIN = 1.2Vpk-pk  
f = 20Hz to 20kHz  
1.65 to 1.95  
© 2005 Fairchild Semiconductor Corporation  
FSA2267 / FSA2267ARev. 1.0.5  
www.fairchildsemi.com  
7
FSA2267A AC Electrical Characteristics  
All typical value are at 25°C unless otherwise specified.  
TA= -40 to  
+85°C  
VCC  
(V)  
TA = +25°C  
Figure  
Number  
Symbol  
Parameter  
Conditions  
Units  
Min. Typ. Max. Min. Max.  
3.6 to 4.3  
2.7 to 3.6  
2.3 to 2.7  
1.65  
37.0 46.0  
37.0 50.0  
60  
48.0  
57.0  
nB0 or nB1 = 1.5V,  
RL = 50, CL = 35pF  
tON  
Turn-On Time  
ns  
Figure 11  
570  
3.6 to 4.3  
2.7 to 3.6  
2.3 to 2.7  
1.65  
15.0 23.0  
16.0 30.0  
50.0  
25.0  
30.0  
nB0 or nB1 = 1.5V,  
RL = 50, CL = 35pF  
Turn-Off Time  
ns  
ns  
Figure 11  
Figure 12  
tOFF  
500  
3.6 to 4.3  
2.7 to 3.6  
2.3 to 2.7  
3.6 to 4.3  
8.0  
2.0  
2.0  
2.0  
Break-Before-  
Make Time  
nB0 or nB1 = 1.5V,  
RL = 50, CL = 35pF  
tBBM  
8.0  
8.0  
CL = 100 pF, VGEN = 0V,  
24.0  
RGEN = 0  
CL = 100 pF, VGEN = 0V,  
RGEN = 0  
2.7 to 3.6  
2.3 to 2.7  
24.0  
24.0  
Q
Charge Injection  
pC  
Figure 14  
CL = 100 pF, VGEN = 0V,  
RGEN = 0  
3.6 to 4.3  
2.7 to 3.6  
2.3 to 2.7  
3.6 to 4.3  
2.7 to 3.6  
2.3 to 2.7  
2.3 to 4.3  
3.6 to 4.3  
-75.0  
-75.0  
-75.0  
-70.0  
-70.0  
-70.0  
45.0  
f = 100kHz, RL = 50, CL = 5pF  
(Stray)  
OIRR Off Isolation  
dB  
dB  
Figure 13  
Figure 13  
f = 100kHz, RL = 50, CL = 5pF  
(Stray)  
Crosstalk  
Xtalk  
BW  
-3db Bandwidth  
RL = 50  
MHz Figure 16  
RL = 32, VIN = 2Vpk-pk  
,
0.02  
f = 20Hz to 20kHz  
Total Harmonic  
Distortion  
RL = 32, VIN = 1.5Vpk-pk  
f = 20Hz to 20kHz  
,
,
2.7 to 3.6  
2.3 to 2.7  
0.02  
0.02  
%
Figure 17  
THD  
RL = 32, VIN = 1.2Vpk-pk  
f = 20Hz to 20kHz  
Capacitance  
TA= -40 to  
+85°C  
VCC  
(V)  
TA = +25°C  
Figure  
Number  
Symbol  
Parameter  
Conditions  
Units  
Min. Typ. Max. Min. Max.  
Control Pin Input Capacitance f = 1Mhz  
0.0  
3.3  
3.3  
1.5  
30.0  
126  
Figure 15  
Figure 15  
Figure 15  
CIN  
COFF  
CON  
pF  
pF  
pF  
B Port Off Capacitance  
A Port On Capacitance  
f = 1Mhz  
f = 1Mhz  
© 2005 Fairchild Semiconductor Corporation  
FSA2267 / FSA2267ARev. 1.0.5  
www.fairchildsemi.com  
8
Typical Characteristics  
Figure 9. RON at 2.7V for FSA2267  
Figure 10. RON at 2.7V for FSA2267A  
© 2005 Fairchild Semiconductor Corporation  
FSA2267 / FSA2267ARev. 1.0.5  
www.fairchildsemi.com  
9
AC Loading and Waveforms  
CL includes Fixture and Stray Capacitance.  
Logic input waveforms are inverted for switches with  
opposite logic sense.  
Figure 11. Turn-On/Turn-Off Timing  
CL Includes Fixture and Stray Capacitance  
Figure 12. Break-Before-Make Timing  
Figure 13. Off Isolation and Crosstalk  
© 2005 Fairchild Semiconductor Corporation  
FSA2267 / FSA2267A Rev. 1.0.5  
www.fairchildsemi.com  
10  
AC Loading and Waveforms (Continued)  
Q = (DVOUT)(CL)  
Figure 14. Charge Injection  
Figure 15. On/Off Capacitance Measurement Setup  
Figure 16. Bandwidth  
Figure 17. Harmonic Distortion  
© 2005 Fairchild Semiconductor Corporation  
FSA2267 / FSA2267A Rev. 1.0.5  
www.fairchildsemi.com  
11  
Physical Dimensions  
2X  
1.62  
B
KEEPOUT ZONE, N  
OR VIAS ALLOWED  
(0.11)  
0.56  
1.12  
1.60  
IDENT IS  
ER THAN  
ER LINES  
0.10 C  
10X  
(0.35)  
(0.25)  
10X  
2X  
0.50  
TOP VIEW  
RECOMMENDED LAND PATTERN  
0.55 MAX  
0.05 C  
0.05 C  
0.05  
0.00  
(0.20)  
C
0.35  
0.25  
SIDE VIEW  
(0.15)  
D
AIL A  
0.65  
(0.36)  
0.35  
0.25  
0.55  
0.35  
DETAIL A 2X SCALE  
1
4
0.25  
0.56  
NOTES:  
10  
5
A. PACKAGE CONFORMS TO JEDEC  
REGISTRATION MO-255, VARIATION UABD  
B. DIMENSIONS ARE IN MILLIMETERS.  
C. DIMENSIONS AND TOLERANCES PER  
ASME Y14.5M, 1994.  
D. PRESENCE OF CENTER PAD IS PACKAGE  
SUPPLIER DEPENDENT. IF PRESENT  
IS NOT INTENDED TO BE SOLDERED A  
HAS A BLACK OXIDE FINISH.  
(0.29)  
0.35  
6
9
9X  
0.25  
0.50  
0.25  
0.15  
9X  
1.62  
0.10  
0.05  
C A B  
C
ALL FEATURES  
E. DRAWING FILENAME: MKT-MAC10Arev5.  
BOTTOM VIEW  
Figure 18. 10-Lead, MicroPak™, 1.6 x 2.1mm  
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in  
any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor  
representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairch-  
ild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products.  
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:  
http://www.fairchildsemi.com/packaging/.  
For current tape and reel specifications, visit Fairchild Semiconductor’s online packaging area:  
http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf.  
© 2005 Fairchild Semiconductor Corporation  
FSA2267 / FSA2267A Rev. 1.0.5  
www.fairchildsemi.com  
12  
Physical Dimensions  
Figure 19. Pb-Free, 10-Lead, Molded Small Outline Package (MSOP), JEDEC MO-187, 3.0mm Wide  
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in  
any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor  
representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairch-  
ild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products.  
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:  
http://www.fairchildsemi.com/packaging/.  
For current tape and reel specifications, visit Fairchild Semiconductor’s online packaging area:  
http://www.fairchildsemi.com/products/analog/pdf/msop10_tr.pdf.  
© 2005 Fairchild Semiconductor Corporation  
FSA2267 / FSA2267A Rev. 1.0.5  
www.fairchildsemi.com  
13  
© 2005 Fairchild Semiconductor Corporation  
FSA2267 / FSA2267A Rev. 1.0.5  
www.fairchildsemi.com  
14  
ON Semiconductor and  
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.  
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent  
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