FSA2269L10X [ONSEMI]
低压双 SPDT (0.4Ω) 模拟开关,带负摆幅音频功能;型号: | FSA2269L10X |
厂家: | ONSEMI |
描述: | 低压双 SPDT (0.4Ω) 模拟开关,带负摆幅音频功能 开关 光电二极管 |
文件: | 总16页 (文件大小:1057K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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July 2013
FSA2269 / FSA2269TS — Low-Voltage Dual-SPDT (0.4 )
Analog Switch with Negative Swing Audio Capability
Features
Description
The FSA2269 is a high-performance, dual Single-Pole
Double-Throw (SPDT) analog switch with negative swing
audio capability. The FSA2269 features ultra-low RON of
0.4 (typical) at 3.0 V VCC. The FSA2269 operates over
a wide VCC range of 1.65 V to 4.5 V, is fabricated with
sub-micron CMOS technology to achieve fast switching
speeds, and is designed for break-before-make
operation. The select input is TTL-level compatible.
. 0.4 Ω Typical On Resistance (RON) for +3.0 VSupply
. 0.25 Ω Maximum RON Flatness for +3.0 VSupply
. -3 db Bandwidth: > 50 MHz
. Low-ICCT Current Over an Expanded Control Input
Range
. Packaged in 10-Lead MicroPak™, UMLP, and
WLCSP
The FSA2269 features very low quiescent current even
when the control voltage is lower than the VCC supply.
This feature suits mobile handset applications by
allowing direct interface with baseband processor
general-purpose I/Os with minimal battery consumption.
. Power-Off Protection on Common Ports
. Broad VCC Operating Range: 1.65 to 4.5 V
. Noise Immunity Termination Resistors in FSA2269TS
The FSA2269TS includes termination resistors that
improve noise immunity during overshoot excursions,
off-isolation coupling, or “pop-minimization.”
Applications
. Cell Phone, PDA, Digital Camera, and Notebook
. LCD Monitor, TV, and Set-Top Box
Ordering Information
Part Number
Top Mark
Package Description
FSA2269L10X
HL
10-Lead, MicroPak, JEDEC MO-255, 1.6 x 2.1 mm
10-Lead, Quad Ultrathin Molded Leadless Package (UMLP), 1.4 x 1.8 mm,
0.4 mm Pitch
FSA2269UMX
FSA2269TSL10X
FSA2269TSUMX
FSA2269UCX
HP
HU
HT
N9
10-Lead, MicroPak, JEDEC MO-255, 1.6 x 2.1 mm
10-Lead, Quad Ultrathin Molded Leadless Package(UMLP), 1.4 x 1.8 mm,
0.4 mm Pitch
12-Ball, Wafer-Level Chip Scale Package (WLCSP),1.2 x 1.6 mm, 0.4 mm Pitch
Analog Symbols
1B0
1A
1B1
3µs
tON
S1
10k
GND
2B0
2B1
2A
3µs
tON
S2
10k
GND
Figure 1. FSA2269
Figure 2. FSA2269TS (with Slow Turn On)
© 2007 Fairchild Semiconductor Corporation
FSA2269 / FSA2269TS • Rev. 1.1.5
www.fairchildsemi.com
Pin Configuration
V
cc
2B0 1B1
10
9
8
7
6
1
1B0
1B1
2B0
1A
S1
S2
2
1
2B1
GND
2A
3
4
10 1B0
2
3
9
8
VCC
1A
5
6
7
2B1
4
2A
5
S2 S1
GND
Figure 3. 10-Pin UMLP (Top Through View)
Figure 4. 10-Pin MicroPak™ (Top Through View)
Figure 5. 12-Ball WLCSP (Bump Side View)
Figure 6. 12-Ball WLCSP (Top Side View)
Pin Descriptions
Pin #
Micropak
Pin # UMLP
WLCSP
Name
Description
1
2
2
3
B1
D3
1B1
2B0
2B1
GND
2A
Data Ports
Data Ports
Data Ports
Ground
3
4
B3
4
5
B2, C2
C3
5
6
Data Ports
6
7
A3
S2
Switch Select Pins
Switch Select Pins
Data Ports
7
8
A1
S1
8
9
C1
1A
9
10
1
D2
VCC
1B0
Supply Voltage
Data Ports
10
D1
Truth Table
Control Input, Sn
Function
LOW Logic Level
HIGH Logic Level
nB0 connected to nA(FSA2269/2269TS); nB1 terminated to GND (FSA2269TS only)
nB1 connected to nA (FSA2269/2269TS); nB0 terminated to GND (FSA2269TS only)
© 2007 Fairchild Semiconductor Corporation
FSA2269 / FSA2269TS • Rev. 1.1.5
www.fairchildsemi.com
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. Functional operation above the
recommended operating conditions is not implied. In addition, extended exposure to stresses above the
recommended operating conditions may affect device reliability. Absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
VCC
VSW
Supply Voltage
Switch I/O Voltage(1)
-0.5
VCC -4.6
-0.5
5.5
5.5
V
V
1B0, 1B1, 2B0, 2B1, 1A, 2A Pins
S1, S2
VCNTRL Control Input Voltage(1)
VCC +0.3
350
V
ISW
Switch I/O Current (Continuous)
mA
mA
ISWPEAK Peak Switch Current
Pulsed at 1ms Duration, <10% Duty Cycle
500
-65
+150
TSTG
TJ
Storage Temperature Range
Maximum Junction Temperature
C
C
°C
+150
+260
TL
Lead Temperature
Soldering, 10 Seconds
I/O to GND
MSL
Moisture Sensitivity Level, JEDEC J-STD-020A
1
12
11
I/O to GND
FSA2269UCX
Human Body Model, JEDEC: JESD22-A114
ESD
kV
Power to GND
All Other Pins
8
7
2
Charged Device Model, JEDEC: JESD22-C101
Note:
1. Input and output negative ratings may be exceeded if input and output diode current ratings are observed.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Min.
Max.
Unit
VCC
VS1, S2
VSW
Supply Voltage(2)
1.65
0V
4.50
VCC
VCC
+85
V
V
Control Input Voltage
Switch I/O Voltage
Operating Temperature
VCC -4.3
-40
V
TA
ºC
Note:
2. For 4.5 V operation, SEL frequency (pins S1 & S2) should not exceed 100 Hz and 50 ns edge rate.
© 2007 Fairchild Semiconductor Corporation
FSA2269 / FSA2269TS • Rev. 1.1.5
www.fairchildsemi.com
3
DC Electrical Characteristics
All typical values are TA=25°C unless otherwise specified.
TA=-40 to
+85°C
TA=+25°C
Symbol
Parameter
Conditions
VCC (V)
Unit
Min. Typ. Max. Min. Max.
3.60 to 4.50
3.00 to 3.60
2.70 to 3.00
2.30 to 2.70
1.65 to 1.95
3.60 to 4.50
2.70 to 3.60
2.30 to 2.70
1.65 to 1.95
1.70
1.50
1.35
1.30
0.90
0.7
V
Input Voltage High
IH
V
V
V
0.5
V
IL
Input Voltage Low
0.4
0.4
Control Input
Leakage (S1, S2)
IIN
V =0 to VCC
1.65 to 4.50
-0.5
0.5
µA
nA
IN
nA=0.5 V, VCC–0.5 V
Off Leakage
Current of Port nB0
and nB1
nB0 or nB1=VCC
0.5 V, 0.5 V, or
Floating
-
INO(0FF),
INC(OFF)
1.95 to 4.50 -50
50
20
-250
250
(FSA2269 only)
Figure 8
nA=0.5 V, VCC–0.5 V
nB0 or nB1=VCC
0.5 V, 0.5 V, or
Floating
-
On Leakage
Current of Port nA
IA(ON)
1.95 to 4.50 -20
-150
150
nA
Figure 9
Power-Off Leakage Common Port (1A,
Current (Common 2A), VIN=0 V to 4.5 V,
0
0
±1
µA
µA
Port Only 1A, 2A)
(FSA2269)
VCC=0V
nB0, nB1=Floating
IOFF
Power-Off Leakage Common Port (1A,
Current (Common 2A), VIN=0V to 4.5 V,
±45
Port Only 1A, 2A)
(FSA2269TS)
VCC=0 VnB0,
nB1=0 Vor Floating
ION=100 mA, nB0 or
nB1=0.7 V, 3.6 V,
4.5 V, Figure 7
4.50
3.00
2.30
1.65
0.30
0.40
0.52
1.00
ION=100 mA, nB0 or
nB1=0.7 V, 3.6 V,
Figure 7
0.80
Switch On
RON
Ω
Resistance(3,6)
ION=100mA, nB0 or
nB1=0V, 0.7 V, 1.6 V,
2.3 V, Figure 7
ION=100 mA, nB0 or
nB1=0V, 0.7 V,
1.65 V, Figure 7
4.50
3.00
2.30
1.65
0.04
0.06
0.12
1.00
0.13
0.13
On Resistance
Matching Between
Channels(4)
ION=100 mA, nB0 or
nB1=0.7 V
∆RON
Ω
Continued on the following page…
© 2007 Fairchild Semiconductor Corporation
FSA2269 / FSA2269TS • Rev. 1.1.5
www.fairchildsemi.com
4
DC Electrical Characteristics (Continued)
All typical values are TA=25°C unless otherwise specified.
TA=-40 to
+85ºC
TA=+25ºC
Symbol
Parameter
Conditions
VCC (V)
Unit
Min. Typ. Max. Min. Max.
4.50
3.00
2.30
1.65
0.25
0.25
On Resistance
Flatness(5)
IOUT=100 mA, nB0 or
nB1=0Vto VCC
RFLAT(ON)
Ω
0.5
0.6
Internal Termination
Resistors(6)
RTERM
10
kΩ
(FSA2269TS only)
Quiescent Supply
Current
ICC
V =0 or VCC, IOUT=0
4.50
4.50
-100
100
-500
500
nA
µA
IN
Input at 2.6 V
Input at 1.8 V
3.0
7.0
10.0
15.0
Increase in ICC per
Input
ICCT
Notes:
3. On resistance is determined by the voltage drop between Aand B pins at the indicated current through the
switch.
4. ∆ RON=RON max – RON min measured at identical VCC, temperature, and voltage.
5. Flatness is defined as the difference between the maximum and minimum value of on resistance (RON) over the
specified range of conditions.
6. Guaranteed by characterization, not production tested.
© 2007 Fairchild Semiconductor Corporation
FSA2269 / FSA2269TS • Rev. 1.1.5
www.fairchildsemi.com
5
AC Electrical Characteristics
All typical value are TA=25°C unless otherwise specified.
TA=+25ºC
TA=-40 to +85°C
Symbol Parameter Conditions
VCC (V)
Unit Figure
Min. Typ. Max. Min.
Max.
3.60 to 4.50
2.70 to 3.60
2.30 to 2.70
1.65 to 1.95
3.60 to 4.50
2.70 to 3.60
2.30 to 2.70
1.65 to 1.95
3.60 to 4.50
2.70 to 3.60
2.30 to 2.70
1.65 to 1.95
3.60 to 4.50
2.70 to 3.60
2.30 to 2.70
1.65 to 1.95
3.60 to 4.50
2.70 to 3.60
2.30 to 2.70
1.65 to 1.95
3.60 to 4.50
2.70 to 3.60
2.30 to 2.70
1.65 to 1.95
3.60 to 4.50
2.70 to 3.60
2.30 to 2.70
1.65 to 1.95
3.60 to 4.50
2.70 to 3.60
2.30 to 2.70
1.65 to 1.95
3.60 to 4.50
2.70 to 3.60
2.30 to 2.70
1.65 to 1.95
55
60
15
15
15
60
65
nB0 or
nB1=1.5 V,
RL=50 Ω,
CL=35 pF
Turn-On Time
FSA2269
Figure 10
ns
Figure 11
100
110
70
110
8.0
40
105
115
180
15
15
15
110
150
185
nB0 or
Turn-On Time nB1=1.5 V,
Figure 10
ns
tON
FSA2269UCX
RL=50 Ω,
CL=35 pF
Figure 11
3.5
4.5
6.0
0.5
0.5
0.5
4.0
5.0
7.0
nB0 or
Turn-On Time nB1=1.5 V,
Figure 10
µs
FSA2269TS
RL=50 Ω,
CL=35 pF
Figure 11
50
55
60
5
5
5
55
60
65
nB0 or
Turn-Off Time
FSA2269
nB1=1.5 V,
RL=50 Ω,
CL=35 pF
Figure 10
ns
Figure 11
100
110
120
5
5
5
105
115
125
nB0 or
nB1=1.5 V,
FSA2269UCX RL=50 Ω,
Turn-Off Time
Figure 10
ns
tOFF
Figure 11
CL=35 pF
80
45
50
55
5
5
5
50
55
60
nB0 or
nB1=1.5 V,
RL=50 Ω,
CL=35 pF
Turn-Off Time
FSA2269TS
Figure 10
ns
Figure 11
50
3
1
2
nB0 or
Break-Before-
Make Time
FSA2269(7)
5
nB1=1.5 V,
RL=50 Ω,
CL=35 pF
tBBM
tBBM
tBBM
ns
ns
µs
Figure 12
Figure 12
Figure 12
10
2
5
2
9.5
17.0
22.0
46.0
1.5
3.0
4.0
5.0
5.5
15.0
20.0
41.0
1.0
1.5
2.5
3.0
nB0 or
Break-Before-
Make Time
nB1=1.5 V,
RL=50 Ω,
CL=35 pF
FSA2269UCX(7)
nB0 or
Break-Before-
Make Time
nB1=1.5 V,
RL=50 Ω,
CL=35 pF
FSA2269TS(7)
Continued on the following page…
© 2007 Fairchild Semiconductor Corporation
FSA2269 / FSA2269TS • Rev. 1.1.5
www.fairchildsemi.com
6
AC Electrical Characteristics (Continued)
All typical value are TA=25°C unless otherwise specified.
TA=-40 to
+85°C
TA=+25ºC
Symbol Parameter
Conditions
VCC (V)
Unit
Figure
Min. Typ. Max. Min. Max.
CL=1.0 nF,
VS=0 V,
RS=0 Ω
Charge
Q
1.65 to 4.50
1.65 to 4.50
25
pC
dB
dB
Figure 16
Figure 14
Figure 15
Injection
f=100 kHz,
RL=50 Ω,
CL=0 pF
OIRR
Off Isolation
-70
f=100 kHz,
RL=50 Ω,
CL=0 pF
Xtalk
BW
Crosstalk
1.65 to 4.50
1.65 to 4.50
-70
RL=50 Ω,
CL=0 pF
-3db Bandwidth
>50
MHz Figure 13
f=20 Hz to
20 kHz,
RL=32 ,
Total Harmonic
Distortion
THD
1.65 to 4.50
.06
%
Figure 19
V =2 VPP
IN
VBIAS=0 V
Notes:
7. Guaranteed by characterization, not production tested.
Capacitance
TA=+25°C
Symbol
Parameter
Conditions VCC (V)
Unit
Figure
Min. Typ.
Max.
CIN
COFF
CON
Control Pin Input Capacitance f=1 MHz
0
2.5
30
pF
pF
pF
Figure 17
Figure 17
Figure 18
B Port Off Capacitance
APort On Capacitance
f=1 MHz
f=1 MHz
3.3
3.3
120
© 2007 Fairchild Semiconductor Corporation
FSA2269 / FSA2269TS • Rev. 1.1.5
www.fairchildsemi.com
7
Test Diagrams
VON
IA(OFF)
NC
A
nB
n
nA
V
IN
V
IN
Select
GND
ION
GND
Select
V = 0 orV
cc
Sel
GND
V
= 0 or V
**Each switch port is tested separately.
cc
Sel
RON = VON / ION
Figure 7. On Resistance
Figure 8. Off Leakage
nB
n
nA
IA(ON)
V
NC
IN
VOUT
A
C
R
L
R
GND
L
S
V
IN
GND
Select
GND
V
Sel
RL and CL are functions of the application
environment (see AC/DC tables).
CL includes test ficutre and stray capacitance.
V
V
cc
Sel= 0 or
GND
Figure 9. On Leakage
Figure 10. Test Circuit Load
tRISE= 2.5ns
tFALL = 2.5ns
V
CC
90%
CC /2
90%
CC /2
Input- VSel
V
V
10%
10%
90%
GND
VOH
90%
Output-VOUT
VOL
tON
tOFF
Figure 11. Turn-On / Turn-Off Waveforms
© 2007 Fairchild Semiconductor Corporation
FSA2269 / FSA2269TS • Rev. 1.1.5
www.fairchildsemi.com
8
Test Diagrams (Continued)
tRISE= 2.5ns
nB
n
nA
C
V
cc
V
IN
90%
VOUT
Input- VSel
V
/2
cc
GND
V
L
R
IN
L
10%
0V
GND
GND
VOUT
R
S
0.9*V
out
0.9*V
out
tD
V
Sel
RL and CL are functions of the application
environment (see AC/DC tables).
GND
CL includes test fixture and stray capacitance.
Figure 12. Break-Before-Make Interval Timing
Network Analyzer
R
S
V
IN
V
GND
S
GND
V
Sel
V
OUT
GND
GND
R
T
RL and CL are functions of the application
environment (see AC/DC tables).
GND
L
CL includes test fixture and stray capacitance.
Figure 13. Bandwidth
Network Analyzer
R
S
V
S
GND
R
T
GND
V
GND
Sel
V
OUT
GND
GND
R
T
RS and RT are functions of the application
environment (see AC/DC tables).
GND
Off-Isolation = 20 Log (VOUT / VIN
)
Figure 14. Channel Off Isolation
© 2007 Fairchild Semiconductor Corporation
FSA2269 / FSA2269TS • Rev. 1.1.5
www.fairchildsemi.com
9
Test Diagrams (Continued)
Figure 15. Adjacent Channel Crosstalk
Figure 16. Charge Injection Test
nB
n
nB
Capacitance
n
nS
n
Meter
nS
n
Capacitance
Meter
VSel = 0 or Vcc
V
Sel= 0 orVcc
f = 1MHz
f = 1MHz
nB
nB
n
n
Figure 17. Channel Off Capacitance
Figure 18. Channel On Capacitance
Audio Analyzer
R
S
V
IN
V
S
GND
GND
VCNTRL
V
OUT
GND
GND
R
T
VSel = 0 or Vcc
GND
RS and RT are functions of the application
environment (see AC Tables for specific values).
Figure 19. Total Harmonic Distortion
© 2007 Fairchild Semiconductor Corporation
FSA2269 / FSA2269TS • Rev. 1.1.5
www.fairchildsemi.com
10
Physical Dimensions
0.10 C
2.10
A
2X
1.62
B
KEEPOUT ZONE, NO TRACES
OR VIAS ALLOWED
(0.11)
0.56
1.12
1.60
PIN1 IDENT IS
2X LONGER THAN
OTHER LINES
0.10 C
10X
(0.35)
(0.25)
2X
10X
0.50
TOP VIEW
RECOMMENDED LAND PATTERN
0.55 MAX
0.05 C
0.05 C
0.05
0.00
(0.20)
C
0.35
0.25
SIDE VIEW
(0.15)
D
DETAIL A
(0.36)
0.35
0.25
0.65
0.55
0.35
0.25
DETAIL A 2X SCALE
1
4
0.56
NOTES:
10
5
A. PACKAGE CONFORMS TO JEDEC
REGISTRATION MO-255, VARIATION UABD .
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
D. PRESENCE OF CENTER PAD IS PACKAGE
SUPPLIER DEPENDENT. IF PRESENT IT
IS NOT INTENDED TO BE SOLDERED AND
HAS A BLACK OXIDE FINISH.
(0.29)
0.35
6
9
9X
0.25
0.50
0.25
0.15
9X
1.62
0.10
0.05
C A B
C
ALL FEATURES
E. DRAWING FILENAME: MKT-MAC10Arev5.
BOTTOM VIEW
Figure 20. 10-Lead MicroPak™
Package drawings are provided as a service to customers considering Fairchild components. Drawings maychange in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2007 Fairchild Semiconductor Corporation
FSA2269 / FSA2269TS • Rev. 1.1.5
www.fairchildsemi.com
11
Physical Dimensions (Continued)
0.10 C
1.40
A
B
2X
(9X)
0.563
1.70
0.663
1.80
1
PIN#1 IDENT
2.10
0.10 C
0.40
TOP VIEW
0.55 MAX.
2X
0.225
(10X)
RECOMMENDED
LAND PATTERN
(0.15)
0.10 C
0.08 C
9X
0.45
1.45
SEATING
PLANE
0.55
0.40
C
0.05
0.00
SIDE VIEW
1.85
0.35
(9X)
0.45
0.225
(10X)
3
OPTIONAL MINIMIAL
TOE LAND PATTERN
0.40
6
DETAIL A
1
NOTES:
PIN#1 IDENT
A. PACKAGE DOES NOT CONFORM TO
ANY JEDEC STANDARD.
B. DIMENSIONS ARE IN MILLIMETERS.
0.15
0.25
10
(10X)
0.10 C A B
0.05 C
BOTTOM VIEW
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
D. LAND PATTERN RECOMMENDATION IS
BASED ON FSC DESIGN ONLY.
0.55
0.45
E. DRAWING FILENAME: MKT-UMLP10Arev5.
F. FAIRCHILD SEMICONDUCTOR.
PACKAGE
EDGE
45°
LEAD
OPTION 2
LEAD
OPTION 1
0.25
0.15
DETAIL A
SCALE : 2X
SCALE : 2X
SCALE : 2X
Figure 21. 10-Lead, Quad Ultrathin Molded Leadless Package (UMLP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings maychange in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2007 Fairchild Semiconductor Corporation
FSA2269 / FSA2269TS • Rev. 1.1.5
www.fairchildsemi.com
12
Physical Dimensions (Continued)
0.03 C
F
E
A
0.80
(Ø0.200)
Cu Pad
2X
B
D
1.20 0.40
0.40
(Ø0.300)
Solder Mask
PIN 1 AREA
0.03 C
2X
TOP VIEW
RECOMMENDED LAND PATTERN
(NSMD PAD TYPE)
0.378±0.018
0.625
0.547
0.05 C
0.208±0.021
C
SEATING PLANE
D
SIDE VIEWS
0.005
C A B
NOTES:
0.80
Ø0.260±0.02
12X
A. NO JEDEC REGISTRATION APPLIES.
B. DIMENSIONS ARE IN MILLIMETERS.
0.40
D
C
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
1.20 0.40
B
A
(Y)±0.018
F
D. DATUM C IS DEFINED BY THE SPHERICAL
CROWNS OF THE BALLS.
1
2 3
(X)±0.018
E. PACKAGE NOMINAL HEIGHT IS 586 MICRONS
±39 MICRONS (547-625 MICRONS).
BOTTOM VIEW
F. FOR DIMENSIONS D, E, X, AND Y SEE
PRODUCT DATASHEET.
G. DRAWING FILENAME: MKT-UC012ACrev1.
Product-Specific Dimensions
Product
D
E
X
Y
FSA2269UCX
1.560 mm
1.160 mm
0.180 mm
0.180 mm
Figure 22. 12-Ball, Wafer Level Chip-Scale Package (WLCSP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings maychange in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2007 Fairchild Semiconductor Corporation
FSA2269 / FSA2269TS • Rev. 1.1.5
www.fairchildsemi.com
13
© 2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA2269 / FSA2269TS • Rev. 1.1.5
14
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