FSA4485UCX [ONSEMI]
USB-C™ Analog Audio Switch with Overvoltage Protection;
| 型号： | FSA4485UCX |
| 厂家： | 
ONSEMI |
| 描述： | USB-C™ Analog Audio Switch with Overvoltage Protection |
| 文件： | 总31页 (文件大小：855K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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USB Type-C Analog Audio
Switch with Over Voltage
Protection
FSA4485
PRODUCT SUMMARY
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General Description
The FSA4485 is a high performance USB Type−C port multimedia
switch to supports analog audio headsets. The FSA4485 allows
sharing of the USB Type−C port to pass USB2.0 signals, analog audio,
sideband use signals, and analog microphone signal. For enhanced
audio performance the FSA4485 incorporates MOSFET gate drivers
to support low resistance external analog ground switches. The
FSA4485 features Over Voltage Protection on all connector facing
pins as well as Over Current Protection for the analog ground switch.
WLCSP25
CASE 567YL
Features
MARKING DIAGRAM
• VCC Range from 2.7 V to 5.5 V (Primary)
• OVP Function on Common Node Pins
• Over Current Protection for Analog Ground Switch
• Analog Audio Device Unplug Detection
6F&K
&.&2&Z
1
• 16 V DC Tolerance on Connector Side Pins:
DP_R, DN_L, GBSUx, SBUx
6F
&K
&2
&Z
= Alphanumeric Device Marking
= Lot Run Code
= Alphabetical Year Code
= Assembly Plant Code
• 20 V DC Tolerance on CC_IN
• High Performance Audio/USB SW:
♦ Audio SW, THD+N < −109 dB; 1 VRMS, 32 ꢀ Load;
♦ USB SW, BW: 1 GHz
• 225 mꢀ (Typical) Sense to GSBUx on Resistance
ORDERING INFORMATION
See detailed ordering and shipping information on page 3 of
this data sheet.
• 78 mꢀ (Typical) SBUx to AGND on Resistance
• Programmable Gate Drive for Optional External SBUx to AGND
Switch
2
• 1.2 V Capable I C Interface
2
• Two I C Addresses
• Optional Normally Closed Configuration for SBU Data Switch to
Support Factory Test
• Moisture/Resistance Detection on DP_R, DN_L and SBUx
Applications
• Mobile Phone
• Tablet
• Notebook PC
• Media Player
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
January, 2021 − Rev. 0
FSA4485/D
FSA4485
PRODUCT BLOCK DIAGRAM
Block Diagram
Figure 1. Block Diagram
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2
FSA4485
PART NUMBERING
Ordering Information
Table 1. ORDERING INFORMATION
Part Number
Operating Temperature
−40 to +85°C
Package
Top Marking
FSA4485UCX
6F
25−Ball WLCSP, Non−JEDEC
2.16 × 2.16 mm, 0.4 mm Pitch
(Pb−Free)
PRODUCT PIN ASSIGNMENTS
Pin Configuration
Figure 2. Pin Configuration
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3
FSA4485
Pin Descriptions
PIN DESCRIPTIONS
Pin
A5
B5
D5
D4
E5
E4
C5
C4
A3
A2
C1
B2
B4
B3
E2
C3
D2
D1
E1
C2
D3
E3
B1
A1
A4
Name
Description
VCC
GND
Power Supply (2.7 to 5.5 V)
Device Ground
DN_R
DN_L
DP
USB/Audio Common Connector
USB/Audio Common Connector
USB Data (Differential +)
USB Data (Differential −)
Audio − Right Channel
Audio − Left Channel
Sideband Use 1
DN
R
L
SBU1
SBU2
MIC
Sideband Use 2
Microphone Signal
AGND
GD1
Audio Ground
External Gate Driver
External Gate Driver
GD2
SENSE
INT
Audio Ground Sense Output
2
I C Interrupt Output, Active Low (Open Drain)
Audio Accessory Attach Detection Input
Audio Sense Path 1 to Headset Jack GND
Audio Sense Path 2 to Headset Jack GND
Attach Detect Output, Active Low (Open Drain)
CC_IN
GSBU1
GSBU2
DET
2
SCL1/SDA2
SDA1/SCL2
S2H
I C Clock/Data
2
I C Data/Clock
Host Side Sideband use
S1H
Host Side Sideband use
EN
Device Enable and Precondition, 3−state Input with internal pull−up/pull−down
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4
FSA4485
MAXIMUM RATINGS
MAXIMUM RATINGS
Symbol
Parameter
Conditions
Min
−0.5
−0.5
−3.5
−0.5
−0.5
−3.5
−0.5
−50
Typ
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Max
6.5
20
Unit
V
VCC
Supply Voltage
CC Voltage
VCC_IN
CC_IN to GND
V
VSW_USB
VSW_SBU
USB Switch Voltage
SBU Switch Voltage
(DP_R, DN_L) to GND
16
V
(SBUx, GSBUx) to GND
16
V
VSW_HOST Host Side Switch Voltage
(DP, DN, S1H, S2H, SENSE, MIC) to GND
6.5
6.5
6.5
−
V
VSW_Audio Host Side Audio Switch Voltage (L, R) to GND
V
VCNTRL
IIK
Control Pin Voltage
DC Input Diode Current
USB Switch Current
SBU Switch Current
(SDA, SCL, EN, DET, INT) to GND
V
mA
mA
mA
mA
mA
mA
kV
kV
kV
ISW_USB
ISW_SBU
Between DP_R and DP or DN_L and DN
(S1H, S2H, MIC) to SBUx
GSBUx to SENSE
100
50
ISW_SENSE Sense Switch Current
ISW_AGND Analog Ground Current
100
500
250
−
SBUx to AGND
ISW_Audio
ESDHBM
Audio Switch Current
DP_R to R or DN_L to L
All Pins
−250
2
Human Body Model, JEDEC:
JS−001−2017
ESDHBM_Con
ESDCDM
Connector Side Pins and Power Pins
3.5
1
−
Charged Device Model,
JEDEC: JS−002−2018
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
THERMAL PROPERTIES
THERMAL PROPERTIES
Symbol
Parameter
Conditions
Min
−65
−40
Typ
Max
150
85
Unit
°C
T
STG
Storage Temperature
Operating Temperature
T
A
25
°C
1. Junction−to−ambient thermal resistance is a function of application and board layout. This data is measured with two−layer 2s2p boards in
accordance to JEDEC standard JESD51. Special attention must be paid not to exceed junction temperature T
at a given ambient
J(max)
temperature T .
A
OPERATING CONDITIONS
OPERATING CONDITIONS
Symbol
VCC
Parameter
Conditions
Min
2.7
0
Typ
−
Max
5.5
5.5
3.6
3.6
3.6
3
Unit
V
Supply Voltage
CC Voltage
VCC_IN
CC_IN to GND
−
V
VSW_USB
VSW_SBU
VSW_HOST
VSW_Audio
VCNTRL
USB Switch Voltage
SBU Switch Voltage
Host Side Switch Voltage
(DP_R, DN_L, DP, DN) to GND
(SBUx, GSBUx) to GND
0
−
V
0
−
V
(DP, DN, S1H, S2H, SENSE, MIC) to GND
0
−
V
Host Side Audio Switch Voltage (DN_L, DP_R, L, R) to GND
−3
−
V
Control Input Voltage
(EN, SCL1/SDA2, SDA1/SCL2)
VCC
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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5
FSA4485
ELECTRICAL SPECIFICATION TABLE
ELECTRICAL SPECIFICATIONS
(Minimum and maximum values are at VCC = 2.7 V to 5.5 V and T = −40°C to +85°C unless otherwise noted. Typical values are at
A
T = 25°C, VCC = 3.3 V)
A
Symbol
Parameter
Conditions
Min Typ Max Unit
CURRENT
ICC
Supply Current
USB switches on, SBUx to SBUx_H
switches on
65
65
ꢁ A
ꢁ A
ICC_AUDIO
Audio Supply Current
Audio switches closed, MIC switch
closed and
Audio GND switch closed
ICCZ
Quiescent Current, Software
Disabled
04H’b7 = 0, EN = Low or Float
5
ꢁ A
ꢁ A
ICCZ_H
Quiescent Current, Hardware Disable
EN = High
10
USB/AUDIO COMMON PINS
IOZ
USB Connector Side Off Leakage Current DP_R, DN_L = 0 V to 3.6 V
−3
3
3
ꢁ A
ꢁ A
IOFF
USB Connector Side Power Off Leakage DP_R, DN_L = 0 V to 3.6 V, VCC = 0 V −3
Current
VOV_TRIP
Input OVP Lockout
Rising Edge of DP_R, DN_L, SBUx,
GSBUx
4.7
5
5.2
V
V
VOV_HYS
Input OVP Hysteresis
DP_R, DN_L, SBUx, GSBUx
−
0.3
−
USB SWITCH
ION_USB
USB Switch ON Leakage Current
USB Host Side Off Leakage Current
DN_L, DP_R = 0 V to 3.6 V, DP, DN, R, −3
3
ꢁ
A
L = Float
IOZ_USB
DN, DP = 0 V to 3.6 V
−3
−3
3
3
ꢁ A
ꢁ A
IOFF_USB
USB Host Side Power Off Leakage
Current
DN, DP = 0 V to 3.6 V, VCC = 0 V
RON_USB
AUDIO SWITCH
ION_AUDIO
USB Switch On Resistance
ISW = 8 mA, VSW = 0.4 V
3
ꢀ
ON Leakage Current of Audio Switch
DN_L, DP_R = −3 V to 3.0 V, DP, DN,
R, L = Float
−6
6
1
ꢁ A
ꢁ A
IOFF_AUDIO
Power Off Leakage Current of Audio
Switch L, R
L, R = 0 V to 3 V; DP_R, DN_L = Float, −1
VCC = 0 V
RON_AUDIO
RON_FLAT
RSHUNT
Audio Switch On Resistance
ISW = 100 mA, VSW = −3 V to 3 V
VSW = −3.0 V to +3.0 V
1
ꢀ
Audio Switch On Resistance Flatness †
10
10
mꢀ
kꢀ
Pull Down Resistor on R/L Pin when Audio L = R = 3 V
Switch is Off
6
14
SBU COMMON PINS
IOZ_SBU
Off Leakage Current (SBU1, SBU2)
SBUx = 0 V to 3.6 V
−3
−3
3
3
ꢁ A
ꢁ A
IOFF_SBU
Power Off Leakage Current (SBU1, SBU2) SBUx = 0 V to 3.6 V, VCC = 0 V
SBU DATA SWITCH
ION_SxH
ON Leakage Current of SBU Switch
Off Leakage Current (S1H, S2H)
SBUx = 0 V to 3.6 V, SxH = Float
SxH =0 V to 3.6 V
−3
−1
−1
3
1
1
ꢁ A
ꢁ A
ꢁ A
ꢀ
IOZ_SxH
IOFF_SxH
Power Off Leakage Current (S1H, S2H)
SxH =0 V to 3.6 V, VCC = 0 V
RON_SxH
SBU Switch On Resistance to (S1H, S2H) VSW = 0 V to 3.6 V, ISW = 20 mA
3
MIC SWITCH
ION_MIC
ON Leakage Current of MIC Switch
Off Leakage Current (MIC)
SBUx = 0 V to 3.6 V, MIC = Float
MIC = 0 V to 3.6 V
−3
−1
3
1
ꢁ A
ꢁ A
IOZ_MIC
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6
FSA4485
ELECTRICAL SPECIFICATIONS (continued)
(Minimum and maximum values are at VCC = 2.7 V to 5.5 V and T = −40°C to +85°C unless otherwise noted. Typical values are at
A
T = 25°C, VCC = 3.3 V)
A
Symbol
MIC SWITCH
IOFF_MIC
Parameter
Conditions
Min Typ Max Unit
Power Off Leakage Current (MIC)
SBU Switch On Resistance to (MIC)
MIC = 0 V to 3.6 V, VCC = 0 V
−1
1
ꢁ A
RON_MIC
VSW = 0 V to 3.6 V, ISW = 20 mA
3
ꢀ
AGND SWITCH
RON_AGND
IOC_TRIP
SBUx Switch On Resistance to AGND
Input OCP Lockout SBUx to AGND
ISW = 100 mA on SBUx
78
125 mꢀ
04h’b0 = 1, 07h = xx010xxxb or
xxxxx010b
0.75 1.5
3.0
A
SENSE SWITCH
ION_SENSE
ON Leakage Current of SENSE switch
On GSBUx = 0 V to 1.0 V,
Off GSBUx = 2 V, Sense = Float
−2
2
ꢁ
A
IOZ_SENSE
IOZ_GSBU
IOFF_SENSE
IOFF_GSBU
RON_SENSE
CC_IN PIN
VTH_L_CC
VTH_H_CC
IIN_CC
Off Leakage Current of SENSE
Off Leakage Current of GSBUx
Power Off Leakage Current of SENSE
Power Off Leakage Current of GSBUx
Sense Switch On Resistance
Sense = 0 V to 1.0 V
−3
−3
−3
−3
3
3
3
3
ꢁ A
ꢁ A
ꢁ A
ꢁ A
GSBUx = 0 V to 3.6 V
Sense = 0 V to 1.0 V, VCC = 0 V
GSBUx = 0 V to 3.6 V, VCC = 0 V
IOUT = 100 mA, VSW =1 V
250 400 mꢀ
Input Low Threshold
1.2
1.5
V
V
Input High Threshold
CC_IN Input Leakage Current
CC_IN = 0 V to 5.5 V
1
ꢁ
A
EN PIN
VIH_EN
EN Input Voltage High
1.1
V
V
VIL_EN
EN Input Voltage Low
0.5
10
RFLOAT_EN
IIN_EN
Resistance from EN to GND
EN Input Leakage Current
900
Kꢀ
ꢁ A
EN = 0 V to 5.5 V
IOUT = 2 mA
DET & INT PIN
VOL
Output Low Voltage
0.4
0.36
V
2
I C PINS
VIL_I2C
VIH_I2C
IIN_I2C
Low Level Input Voltage
High Level Input Voltage
Input Current
V
V
0.84
SCL1/SDA2,
SDA1/SCL2 = 0 V to 3.6 V
−2
2
ꢁ
A
VOL_I2C
VOH_I2C
Low Level Output Voltage
Low Level Output Current
IOL = 2 mA
0.3
V
VOL_I2C = 0.2 V
10
mA
GATE DRIVE
I_GATE
Gate Drive Current (GD1, GD2) †
Gate Drive Voltage (GD1, GD2) †
Gate Drive Discharge Resistance †
V_GATE = 3 V
ILoad = 200 nA
2
6
ꢁ A
V
V_GATE
R_GATE
1.0
Mꢀ
AUDIO SWITCH
tDELAY_Audio
Audio Switch Turn On Delay Time †
DP_R = DN_L = 1 V, RL = 32 ꢀ,
100
150
ꢁ s
ꢁ s
SLOW_TURN_ON = 0b
tDELAY_Audio_Slow
Audio Switch Turn On Delay with Slow
Turn On †
DP_R = DN_L = 1 V, RL = 32 ꢀ,
SLOW_TURN_ON = 1b
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FSA4485
ELECTRICAL SPECIFICATIONS (continued)
(Minimum and maximum values are at VCC = 2.7 V to 5.5 V and T = −40°C to +85°C unless otherwise noted. Typical values are at
A
T = 25°C, VCC = 3.3 V)
A
Symbol
AUDIO SWITCH
tRISE_Audio
Parameter
Conditions
Min Typ Max Unit
Audio Switch Turn On Rise Time †
DP_R = DN_L = 1 V, RL = 32 ꢀ,
SLOW_TURN_ON = 0b
26
ꢁ s
ꢁ s
tRISE_Audio_Slow
Audio Switch Turn On Rise Time with Slow DP_R = DN_L = 1 V, RL = 32 ꢀ,
180
Turn On †
SLOW_TURN_ON = 1b
tOFF_Audio
Audio Switch Turn Off Time †
Crosstalk between Left and Right †
DP_R = DN_L = 1 V, RL = 32 ꢀ
15
ꢁ s
XTALK_Audio
f = 1 kHz, RL = 50 ꢀ to GND,
VSW = 1 VRMS
−100
dB
BW_Audio
−3dB Bandwidth †
VSW = 200 mV, RL = 50 ꢀ
550
MHz
dB
OIRR_Audio
Off Isolation †
F = 1 kHz, RL = 50 ꢀ, CL = 0 pF,
VSW = 1 VRMS
−100
THD+N_600
THD+N_32
THD+N_16
PSRR_Audio
Total Harmonic Distortion + Noise
RL = 600 ꢀ, f = 20 Hz~20 kHz,
−100
−109
−108
−70
dB
dB
dB
dB
Performance with A−weighting Filter †
VSW = 2 VRMS
Total Harmonic Distortion + Noise
Performance with A−weighting Filter †
RL = 32 ꢀ, f = 20 Hz~20 kHz,
VSW = 1 VRMS
Total Harmonic Distortion + Noise
Performance with A−weighting Filter †
RL = 16 ꢀ, f = 20 Hz~20 kHz,
VSW = 0.5 VRMS
Power Supply Rejection Ratio to Audio † Supply Noise = 300mVpp, f = 217 Hz,
RL = 50 ꢀ, Audio Switch Closed
USB SWITCH
tON_USB
tOFF_USB
BW_USB
USB Switch Turn−on Time †
USB Switch Turn −off Time †
−3 dB Differential Bandwidth †
Insetrion Loss †
DP_R = DN_L = 1.5 V, RL = 50 ꢀ
DP_R = DN_L = 1.5 V, RL = 50 ꢀ
RL = 50 ꢀ
33
15
ꢁ s
ꢁ s
1
GHz
dB
IL_USB
RL = 50 ꢀ, f = 720 MHz
−2.2
-100
OIRR_USB
Off Isolation between DP, DN and
Common Node Pins †
dB
f = 1 kHz, RL = 50 ꢀ, CL = 0 pF,
VSW = 1 VRMS
tOVP_USB
DP_R and DN_L pins OVP Response
Time †
Rising edge of DP_R or DN_L ≥ 4.8 V
to falling edge of DP or DN or L or
R ≤ 4.8 V, RL on DP or DN = 1 kꢀ
600
ns
MIC/AUDIO GROUND SWITCH
tDELAY_MIC
tDELAY_MIC_Slow
tRISE_MIC
MIC Switch Turn On Delay Time with Slow SBUx = 1 V, RL = 50 ꢀ,
90
200
40
ꢁ s
ꢁ s
ꢁ s
ꢁ s
ꢁ s
Turn On Disabled †
SLOW_TURN_ON = 0b
MIC Switch Turn On Delay with Slow Turn SBUx = 1 V, RL = 50 ꢀ,
On Enabled †
SLOW_TURN_ON = 1b
MIC Switch Turn On Rising Time with Slow SBUx = 1 V, RL = 50 ꢀ,
Turn On Disabled †
SLOW_TURN_ON = 0b
tRISE_MIC_Slow
tDELAY_AGND
MIC Switch Turn On Rising Time with Slow SBUx = 1 V, RL = 50 ꢀ,
300
660
Turn On Enabled †
SLOW_TURN_ON = 1b
AGND Switch Turn On Time with Slow
Turn On Disabled †
SBUx pulled up to 0.5 V by 16 ꢀ,
AGND connect to GND,
SLOW_TURN_ON = 0b
tDELAY_AGND_Slow AGND Switch Turn On Time with Slow
Turn On Enabled †
SBUx pulled up to 0.5 V by 16 ꢀ,
AGND connect to GND,
1100
270
ꢁ s
ꢁ s
SLOW_TURN_ON = 1b
tRISE_AGND
AGND Switch Turn On Rise Time with
Slow Turn On Disabled †
SBUx pulled up to 0.5 V by 16 ꢀ,
AGND connect to GND,
SLOW−TURN_ON = 0b
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FSA4485
ELECTRICAL SPECIFICATIONS (continued)
(Minimum and maximum values are at VCC = 2.7 V to 5.5 V and T = −40°C to +85°C unless otherwise noted. Typical values are at
A
T = 25°C, VCC = 3.3 V)
A
Symbol
Parameter
Conditions
Min Typ Max Unit
MIC/AUDIO GROUND SWITCH
tRISE_AGND_Slow
AGND Switch Turn On Rise Time with
Slow Turn On Enabled †
SBUx pulled up to 0.5 V by 16 ꢀ,
AGND connect to GND,
SLOW−TURN_ON = 1b
720
ꢁ s
tOFF_MIC
MIC Switch Turn Off Time †
AGND Switch Turn Off Time †
SBUx = 2.5 V, RL = 50 ꢀ
15
15
ꢁ s
ꢁ s
tOFF_AGND
SBUx: Vsource = 2.5 V,
clamp to 10 mA
BW
MIC Switch Bandwidth †
RL = 50 ꢀ
35
MHz
tOC_DEB
SBUx to AGND Over Current Debounce
Time †
500
ꢁ
s
SBU SWITCH
tON_SBU
SBUx_H Switch Turn On Time †
SBUx_H Switch Turn Off Time †
Bandwidth †
SBUx = 2.5 V, RL = 50 ꢀ
SBUx = 2.5 V, RL = 50 ꢀ
RL = 50 ꢀ
75
15
ꢁ s
ꢁ s
tOFF_SBU
BW_SBU
35
MHz
ns
tOVP_SBU
SBUx Pins OVP Response Time †
Rising edge of SBUx ≥ 4.8 V to falling
edge of SxH ≤ 4.8 V, RL on SxH = 1 kꢀ
250
SENSE SWITCH
tDELAY_SENSE
Sense Switch Turn On Delay with Slow
Turn On Disabled †
GSBUx = 1 V, RL = 50 ꢀ,
150
110
110
110
ꢁ s
ꢁ s
ꢁ s
ꢁ s
SLOW_TURN_ON = 0b
tDELAY_SENSE_Slow Sense Switch Turn On Delay with Slow
Turn On Enabled †
GSBUx = 1 V, RL = 50 ꢀ,
SLOW_TURN_ON = 1b
tRISE_SENSE
Sense Switch Turn On Rise Time with
Slow Turn On Disabled †
GSBUx = 1 V, RL = 50 ꢀ,
SLOW_TURN_ON = 0b
tRISE_SENSE_Slow
Sense Switch Turn On Rise Time with
Slow Turn On Enabled †
GSBUx = 1 V, RL = 50 ꢀ,
SLOW_TURN_ON = 1b
tOFF_SENSE
tOVP_SENSE
Sense Switch Turn Off Time †
GSBUx = 1 V, RL = 50 ꢀ
15
ꢁ
s
GSBUx Pins OVP Response Time †
Rising edge of GSBUx ≥ 4.8 V to
falling edge of SENSE ≤ 4.8 V, RL on
SENSE = 1 kꢀ
250
ns
BW_SENSE
DET DELAY
Bandwidth †
RL = 50 ꢀ
108
2.5
MHz
tDELAY_DET
DET Response Delay †
Transition from High−Z to 0 V
ꢁ
s
2
I C SPECIFICATIONS
fSCL
tHD; STA
tLOW
I2C_SCL Clock Frequency
400 kHz
Hold Time (Repeated) START Condition †
Low Period of I2C_SCL Clock †
High Period of I2C_SCL Clock †
0.6
1.3
0.6
0.6
ꢁ s
ꢁ s
ꢁ s
ꢁ s
tHIGH
tSU; STA
Set−up Time for Repeated START
Condition †
tHD; DAT
tSU; DAT
tr
Data Hold Time †
0
0.9
ꢁ s
ns
ns
Data Set−up Time †
100
Rise Time of I2C_SDA and I2C_SCL
Signals †
20 +
0.1Cb
300
300
tf
Fall Time of I2C_SDA and I2C_SCL
Signals †
20 +
0.1Cb
sn
tSU; STO
Set−up Time for STOP Condition †
0.6
ꢁ
s
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9
FSA4485
ELECTRICAL SPECIFICATIONS (continued)
(Minimum and maximum values are at VCC = 2.7 V to 5.5 V and T = −40°C to +85°C unless otherwise noted. Typical values are at
A
T = 25°C, VCC = 3.3 V)
A
Symbol
Parameter
Conditions
Min Typ Max Unit
2
I C SPECIFICATIONS
tBUF
1.3
0
ꢁ s
Bus−Free Time between STOP and
START Conditions †
tSP
Pulse Width of Spikes that Must Be
Suppressed by the Input Filter †
50
ns
CAPACITANCE
CON_USB
On Capacitance of USB Common Pins † f = 1 MHz, 100 mVPK−PK, 100 mV DC
Off Capacitance of USB Common Pins † f = 1 MHz, 100 mVPK−PK, 100 mV DC
8.5
9.5
3.0
34
pF
pF
pF
pF
pF
pF
pF
pF
COFF_ USB
COFF_USBHost
CON_SENSE
COFF_SENSE
CON_MIC
Off Capacitance of USB Host Pins †
On Capacitance of GSBUx †
Off Capacitance of GSBUx †
f = 1 MHz, 100 mVPK−PK, 100 mV DC
f = 1 MHz, 100 mVPK−PK, 100 mV DC
f = 1 MHz, 100 mVPK−PK, 100 mV DC
44
On Capacitance of SBUx to MIC Switch † f = 1 MHz, 100 mVPK−PK, 100 mV DC
115
8.5
94.5
COFF_MIC
Off Capacitance of MIC †
f = 1 MHz, 100 mVPK−PK, 100 mV DC
f = 1 MHz, 100 mVPK−PK, 100 mV DC
CON_AGND
On Capacitance of SBUx to AGND
Switch †
CON_SBU
COFF_SBU
COFF_SBUHost
CCNTRL
On Capacitance of SBUx to SxH Switch † f = 1 MHz, 100 mVPK−PK, 100 mV DC
Off Capacitance of SBUx †
f = 1 MHz, 100 mVPK−PK, 100 mV DC
On Capacitance of SBUx to SxH Switch † f = 1 MHz, 100 mVPK−PK, 100 mV DC
Control Input Pin Capacitance †
f = 1 MHz, 100 mVPK−PK, 100 mV DC
114
108
9.0
5.0
pF
pF
pF
pF
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Guarantee Levels:
†Guaranteed by Design. Characterized on the ATE or Bench.
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10
FSA4485
FUNCTIONAL SPECIFICATIONS
I2C Interface
2
2
2
The FSA4485 includes a full I C slave controller. The I C
slave fully complies with the I C specification version 2.1
requirements. This block is designed for fast mode, 400 kHz,
signals. Examples of an I C write and read sequence are
The I C Address can be selected by routing the SDA/SCL
2
signals per the Table 2 below. The FSA4485 will detect the
clock and automatically configure the I/O and address. The
I C interface will operate with VDDIO pull up from 1.2 V
2
2
shown in below figures respectively.
to 1.8 V.
Table 2. I2C SLAVE ADDRESS
SDA
SDA1
SDA2
SCL
SCL1
SCL2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
1
1
0
0
0
0
0
0
0
0
1
1
0
1
Figure 3. I2C Write Example
Figure 4. I2C Read Example
Over Voltage Protection
I_OCP_AGND register. The SBUx to AGND switch can be
closed after an OCP event by setting AGND_EN = 1b.
FSA4485 features over voltage protection (OVP) on the
receptacle side pins. This will automatically switch open the
internal signal routing path if the input voltage exceeds the
OVP threshold. If OVP has occurred an interrupt signal will
be send using the INT signal. The OVP_INTERRUPT
register will indicate which pin had the OVP event. If the
over voltage is no longer present, indicated by the
OVP_STAT register, the signal path can be restored
manually from the SWITCH_SEL register.
MIC Switch Auto−Off
MIC switch auto−off is controlled by the
MIC_AUTO_OFF register (12h, Bit 2). If enabled, when the
port is configured for audio (L, R, MIC, AGND switches are
closed) and a detach is detected (CC_IN > 1.5 V) the
receptacle side of the MIC switch will connect to ground for
50 ꢁ s prior to becoming high impedance.
Headset Detection
Over Current Protection
Headset detection is performed by the CC_IN input and
indicated by the CC_IN_STAT register (11h, Bit 2). Headset
detection can also be indicated by the DET output. DET is
an Open Drain user configurable attach/detach detection
When the EN_OCP register is set to Enable and the SBUx
switch is closed to AGND Over Current Protection (OCP)
will be enabled. OCP monitors the voltage drop from SBUx
to AGND across the closed switch to limit the current to
1.5 A for 500 ꢁ s. This will prevent a short from VBUS to
AGND through SBUx. OCP will not automatically reset.
When an OCP event occurs an interrupt will be sent to the
processor. The interrupt is cleared by reading the
2
output. It can be configured or disabled from the I C register
DET_FUNCT. The DET output once triggered can be
cleared by reading the Detection Interrupt Register
I_DET_FUNCT. When configured for Type−C or Audio
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11
FSA4485
Accessory attach detection DET will clear automatically
when the Type−C device or audio accessory is detached.
Figure 5. Detect Pin Function
Gate Drive
The gate to source voltage (Vgs) will be held at V_GATE
to ensure low on resistance. The maximum gate drive
current can be selected from the I C register
The FSA4485 includes two gate drive outputs GD1 and
GD2 to allow a low resistance external switch to be used for
AGND. The gate drives are enabled from the I C register
2
2
GATE_DRIVE_CURR to control switch turn on time.
GATE_DRIVE_EN and will follow automatic orientation
detection. When enabled, if SBU1 = AGND then GD1 =
High, If SBU2 = AGND then GD2 = High.
GATE DRIVE CURRENT
Register Value
GATE_DRIVE_CURR
1 ꢁ A
00b
01b
10b
11b
1.5 ꢁ A
2.0 ꢁ A (default)
3.0 ꢁ A
EN and Factory Mode
be floated or connected to a GPIO in High−Z state at power
up. For typical conditions EN can be tied to GND. EN is tied
to GND using a 10 kꢀ resistor if also using the EN input to
disable the device. It is not recommended that the EN =
High−Z condition be used if the system uses SBU for the
DisplayPort Aux channel.
The enable input (EN) is a 3 state input which sets the USB
and SBU data switch initial conditions during device power
up. It has a weak internal pull down which will set the default
condition to High−Z if no input level is present. For
applications using the SBU signals for data the EN input can
Figure 6. EN Input Truth Table
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12
FSA4485
Moisture Detection
The detection result will be saved in the RES_VALUE
register (14h). The measurement range is from 1 kꢀ to
2.56 Mꢀ and is controlled by the RES_DET_RANGE
register (12h, Bit 5). Detection can be performed manually
or an automatic detection interval can be set to 100 ms, 1 s
or 10 s by the RED_DET_INTV register (16h).
The moisture detection function is controlled the
RES_DETECT register (12h, Bit 1). It will detect moisture
or any foreign object that creates resistance between the
receptacle side pins and ground. During resistance
detection, the switch associated with the pin will be open.
Figure 7. Moisture Detection Procedure
Test Diagrams
Figure 9. On Resistance
Figure 8. Off Leakage (IOZ)
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13
FSA4485
Figure 10. On Leakage
Figure 11. Power Off Leakage (IOFF)
Figure 12. Test Circuit Load
Figure 13. Manual Mode Turn On/Off Waveform
Figure 14. Bandwidth
Figure 15. Channel Off Isolation
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14
FSA4485
Figure 16. Adjacent Channel Crosstalk
Figure 17. Channel Off Capacitance
Figure 18. Channel Off Capacitance
Figure 19. Total Harmonic Distortion (THD + N)
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15
FSA4485
REGISTER MAPPING TABLE
REGISTER MAPPING
Read Only
Write Only
Read / Write
Bit[2]
Read / Clear
Write / Clear
Bit[0]
Address
0x00
Name
DEVID
Bit[7]
Bit[6]
Bit[5]
Bit[4]
VERID
Bit[3]
Bit[1]
REVID
VENID
0x01
OVP_MASK
OVP_INTERRUPT
OVP_STAT
M_OCP_AGND
I_OCP_AGND
Reserved
M_OVP_ALL
I_OVP_ALL
M_OVP_DP_R
I_OVP_DP_R
M_OVP_DN_L
I_OVP_DN_L
M_OVP_SBU1
I_OVP_SBU1
M_OVP_SBU2
I_OVP_SBU2
M_OVP_GSBU1
I_OVP_GSBU1
M_OVP_GSBU2
I_OVP_GSBU2
0x02
0x03
OCP_STAT
_AGND
OVP_STAT
_DP_R
OVP_STAT
_DN_L
OVP_STAT
_SBU1
OVP_STAT
_SBU2
OVP_STAT
_GSBU1
OVP_STAT
_GSBU2
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
SWITCH_EN
SWITCH_SEL
DEVICE_EN
Reserved
S1H_EN
S2H_EN
DN_L_EN
DP_R_EN
SENSE_EN
SENSE_SEL
MIC_EN
AGND_EN
S1H_SEL
S2H_SEL
DN_L_SEL
DP_R_SEL
MIC_SEL
AGND_SEL
SWITCH_STAT_1
SWITCH_STAT_2
AUDIO_SLO W_LEFT
AUDIO_SLO W_RIGHT
MIC_SLOW
Reserved
SENSE_STAT
SBU2_STAT
AUDIO_SLOW_LEFT
DP_R_STAT
DN_L_STAT
Reserved
SBU1_STAT
AUDIO_SLOW_RIGHT
MIC_SLOW
SENSE_SLOW
SENSE_SLOW
AGND_SLOW
AGND_SLOW
L2R_EN_DELAY
MIC2L_EN_ DELAY
L2R_EN_DELAY
MIC2L_EN
_DELAY
0x0F
0x10
0x11
0x12
SENSE2L_EN_DELAY
AGND2L_EN_DELAY
AUDIO_ACC_STAT
FUNCTION_ EN
SENSE2L_EN_DELAY
AGND2L_EN_DELAY
Reserved
HIZ_ACC_DET
CC_IN_STAT
DET_STAT
DET_FUNCT
RES_DET
_RANGE
SLOW_TURN
_ON
MIC_AUT_OFF
RES_DETECT
AUDIO_JACK
_DET
0x13
0x14
0x15
0x16
0x17
RES_PIN_SEL
RES_VALUE
Reserved
RES_PIN_SEL
RES_VALUE
RES_DET_THRESH
RES_DET_THRESH
RES_DET_INTV
AUDIO_JACK_STAT
Reserved
UNKNOWN
RES_DET_INTV
Reserved
4POLE_A
I_DET_FUNCT
M_DET
4POLE_B
3POLE
NO_AUDIO_ACC
_AUDIO_ACC
0x18
0x19
DET_INTERRUPT
DET_MASK
Reserved
Reserved
I_DISABLE
I_AUDIO_JACK
_DET
I_LOW_RES
M_LOW_RES
I_RES_DET
_COMP
M_DISABLE
M_AUDIO
_JACK_DET
M_RES
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
AUDIO_JACK_DET1
AUDIO_JACK_DET2
MIC_DET_TH_LOW
MIC_DET_TH_UP
I2C_RESET
AUDIO_JACK_DET1
AUDIO_JACK_DET2
MIC_DET_TH_LOW
MIC_DET_TH_UP
Reserved
I2C_RESET
CURR_SOURCE_SET
CURR_SOURCE_STAT
GATE_DRIVE
Reserved
Reserved
CURR_SOURCE_SET
CURR_SOURCE_STAT
GATE_DRIVE_CURR
Reserved
GATE_DRIVE
_EN
0x22
0x23
PROTECTION_EN
Reserved
EN_OVP
OCP1
EN_OCP
OCP2
PROTECTION_STAT
Reserved
USB_OVP
GSBU_OVP
SBU1_OVP
SBU2_OVP
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16
FSA4485
REGISTER DETAILS
Table 3. DEVICE ID
0x00 DEVID
Name
VENID
Default = 00001001
Description
Bit
7:6
5:3
Default
00
Type
Read
Read
Vendor ID
Revision ID Low: 001h
VERID
001
A_[Revision ID]: 0x001 (e.g. A_revA)
B_[Revision ID]: 0x010 (e.g. B_revA)
C_[Revision ID]: 0x011 (e.g. C_revA) etc
Revision ID Low: 001h
2:0
REVID
001
Read
A_[Revision ID]: 0x001 (e.g. A_revA)
B_[Revision ID]: 0x010 (e.g. A_revB)
C_[Revision ID]: 0x011 (e.g. A_revC) etc
Table 4. OVP/OCP INTERRUPT MASK
0x01 OVP_MASK
Default = 00000000
Description
0b: Do not mask OCP interrupt
Bit
Name
Default
Type
7
M_OCP_AGND
0
R/W
1b: Mask OCP interrupt on SBUx to AGND
0b: OCP Mask is controled by bit 7, OVP Mask is controled by bit [5:0]
1b: Mask OVP/OCP interrupt on all connector side pins
6
5
4
3
2
1
0
M_OVP_ALL
M_OVP_DP_R
M_OVP_DN_L
M_OVP_SBU1
M_OVP_SBU2
M_OVP_GSBU1
M_OVP_GSBU2
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0b: Do not mask OVP interrupt
1b: Mask OVP interrupt on DP_R
0b: Do not mask OVP interrupt
1b: Mask OVP interrupt on DN_L
0b: Do not mask OVP interrupt
1b: Mask OVP interrupt on SBU1
0b: Do not mask OVP interrupt
1b: Mask OVP interrupt on SBU2
0b: Do not mask OVP interrupt
1b: Mask OVP interrupt on GSBU1
0b: Do not mask OVP interrupt
1b: Mask OVP interrupt on GSBU2
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17
FSA4485
Table 5. OVP/OCP INTERRUPT FLAG
0x02 OVP_INTERRUPT
Default = 00000000
Description
Bit
Name
Default
Type
0b: OCP has not occured
1b: OCP event has occured on SBUx to AGND
7
I_OCP_AGND
0
R/CLR
0b: OVP or OCP event has not occurred
1b: OVP or OCP event has occurred
6
5
4
3
2
1
0
I_OVP_ALL
I_OVP_DP_R
I_OVP_DN_L
I_OVP_SBU1
I_OVP_SBU2
I_OVP_GSBU1
I_OVP_GSBU2
0
0
0
0
0
0
0
R/CLR
R/CLR
R/CLR
R/CLR
R/CLR
R/CLR
R/CLR
0b: OVP event has not occured
1b: OVP event has occurred on DP_R
0b: OVP event has not occured
1b: OVP event has occurred on DN_L
0b: OVP event has not occured
1b: OVP event has occurred on SBU1
0b: OVP event has not occured
1b: OVP event has occurred on SBU2
0b: OVP event has not occured
1b: OVP event has occurred on GSBU1
0b: OVP event has not occured
1b: OVP event has occurred on GSBU2
Table 6. OVP/OCP STATUS
0x03 OVP_STAT
Default = 00000000
Bit
Name
Default
Type
Description
7
Reserved
0
Read
Do Not Use
0b: OCP event has not occured
1b: OCP event has occurred on SBUx to AGND
6
5
4
3
2
1
0
OCP_STAT_AGND
OVP_STAT_DP_R
OVP_STAT_DN_L
OVP_STAT_SBU1
OVP_STAT_SBU2
OVP_STAT_GSBU1
OVP_STAT_GSBU2
0
0
0
0
0
0
0
Read
Read
Read
Read
Read
Read
Read
0b: OVP event has not occured
1b: OVP event has occurred on DP R
0b: OVP event has not occured
1b: OVP event has occurred on DN L
0b: OVP event has not occured
1b: OVP event has occurred on SBU1
0b: OVP event has not occured
1b: OVP event has occurred on SBU2
0b: OVP event has not occured
1b: OVP event has occurred on GSBU1
0b: OVP event has not occured
1b: OVP event has occurred on GSBU2
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18
FSA4485
Table 7. SWITCH ENABLE
0x04 SWITCH_EN
Name Default
Default = 10011000
Description
Bit
Type
0b: Device Disabled, L and R = 10 kꢀ Pull Down, All Other Switches = High−Z,
this overrides EN = Low
7
DEVICE_EN
1
R/W
1b: Device Enabled, All Switches are Enabled, this can be overridden by EN = High
0b: Switch Disabled, S1H = High−Z
1b: SBUx to S1H Switch Enabled
6
5
4
3
S1H_EN
S2H_EN
0
0
1
1
R/W
R/W
R/W
R/W
0b: Switch Disabled, S2H = High−Z
1b: SBUx to S2H Switch Enabled
0b: Switch Disabled, DN = High−Z, L = 10 kꢀ Pull Down
1b: DN L Switch Enabled
DN_L_EN
DP_R_EN
0b: Switch Disabled, DP = High−Z, R = 10 kꢀ Pull Down
1b: DP R Switch Enabled
0b: Switch Disabled, SENSE, GSBU1 and GSBU2 = High−Z
1b: SENSE Switch Enabled
2
1
SENSE_EN
MIC_EN
0
0
R/W
R/W
0b: Switch Disabled, MIC = High−Z
1b: MIC to SBUx Switch Enabled
If S1H EN and/or S2H EN = 1b then MIC will = High−Z when MIC EN = 1b
0b: Switch Disabled, AGND = High−Z
0
AGND_EN
0
R/W
1b: AGND to SBUx Switch Enabled
If S1H EN and/or S2H EN = 1b then AGND will = High−Z when AGND EN = 1b
Table 8. SWITCH SELECT
0x05 SWITCH_SEL
Default = 00011000
Bit
Name
Default
Type
Description
7
Reserved
0
R/W
Do Not Use
0b: S1H to SBU1 switch is CLOSED
1b: S1H to SBU2 switch is CLOSED
6
5
4
3
S1H_SEL
S2H_SEL
DN_L_SEL
DP_R_SEL
0
0
1
1
R/W
R/W
R/W
R/W
0b: S2H to SBU2 switch is CLOSED
1b: S2H to SBU1 switch is CLOSED
0b: DN_L to L switch is CLOSED
1b: DN L to DN switch is CLOSED
0b: DP_R to R switch is CLOSED
1b: DP R to DP switch is CLOSED
0b: SENSE to GSBU1 switch is CLOSED
1b: SENSE to GSBU2 switch is CLOSED
2
1
SENSE_SEL
MIC_SEL
0
0
R/W
R/W
0b: MIC to SBU2 switch is CLOSED
1b: MIC to SBU1 switch is CLOSED
If AGND_SEL = 0b and MIC_SEL = 1b when AGND_EN and MIC_EN = 1b then
MIC = High−Z If AGND SEL = 1b and MIC SEL = 0b when AGND EN and
MIC EN = 1b then MIC = High−Z
0b: AGND to SBU1 switch is CLOSED
1b: AGND to SBU2 switch is CLOSED
0
AGND_SEL
0
R/W
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FSA4485
Table 9. SWITCH STATUS 1
0x06 SWITCH_STAT_1
Name Default
Default = 00000000
Description
Bit
7:6
5:4
Type
Read Do Not Use
Reserved
00
00
00b: SENSE switch is OPEN
01b: SENSE switch is CLOSED to GSBU1
10b: SENSE Switch is CLOSED to GSBU2
11b: Not Valid
SENSE_STAT
Read
Read
Read
00b: DP_R switch is OPEN
01b: DP_R switch is CLOSED to DP
10b: DP_R Switch is CLOSED to R
11b: Not Valid
3:2
1:0
DP_R_STAT
DN_L_STAT
00
00
00b: DN_L switch is OPEN
01b: DN_L switch is CLOSED to DN
10b: DN_L Switch is CLOSED to L
11b: Not Valid
Table 10. SWITCH STATUS 2
0x07 SWITCH_STAT_2
Default = 00000000
Description
Bit
7:6
5:3
Name
Default
Type
Reserved
SBU2_STAT
00
Read Do Not Use
Read 000b: SBU2 switch is OPEN
000
001b: SBU2 switch is CLOSED to MIC
010b: SBU2 Switch is CLOSED to AGND
011b: SBU2 Switch is CLOSED to S1H
100b: SBU2 Switch is CLOSED to S2H
101b: SBU2 Switch is CLOSED to both S1H and S2H
110b: Not Valid
111b: Not Valid
2:0
SBU1_STAT
000
Read 000b: SBU1 switch is OPEN
001b: SBU1 switch is CLOSED to MIC
010b: SBU1 Switch is CLOSED to AGND
011b: SBU1 Switch is CLOSED to S1H
100b: SBU1 Switch is CLOSED to S2H
101b: SBU1 Switch is CLOSED to both S1H and S2H
110b: Not Valid
111b: Not Valid
Table 11. AUDIO SWITCH LEFT CHANNEL SLOW TURN ON TIME
0x08 AUDIO_SLOW_LEFT
Default = 00000001
Description
Bit
Name
Default
Type
7:0
AUDIO_SLOW_LEFT 00000001
R/W
00000000b: = 180 ꢁ s
00000001b: = 330 ꢁ s (DEFAULT)
Typical turn on time (tON) is incremented approximately 150 ꢁ s per bit
Table 12. AUDIO SWITCH RIGHT CHANNEL SLOW TURN ON TIME
0x09 AUDIO_SLOW_RIGHT
Default = 00000001
Description
Bit
Name
Default
Type
7:0
AUDIO_SLOW_RIGHT 00000001
R/W
00000000b: = 180 ꢁ s
00000001b: = 330 ꢁ s (DEFAULT)
Typical turn on time (tON) is incremented approximately 150 ꢁ s per bit
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20
FSA4485
Table 13. MIC SWITCH SLOW TURN ON TIME
0x0A MIC_SLOW
Default = 00000010
Description
Bit
Name
Default
Type
7:0
MIC_SLOW
00000010
R/W 00000000b: = Do Not Use
00000001b: = 370 ꢁ s
00000010b: = 520 ꢁ s (DEFAULT)
Typical turn on time (tON) is incremented approximately 150 ꢁ s per bit
Table 14. SENSE SWITCH SLOW TURN ON TIME
0x0B SENSE_SLOW
Default = 00000001
Description
Bit
Name
Default
Type
7:0
SENSE_SLOW
00000001
R/W 00000000b: = 160 ꢁ s
00000001b: = 220 ꢁ s (DEFAULT)
Typical turn on time (tON) is incremented approximately 60 ꢁ s per bit
Table 15. AGND SWITCH SLOW TURN ON TIME
0x0C AGND_SLOW
Default = 00000001
Description
Bit
Name
Default
Type
R/W 00000000b: = 900 ꢁ s
7:0
AGND_SLOW
00000001
00000001b: = 1750 ꢁ s (DEFAULT)
Typical turn on time (tON) is incremented approximately 850 ꢁ s per bit
Table 16. TIMING DELAY BETWEEN AUDIO L AND AUDIO R SWITCH ENABLE
0x0D L2R_EN_DELAY
Default = 00000000
Description
Bit
Name
Default
00000000
Type
7:0
L2R_EN_DELAY
R/W 00000000b: = 0 ꢁ s (DEFAULT)
00000001b: = 100 ꢁ s
……..
11111111b: = 25500 ꢁ s
Increment size is 100 ꢁ s per bit
Table 17. TIMING DELAY BETWEEN AUDIO MIC AND AUDIO L SWITCH ENABLE
0x0E MIC2L_EN_DELAY
Default = 00000000
Description
Bit
Name
Default
00000000
Type
7:0
MIC2L_EN_DELAY
R/W 00000000b: = 0 ꢁ s (DEFAULT)
00000001b: = 100 ꢁ s
……..
11111111b: = 25500 ꢁ s
Increment size is 100 us per bit
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FSA4485
Table 18. TIMING DELAY BETWEEN SENSE SWITCH AND AUDIO L SWITCH ENABLE
0x0F SENSE2L_EN_DELAY
Name Default
7:0 SENSE2L_EN_DELAY 00000000
Default = 00000000
Description
Bit
Type
R/W 00000000b: = 0 ꢁ s (DEFAULT)
00000001b: = 100 ꢁ s
……..
11111111b: = 25500 ꢁ s
Increment size is 100 ꢁ s per bit
Table 19. TIMING DELAY BETWEEN AGND SWITCH AND AUDIO L SWITCH ENABLE
0x10 AGND2L_EN_DELAY
Name Default
AGND2L_EN_DELAY 00000000
Default = 00000000
Description
Bit
Type
7:0
R/W 00000000b: = 0 ꢁ s (DEFAULT)
00000001b: = 100 ꢁ s
……..
11111111b: = 25500 ꢁ s
Increment size is 100 ꢁ s per bit
Table 20. AUDIO ACCESSORY STATUS
0x11 AUDIO_ACC_STAT
Default = 00000011
Description
Bit
Name
Default
Type
7:2
Reserved
000000
Read Reserved
0b: CC_IN < V_TH_L_CC
Read
1
0
CC_IN_STAT
DET_STAT
1
1
1b: CC_IN > V_TH_H_CC
0b: DET output is LOW
Read
1b: DET output is High−Z
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Table 21. AUTOMATIC FUNCTION ENABLE
0x12 FUNCTION_EN
Default = 11001000
Description
Bit
Name
Default
Type
R/W DET Output Configuration
7:6
DET_FUNCT
11
00b: Type−C Attach Detection, DET = LOW if CC_IN_STAT = 0b
01b: Audio Accessory Attach Detection, DET = LOW if NO_AUDIO_ACC = 0b
10b: Audio Accessory Detach Detection, DET = LOW if CC_IN_STAT transitions
from 0b to 1b
11b: Disabled, DET = High−Z (DEFAULT)
Resistor Detection Range Setting
0b: 1 kꢀ to 256 kꢀ
1b: 10 kꢀ to 2560 kꢀ
5
4
3
RES_DET_RANGE
HIZ_ACC_DET
0
0
1
R/W
R/W
R/W
High Impedance Audio Accessory Detection
0b: Automatic Hi−Z Accessory Detection is disabled
1b: Automatic Hi−Z Accessory Detection is enabled
Switch Slow Turn On Control Enable
0b: Disabled 1b: Enabled
SLOW_TURN_ON
0b: MIC Switch Auto Off Function is Disabled
1b: MIC Switch Auto Off Function is Enabled
2
1
MIC_AUTO_OFF
RES_DETECT
0
0
R/W
R/W
Resistance Detection Enabled
0b: Resistance Detection is Disabled
1b: Resistance Detection is Enabled
Automatically reset to 0b by I LOW RES = 1b
Audio Jack Detection and Configuration Enabled
0b: Audio Jack Detection is Disabled
0
AUDIO_JACK_DET
0
R/W
1b: Audio Jack Detection and Configuration is Enabled Automatically reset to 0b by
I AUDIO JACK DET = 1b
Table 22. RESISTOR DETECTION PIN SELECTION
0x13 RES_PIN_SEL
Default = 00000001
Description
Bit
7:3
2:0
Name
Default
00000
001
Type
Reserved
R/W Do Not Use
R/W 000b: Not Valid
RES_PIN_SEL
001b: DP_R (DEFAULT)
010b: DN_L
011b: SBU1
100b: SBU2
101b to 111b: Not Valid
RES PIN SEL must be set prior to setting RES DETECT to Enabled
Table 23. DETECTED RESISTOR VALUE
0x14 RES_VALUE
Default = 11111111
Description
Bit
Name
Default
Type
00000000b: R <= 1 kꢀ / 10 kꢀ
7:0
RES_VALUE
11111111
Read
11111111b: R >= 256 kꢀ / 2.56 Mꢀ
Increment = 10 kꢀ per bit if RES_DET_RANGE = 0b Increment = 1 kꢀ per bit if
RES DET RANGE = 1b
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Table 24. RESISTOR DETECTION THRESHOLD
0x15 RES_DET_THRESH
Default = 00010110
Description
Bit
Name
Default
Type
7:0
RES_DET_THRESH 00010110
R/W 00000000b: 1 kꢀ / 10 kꢀ
........
00010110b: 23 kꢀ / 230 kꢀ (DEFAULT)
........
11111111b: 256 kꢀ / 2560 kꢀ
Increment = 10 kꢀ per bit if RES_DET_RANGE = 0b Increment = 1 kꢀ per bit if
RES DET RANGE = 1b
Table 25. AUTOMATIC RESISTANCE DETECTION TIME INTERVAL
0x16 RES_DET_INTV
Default = 00000000
Description
Bit
7:2
1:0
Name
Default
000000
00
Type
Reserved
R/W Do Not Use
00b: One Time Detection
01b: Detection is performed every 100 ms
RES_DET_INTV
R/W
10b: Detection is performed every 1 s
11b: Detection is performed every 10 s
Table 26. AUDIO JACK STATUS
0x17 AUDIO_JACK_STAT
Default = 00000001
Description
Bit
Name
Default
Type
7:5
Reserved
000
0
Read Do Not Use
0b: OTHER
Read
4
3
2
1
0
UNKNOWN_AUDIO_ACC
4POLE_A
1b: Unknown Audio Accessory
0b: OTHER
0
0
0
1
Read
Read
Read
Read
1b: 4 Pole Audio, SBU2 to MIC, SBU1 to AGND
0b: OTHER
4POLE_B
1b: 4 Pole Audio, SBU1 to MIC, SBU2 to AGND
0b: OTHER
1b: 3 Pole Audio
3POLE
0b: Audio Accessory Attached
1b: No Audio Accessory
NO_AUDIO_ACC
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Table 27. RESISTANCE AND AUDIO JACK DETECTION INTERRUPT
0x18 DET_INTERRUPT
Default = 00000000
Description
Bit
7:5
4
Name
Default
000
Type
Reserved
I_DISABLE
R/CLR Do Not Use
A hardware disable has occurred due to EN = High
0b: The device has not been disabled
1b: The device was disabled
0
R/CLR
Audio Accessory Detach has occurred
3
I_DET_FUNCT
0
R/CLR
0b: DET_FUNCT = 00b, 01b, 11b, or DET_FUNCT = 10b and DET_STAT= 1b
1b: DET_FUNCT = 10b and DET_STAT = 0b
Clearing I DET FUNCT will return the DET output to High−Z
0b: Audio Jack Detection and Configuration has not occurred
1b: Audio Jack Detection and Configuration has occurred
2
1
0
I_AUDIO_JACK_DET
I_LOW_RES
0
0
0
R/CLR
R/CLR
R/CLR
0b: A Resistance < RES_DET_THRESH has not been detected
1b: A Resistance < RES DET THRESH has been detected
0b: Resistance Detection has not been completed
1b: Resistance Detection has been completed
I_RES_DET_COMP
Table 28. RESISTANCE AND AUDIO JACK DETECTION INTERRUPT MASK
0x19 DET_MASK
Name
Default = 00001000
Description
Bit
Default
Type
7:5
Reserved
000
R/W Do Not Use
0b: Do not mask Device Disable interrupt
1b: Mask Device Disable interrupt
4
3
2
1
0
M_DISABLE
M_DET_FUNCT
0
1
0
0
0
R/W
R/W
R/W
R/W
R/W
0b: Do not mask Audio Accessory Detach interrupt
1b: Mask Audio Accessory Detach interrupt
0b: Do not mask Audio Jack Detection and Configuration interrupt
1b: Mask Audio Jack Detection and Configuration interrupt
M_AUDIO_JACK_DET
M_LOW_RES
0b: Do not mask Low Resistance Detection interrupt
1b: Mask Low Resistance Detection interrupt
0b: Do not mask Resistance Detection completed interrupt
1b: Mask Resistance Detection completed interrupt
M_RES_DET_COMP
Table 29. AUDIO JACK MIC/AGND ORIENTATION DETECTION 1
0x1A AUDIO_JACK_DET1
Default = 00000000
Description
Bit
Name
Default
Type
Voltage from resistance between SBU1 and SBU2 (SBU2 = ground)
7:0
AUDIO_JACK_DET1
00000000
Read
00000000b: = 0 V
……..
11111111b: = 2.4 V
Increment is 9.375 mV per bit
Resistance is calculated as AUDIO_JACK_DET1 / CURR_SOURCE_SET
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Table 30. AUDIO JACK MIC/AGND ORIENTATION DETECTION 2
0x1B AUDIO_JACK_DET2
Default = 00000000
Description
Bit
Name
Default
Type
Voltage from resistance between SBU2 and SBU1 (SBU1 = ground)
7:0
AUDIO_JACK_DET2
00000000
Read
00000000b: = 0 V
……..
11111111b: = 2.4 V
Increment is 9.375 mV per bit
Resistance is calculated as AUDIO_JACK_DET2 / CURR_SOURCE_SET
Table 31. LOWER MIC DETECTION THRESHOLD VOLTAGE
0x1C MIC_DET_TH_LOW
Default = 00100000
Description
Bit
Name
Default
Type
00000000b: = 0 mV
7:0
MIC_DET_TH_LOW
00100000
R/W
……..
00100000b: = 300 mV (DEFAULT)
……..
11111111b: = 2.4 V
Increment = 9.375 mV per bit
Table 32. UPPER MIC DETECTION THRESHOLD VOLTAGE
0x1D MIC_DET_TH_UP
Default = 11111111
Description
Bit
Name
Default
Type
00000000b: = 0 mV
……..
7:0
MIC_DET_TH_UP
11111111
R/W
00100000b: = 300 mV
……..
11111111b: = 2.4 V (DEFAULT)
Increment = 9.375 mV per bit
Table 33. I2C REGISTER RESET
0x1E I2C_RESET
Default = 00000000
Description
Bit
Name
Default
Type
7:1
Reserved
0000000 W1CLR Do Not Use
0b: DEFAULT
0
I2C_RESET
0
W1CLR
2
1b: Reset all I C Register Values to Default
Table 34. RESISTANCE DETECTION CURRENT SOURCE
0x1F CURR_SOURCE_SET
Default = 00000010
Description
Bit
7:2
1:0
Name
Reserved
Default
000000
10
Type
Write Do Not Use
00b: 20 ꢁ A
CURR_SOURCE_SET
Write
01b: 100 ꢁ A
10b: 700 ꢁ A (DEFAULT)
11b: 1500 ꢁ A
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Table 35. DETECTION CURRENT STATUS
0x20 CURR_SOURCE_STAT
Default = 00000010
Description
Bit
7:2
1:0
Name
Reserved
Default
000000
10
Type
Read Do Not Use
00b: 20 ꢁ A
CURR_SOURCE_STAT
Read
01b: 100 ꢁ A
10b: 700 ꢁ A (DEFAULT)
11b: 1500 ꢁ A
Table 36. EXTERNAL GATE DRIVE OUTPUT CONTROL
0x21 GATE_DRIVE
Default = 00000000
Description
Bit
Name
Default
Type
7:3
Reserved
00000
R/W Do Not Use
0b: External Gate Drive GD1 and GD2 are Disabled (DEFAULT)
1b: External Gate Drive GD1 and GS2 are Enabled
2
GATE_DRIVE_EN
0
R/W
R/W
00b: 1 ꢁ A (DEFAULT)
01b: 1.5 ꢁ A
1:0
GATE_DRIVE_CURR
00
10b: 2 ꢁ A
11b: 3 ꢁ A
Table 37. OVER VOLTAGE AND OVER CURRENT PROTECTION ENABLE
0x22 PROTECTION_EN
Default =00000011
Description
Bit
Name
Default
Type
7:2
Reserved
000000
R/W Do Not Use
0b: Over Voltage Protection is Disabled
1
0
EN_OVP
EN_OCP
1
1
R/W
1b: Over Voltage Protection is Enabled (DEFAULT)
R/W 0b: Over Current Protection is Disabled
1b: Over Current Protection is Enabled (DEFAULT)
Table 38. OVER VOLTAGE AND OVER CURRENT PROTECTION STATUS
0x23 PROTECTION_STAT
Default = 00100000
Description
Bit
Name
Default
Type
7:6
Reserved
00
Read Do Not Use
0b: Over Voltage Protection on DP_R and DN_L is Disabled
1b: Over Voltage Protection on DP_R and DN_L is Enabled (DEFAULT)
5
4
3
2
1
USB_OVP
GSBU_OVP
SBU1_OVP
SBU2_OVP
OCP1
1
0
0
0
0
Read
Read
Read
Read
Read
0b: Over Voltage Protection on GSBUx is Disabled (DEFAULT)
1b: Over Voltage Protection on GSBUx is Enabled
0b: Over Voltage Protection on SBU1 is Disabled (DEFAULT)
1b: Over Voltage Protection on SBU1 is Enabled
0b: Over Voltage Protection on SBU2 is Disabled (DEFAULT)
1b: Over Voltage Protection on SBU2 is Enabled
0b: Over Current Protection from SBU1 to AGND is Disabled (DEFAULT)
1b: SBU1 STAT = 010b, Over Current Protection from SBU1 to AGND is
Enabled
0b: Over Current Protection from SBU2 to AGND is Disabled (DEFAULT)
1b: SBU2_STAT = 010b, Over Current Protection from SBU2 to AGND is
Enabled
0
OCP2
0
Read
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FSA4485
APPLICATION CIRCUIT
Application Circuit Diagram
Figure 20. Application Example with Factory Test Mode
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FSA4485
Figure 21. Application Example with Factory Test Mode
2
ON Semiconductor is licensed by the Philips Corporation to carry the I C bus protocol.
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FSA4485
PACKAGE DIMENSIONS
WLCSP25 2.16x2.16x0.574
CASE 567YL
ISSUE O
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