FSA634UCX [ONSEMI]
2:1 MIPI D-PHY (1.5Gbps) 4 Data Lane Switch;
| 型号： | FSA634UCX |
| 厂家： | 
ONSEMI |
| 描述： | 2:1 MIPI D-PHY (1.5Gbps) 4 Data Lane Switch |
| 文件： | 总9页 (文件大小：1035K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2:1 MIPI D-PHY (1.5ꢀGbps)
4ꢀData Lane Switch
FSA634
Description
The FSA634 is configured as a 4 data lane, MIPI D−PHY switch.
This single pole double throw (SPDT) switch is optimized for
switching between two high speed or low power MIPI sources. The
FSA634 is designed for the MIPI specification and allows connection
to a CSI or DSI module.
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Features
• Switch Type: SPDT (10x)
• Signal Type: MIPI, D−PHY
(Bottom View)
• V : 1.65 to 4.5 V
CC
WLCSP36,
2.06x2.06x0.432
CASE 567XU
• Input Signal: 0 V to V
CC
• R
:
ON
♦ 5 W Typical HS MIPI
♦ 5 W Typical LP MIPI
MARKING DIAGRAM
• DR : 0.1 W Typical
ON
• R
: 0.06 W Typical
ON_FLAT
VJKK
XYZ
• I : 0.5 mA Maximum
CCZ
• I : 32 mA Maximum
CC
• O : −30 dB Typical
IRR
VJ
KK
X
Y
Z
= Specific Device Code
= Assembly Lot
= Year
= Work Week
= Assembly Location
• Bandwidth: 1.9 GHz Typical
• Xtalk: −38 dB Typical
• C : 4.3 pF Typical
ON
• Skew: 3 ps Typical
Applications
ORDERING INFORMATION
See detailed ordering and shipping information on page 7 of
this data sheet.
• Cellular Phones, Smart Phones
• Tablets
• Laptops
• Displays
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
September, 2019 − Rev. 1
FSA634/D
FSA634
Figure 1. Typical Application
PIN DESCRIPTIONS
Figure 2. Analog Symbol
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2
FSA634
PIN DEFINITIONS
Figure 3. Top Through View
Table 1. BALL−TO−PIN MAPPINGS
Ball
A1
A2
A3
A4
A5
A6
B1
B2
B3
B4
B5
B6
Pin Name
GND
Ball
C1
C2
C3
C4
C5
C6
D1
D2
D3
D4
D5
D6
Pin Name
D3A
D4A
D3
Ball
E1
E2
E3
E4
E5
E6
F1
F2
F3
F4
F5
F6
Pin Name
D7A
D8A
D7
GND
/OE
SEL
D4
D8
V
CC
D3B
D4B
D5A
D6A
D5
D7B
D8B
D9A
D10A
D9
GND
D1A
D2A
D1
D2
D6
D10
D1B
D2B
D5B
D6B
D9B
D10B
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3
FSA634
Figure 4. Suggested Configuration for 4 Lane D−PHY
TRUTH TABLE
SEL
LOW
HIGH
X
/OE
Function
LOW
LOW
HIGH
Dn = DnA
Dn = DnB
All Ports High Impedance
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
−0.5
−0.5
−0.3
−50
Max
Unit
V
V
CC
Supply Voltage
5.25
V
DC Input Voltage (/OE, SEL)
DC Switch I/O Voltage
DC Input Diode Current
DC Output Current
(Note 1)
V
CC
V
CC
V
CNTRL
V
I
(Note 1,2)
V
SW
mA
mA
°C
kV
IK
I
50
+150
OUT
T
STG
Storage Temperature
−65
3.5
1.5
ESD
Human Body Model, JEDEC: JESD22−A114
Charged Device Model, JEDEC: JESD22−C101
All Pins
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The input and output negative ratings may be exceeded if the input and output diode current ratings are observed.
2. V
refers to analog data switch paths.
SW
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4
FSA634
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
1.65
0
Max
Unit
V
V
CC
Supply Voltage
4.50
V
Control Input Voltage (SEL, /OE)
(Note 3)
V
CC
V
CNTRL
V
SW
Switch I/O Voltage
(Dn, DAn, DBn)
HS Mode
LP Mode
0
0.425
1.3
V
0
V
T
A
Operating Temperature
−40
+85
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
3. The control inputs must be held HIGH or LOW; they must not float.
ELECTRICAL SPECIFICATION TABLE Typical values are at T = 25°C, V = 3.3 V unless otherwise specified.
A
CC
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DC ELECTRICAL PARAMETERS
V
V
Clamp Diode Voltage
Input Voltage High
Input Voltage Low
I
= −18 mA, V = 1.8 V
−1.2
V
V
IK
IH
IN
CC
V
V
V
= 1.65 V to 4.50 V
= 1.65 V to 4.50 V
1.0
CC
CC
SW
V
0.4
V
IL
I
IN
Control Input Leakage
(SEL,/OE)
= 0 V to V , V = 1.65 V to 4.50 V
−500
−500
500
nA
CC
CC
IN
, IN
O(OFF)
Off Leakage Current of
Port Dn, DnA, DnB
Dn = 0.3 V to V − 0.3 V; DnA or DnB =
Floating, 0.3 V, or V − 0.3 V; /OE = 0 V;
V
500
500
nA
nA
C(OFF)
CC
CC
= 1.65 V to 4.5 V
CC
I
On Leakage Current of
Common Ports (Dn)
Dn = 0.3 V to V − 0.3 V; DnA or DnB =
Floating, 0.3 V, or V − 0.3 V; /OE = 0 V;
−500
A(ON)
CC
CC
V
CC
= 1.65 V to 4.5 V
I
Power−Off Leakage
Current
Dn, DnA or DnB; V = 0 V to 4.5 V;
−500
−500
500
500
12
9
nA
nA
W
OFF
IN
V
CC
= 0 V
IOZ
Off−State Leakage
0 ≤ Dn, DnA, DnB ≤ 3.6 V, /OE = High,
= 4.5 V
V
CC
R
R
R
R
Switch On Resistance for I = −10 mA, /OE = 0 V, SEL = V or 0 V,
HS MIPI Applications
(Note 5)
5
5
5
5
5
5
5
5
ON_MIPI_HS_1p8
ON_MIPI_HS_2p5
ON_MIPI_HS_3p6
ON_MIPI_HS_4p5
ON
CC
DnA or DnB = 0.1 V, 0.2 V, 0.3 V, V = 1.8 V
CC
I
= −10 mA, /OE = 0 V, SEL = V or 0 V,
CC
W
ON
DnA or DnB = 0.1 V, 0.2 V, 0.3 V, V = 2.5 V
CC
I
= −10 mA, /OE = 0 V, SEL = V or 0 V,
CC
9
W
ON
DnA or DnB = 0.1 V, 0.2 V, 0.3 V, V = 3.6 V
CC
I
= −10 mA, /OE = 0 V, SEL = V or 0 V,
CC
9
W
ON
DnA or DnB = 0.1 V, 0.2 V, 0.3 V, V = 4.5 V
CC
R
R
R
R
Switch On Resistance for I = −10 mA, /OE = 0 V, SEL = V or 0 V,
LP MIPI Applications
(Note 5)
12
9
W
ON_MIPI_LP_1p8
ON_MIPI_LP_2p5
ON_MIPI_LP_3p6
ON_MIPI_LP_4p5
ON
CC
DnA or DnB = 0 V, 0.6 V, 1.2 V, V = 1.8 V
CC
I
= −10 mA, /OE = 0 V, SEL = V or 0 V,
W
ON
CC
DnA or DnB = 0 V, 0.6 V, 1.2 V, V = 2.5 V
CC
I
= −10 mA, /OE = 0 V, SEL = V or 0 V,
9
W
ON
CC
DnA or DnB = 0 V, 0.6 V, 1.2 V, V = 3.6 V
CC
I
= −10 mA, /OE = 0 V, SEL = V or 0 V,
9
W
ON
CC
DnA or DnB = 0 V, 0.6 V, 1.2 V V = 4.5 V
CC
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5
FSA634
ELECTRICAL SPECIFICATION TABLE Typical values are at T = 25°C, V = 3.3 V unless otherwise specified.
A
CC
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DC ELECTRICAL PARAMETERS
On Resistance Matching
Between HS MIPI Chan- DnA or DnB = 0.1 V, 0.2 V, 0.3 V, V = 1.8 V
nels
I
= −10 mA, /OE = 0 V, SEL = V or 0 V,
DR
DR
DR
DR
DR
DR
DR
DR
0.10
0.10
0.10
0.10
0.12
0.12
0.12
0.12
0.04
0.06
0.06
0.06
0.18
0.28
0.28
0.28
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
mA
ON CC
ON_MIPI_HS_1p8
ON_MIPI_HS_2p5
ON_MIPI_HS_3p6
ON_MIPI_HS_4p5
ON_MIPI_LP_1p8
ON_MIPI_LP_2p5
ON_MIPI_LP_3p6
ON_MIPI_LP_4p5
CC
I
= −10 mA, /OE = 0 V, SEL = V or 0 V,
CC
ON
DnA or DnB = 0.1 V, 0.2 V, 0.3 V, V = 2.5 V
CC
I
= −10 mA, /OE = 0 V, SEL = V or 0 V,
CC
ON
DnA or DnB = 0.1 V, 0.2 V, 0.3 V, V = 3.6 V
CC
I
= −10 mA, /OE = 0 V, SEL = V or 0 V,
CC
ON
DnA or DnB = 0.1 V, 0.2 V, 0.3 V, V = 4.5 V
CC
On Resistance Matching
Between LP MIPI Chan- DnA or DnB = 0.0 V, 0.6 V, 1.2 V, V = 1.8 V
nels
I
= −10 mA, /OE = 0 V, SEL = V or 0 V,
ON CC
CC
I
= −10 mA, /OE = 0 V, SEL = V or 0 V,
CC
ON
DnA or DnB = 0.0 V, 0.6 V, 1.2 V, V = 2.5 V
CC
I
= −10 mA, /OE = 0 V, SEL = V or 0 V,
CC
ON
DnA or DnB = 0.0 V, 0.6 V, 1.2 V, V = 3.6 V
CC
I
= −10 mA, /OE = 0 V, SEL = V or 0 V,
CC
ON
DnA or DnB = 0.0 V, 0.6 V, 1.2 V, V = 4.5 V
CC
On Resistance Flatness
for HS MIPI Signals
I
= −10 mA, /OE = 0 V, SEL = V or 0 V,
R
R
R
R
ON CC
ON_FLAT_MIPI_HS_1p8
ON_FLAT_MIPI_HS_2p5
ON_FLAT_MIPI_HS_3p6
ON_FLAT_MIPI_HS_4p5
DnA or DnB = 0.1 V, 0.2 V, 0.3 V, V = 1.8 V
CC
I
= −10 mA, /OE = 0 V, SEL = V or 0 V,
CC
ON
DnA or DnB = 0.1 V, 0.2 V, 0.3 V, V = 2.5 V
CC
I
= −10 mA, /OE = 0 V, SEL = V or 0 V,
CC
ON
DnA or DnB = 0.1 V, 0.2 V, 0.3 V, V = 3.6 V
CC
I
= −10 mA, /OE = 0 V, SEL = V or 0 V,
CC
ON
DnA or DnB = 0.1 V, 0.2 V, 0.3 V, V = 4.5 V
CC
On Resistance Flatness
for LP MIPI Signals
I
= −10 mA, /OE = 0 V, SEL = V or 0 V,
R
R
R
R
ON CC
ON_FLAT_MIPI_LP_1p8
ON_FLAT_MIPI_LP_2p5
ON_FLAT_MIPI_LP_3p6
ON_FLAT_MIPI_LP_4p5
DnA or DnB = 0.0 V, 0.6 V, 1.2 V, V = 1.8 V
CC
I
= −10 mA, /OE = 0 V, SEL = V or 0 V,
CC
ON
DnA or DnB = 0.0 V, 0.6 V, 1.2 V, V = 2.5 V
CC
I
= −10 mA, /OE = 0 V, SEL = V or 0 V,
CC
ON
DnA or DnB = 0.0 V, 0.6 V, 1.2 V, V = 3.6 V
CC
I
= −10 mA, /OE = 0 V, SEL = V or 0 V,
CC
ON
DnA or DnB = 0.0 V, 0.6 V, 1.2 V, V = 4.5 V
CC
I
Quiescent Hi−Z Supply
Current
V
= 0 V or V , I
= 0 A, V = 4.5 V
0.5
CCZ
IN
CC OUT
CC
I
Quiescent Supply Current V = 0 or V , I
= 0 A, V = 2.5 V to 4.5 V
16
15
32
25
4
mA
mA
mA
mA
CC
IN
CC OUT
CC
I
V
V
V
= 0 or V , I
= 0 A, V = 1.8 V
CC_1p8
IN
CC OUT CC
I
Increase in I Current
Per Control Voltage and
= 1.65 V, /OE = 1.65 V, V = 4.5 V
CCT_4p5
CCT_2p5
CC
SEL
CC
I
= 1.65 V, /OE = 1.65 V, V = 2.5 V
0.1
V
CC
SEL
CC
AC ELECTRICAL PARAMETERS
t
R = 50 W, C = 5 pF, V
= 1.2 V, V = 2.5 V
100
ms
Initalization Time V to
INIT
L
L
SW
CC
CC
Output
to 4.5 V
t
R = 50 W, C = 5 pF, V
= 1.2 V, V = 1.8 V
150
200
ms
INIT_1p8
L
L
SW
CC
t
Enable Turn−On Time,
/OE to Output
R = 50 W, C = 5 pF, V
= 1.2 V, V = 2.5 V
120
ns
EN
L
L
SW
CC
to 4.5 V
t
R = 50 W, C = 5 pF, V
= 1.2 V, V = 1.8 V
250
25
500
50
ns
ns
EN_1p8
L
L
SW
CC
t
Disable Turn−Off Time,
/OE to Output
R = 50 W, C = 5 pF, V
= 1.2 V, V = 2.5 V
CC
DIS
L
L
SW
to 4.5 V
t
R = 50 W, C = 5 pF, V
= 1.2 V, V = 1.8 V
50
90
ns
DIS_1p8
L
L
SW
CC
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6
FSA634
ELECTRICAL SPECIFICATION TABLE Typical values are at T = 25°C, V = 3.3 V unless otherwise specified.
A
CC
Symbol
Parameter
Conditions
Min
Typ
Max
Units
AC ELECTRICAL PARAMETERS
t
Turn−On Time, SEL to
Output
R = 50 W, C = 5 pF, V
to 4.5 V, SEL = H to L, SEL = L to H
= 1.2 V, V = 2.5 V
200
300
200
300
ns
ns
ns
ON
L
L
SW
CC
t
R = 50 W, C = 5 pF, V = 1.2 V, V = 1.8 V,
ON_1p8
L
L
SW
CC
SEL = H to L, SEL = L to H
R = 50 W, C = 5 pF, V = 1.2 V, V = 2.5 V
SW CC
t
Turn−Off Time SEL to
Output
OFF
L
L
to 4.5 V, SEL = H to L, SEL = L to H
t
R = 50 W, C = 5 pF, V = 1.2 V, V = 1.8 V,
OFF_1p8
L
L
SW
CC
SEL = H to L, SEL = L to H
t
Break−Before−Make
Time
R = 50 W, C = 5 pF, V
1.65 V to 4.5 V
= 1.2 V, V =
CC
10
50
−30
−38
1.9
3
ns
dB
BBM
L
L
SW
OIRR
XTALK
BW
Off Isolation for MIPI
(Note 5)
R = 50 W, f = 750 MHz, /OE = V , V
=
SW
L
CC
−1 dBm (200 mV ), V = 1.65 V to 4.5 V
PP
CC
Crosstalk for MIPI
(Note 5)
R = 50 W, f = 750 MHz, V
= −1 dBm
dB
L
SW
(200 mV ), V = 1.65 V to 4.5 V
PP
CC
Bandwidth at −3dB
(Note 5)
R = 50 W, C = 0 pF, V = 3 V
GHz
ps
L
L
CC
SW
SW
t
Channel−to−Channel Sin- TDR−Based Method (V
gle−Ended Skew (Note 5) C ), V = 3.3 V
= 0.2 V , C =
20
20
SK(O)
PP
L
ON
CC
t
Skew of Opposite Transi- TDR−Based Method (V
= 0.2 V , C =
3
ps
SK(P)
PP
L
tions of the Same Output
(Note 5)
C
), V = 3.3 V
ON
CC
CAPACITANCE
C
Control Pin Input Capaci-
tance (Note 5)
V
CC
V
CC
V
CC
= 0 V, f = 1 MHz
2.7
4.3
1.9
pF
pF
pF
IN
C
Out On Capacitance
(Note 5)
= 3.3 V, /OE = 0 V, f = 1 MHz
and /OE = 3.3 V, f = 1 MHz
ON
C
Out Off Capacitance
(Note 5)
OFF
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Guarantee Levels:
4. Guaranteed by Design. Characterized on the ATE or Bench.
5. Guaranteed by Design and Characterization, not Production Tested.
The table below pertains to the Packaging information on the following page.
ORDERING INFORMATION
Part Number
Operating Temperature Range
Package
Top Mark
FSA634UCX
−40 to +85°C
36−Ball WLCSP, Non−JEDEC
2.06 x 2.06 mm, 0.35 mm Pitch
VJ
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7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WLCSP36 2.06x2.06x0.432
CASE 567XU
ISSUE O
DATE 26 APR 2019
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON06820H
WLCSP36 2.06x2.06x0.432
PAGE 1 OF 1
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相关型号：
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