FSA8049UCX [ONSEMI]
音频插孔检测和配置，MIC / GND 交点开关;
| 型号： | FSA8049UCX |
| 厂家： | 
ONSEMI |
| 描述： | 音频插孔检测和配置，MIC / GND 交点开关 开关 |
| 文件： | 总10页 (文件大小：1460K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA
Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended
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August 2012
FSA8049
Audio Jack Detection and Configuration, MIC / GND
Cross Point Switch
Features
Description
Detection
VDD
Audio Plug GND & MIC Polarity
2.5 to 4.4 V
The FSA8049 is an audio jack detection switch for 3- or
4-pole accessories. The FSA8049 detects the locations of
ground (GND) and microphone (MIC) poles on the audio
plug and automatically routes them to the appropriate
connections. This allows the end user to plug accessories,
such as headsets with different audio pole configurations,
into the mobile device and have them operate correctly.
THD (MIC)
0.002% Typical
ESD (IEC 61000-4-2)
(Air Gap)
15 kV
Operating Temperature
-40°C to 85°C
.
.
.
Detects 3- or 4-pole audio accessories
9-Ball WLCSP 3x3 Array, 0.4 mm
Terminal Pitch, 250 µm Ball
Package
Detects polarity of GND and MIC on 4-pole plugs
Automatically routes GND and MIC to audio jack terminals
Top Mark
M3
Ordering Information
FSA8049UCX
Related Resources
. For evaluation boards and questions, please contact:
Applications
Analog.Switch@fairchildsemi.com.
.
.
Cellular Phones, Smart Phones
MP3 and Portable Multimedia Player
Typical Application
To Audio Plug
Detection Circuit
VDD
Baseband
Processor
Audio Jack
GPIO
EN
Oscillator &
Logic
Detection
LSPKR
RSPKR
CEXT
Audio
Sub System
Switch Enable
Timing
3Pole
4Pole
MIC Bias
GND/MIC1
RMIC
MIC
MIC
GND/MIC2
CMIC
5Ω
tOn/Off
Capacitor
100mΩ
GND
GNDA
Figure 1. Mobile Phone Example
© 2011 Fairchild Semiconductor Corporation
FSA8049 • Rev. 1.0.2
www.fairchildsemi.com
Pin Configuration
1
2
3
3
2
1
GND/
MIC1
GND/
MIC1
VDD
VDD
GNDA
GNDA
A
A
GND/
MIC2
GND/
MIC2
MIC
EN
MIC
EN
GNDA
CEXT
GNDA
CEXT
B
C
B
C
M3 KK
X Y Z
GND
GND
Pin Assignments , Top Through View
Top Mark Side
Pin Assignments Bottom View
Bump Side
3
GND/
MIC1
2
GNDA
1
VDD
M3 = FSA8049UCX Product Identifier
KK = Lot Run Trace Code
A
GND/
MIC2
GNDA
MIC
B
X
Y
Z
●
=
=
=
=
Year
Work Week
GND
EN
CEXT
C
Assembly Site (P= Penang, Malaysia)
Pin 1 Indicator
Top View
Bottom View
Figure 2. Pin Assignments
Figure 3. Top Mark
Pin Descriptions
Name
VDD
Ball
A1
A2
A3
B1
B2
B3
Type
Description
Power Supply voltage
GNDA
GND
I/O
Switch Ground(1)
GND/MIC1
MIC
Switch connects to audio jack
I/O
Switch connects to audio subsystem microphone pre-amplifier
Switch Ground(1)
GNDA
GND
I/O
GND/MIC2
Switch connects to audio jack
0
1
Disabled
Enabled
EN
C1
Input
Enable (0=VIL, 1=VIH)
CEXT
GND
C2
C3
Input
GND
External capacitor for switch slow tON/OFF timing
Device Ground(1)
Note:
1. GND and GNDA can be shorted together if the system does not utilize an FM antenna on the handset ground. If the
system utilizes an FM antenna on the handset ground; separate GND and GNDA, place the FM-decoupling inductor and
capacitor on GNDA only, and connect GND to a low-impedance path to battery ground.
States of Pins after Audio Jack Detection
State of pins GND/MIC1, GND/MIC2, and MIC after detection time (tDET) is complete.
GND/MIC1
0 (GND)
GND/MIC2
Switch Configuration
Accessory Connected
0 (GND)
GND/MIC1=GND, GND/MIC2=GND, MIC=GND 3-Pole Headphones
0 (GND)
1 (MIC Attached) GND/MIC1=GND, GND/MIC2=MIC
4-Pole Headset with Microphone
4-Pole Headset with Microphone
1 (MIC Attached)
0 (GND)
GND/MIC1=MIC, GND/MIC2=GND
© 2011 Fairchild Semiconductor Corporation
FSA8049 • Rev. 1.0.2
www.fairchildsemi.com
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable
above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition,
extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute
maximum ratings are stress ratings only.
Symbol
Parameter
Min.
-0.5
-0.5
-50
Max.
6.0
Unit
V
v
VSW
IIK
Supply Voltage from Battery
Switch I/O Voltage
VCC+0.5
V
Input Clamp Diode Current
Switch I/O Current (Continuous)(2)
Storage Temperature Range
Maximum Junction Temperature
mA
mA
°C
°C
°C
ISW
TSTG
TJ
50
-65
+150
+150
+260
TL
Lead Temperature (Soldering, 10 Seconds)
Air Gap
15
8
IEC 61000-4-2 System ESD
Contact
GND/MICn vs. GND
VDD vs. GND
All Pins
11
16
7
ESD
kV
Human Body Model, JEDEC JESD22-A114
Charged Device Model, JEDEC JESD22-C101 All Pins
1.5
Note:
2. The input and output negative ratings may be exceeded if the input and output diode current ratings are observed.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating
conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend
exceeding them or designing to Absolute Maximum Ratings.
Symbol
VDD
Parameter
Min.
2.5
0
Max.
4.4
Unit
V
Supply Voltage
VEN
Enable Input Voltage
Operating Temperature
VDD
V
TA
-40
+85
ºC
© 2011 Fairchild Semiconductor Corporation
FSA8049 • Rev. 1.0.2
www.fairchildsemi.com
3
DC Electrical Characteristics
All typical values are at TA=25°C unless otherwise specified.
TA=-40 to +85°C
Symbol
Parameter
VDD (V)
Condition
Unit
Min.
Typ.
Max.
MIC Switch (MIC to (GND/MIC1 or GND/MIC2))
2.8
3.8
2.8
3.00
2.50
0.25
5.00
4.00
0.50
RON(MIC) MIC Switch On Resistance
IOUT=24 mA, VIN=1.8 V
Ω
Ω
RFLAT(ON) On Resistance Flatness
IOUT=24 mA, VIN=1 V to VDD
3.8
0.20
0.40
VDD
VIN(MIC) Switch Input Voltage Range
CON(MIC) MIC Switch On Capacitance(3)
COFF(MIC) MIC Switch Off Capacitance(3)
2.7 to 4.4
3.8
0
0
V
f=1 MHz
f=1 MHz
90
21
pF
pF
3.8
GND Switch (GND to (GND/MIC1 or GND/MIC2))
2.8
3.8
90
80
170
100
1
RON(GNDA) GND Switch On Resistance
IOUT=24 mA
mΩ
V
VIN(GNDA) Switch Input Voltage Range
XC(GNDA) GND Switch On Reactance(4)
Parallel I/O
2.7 to 4.4
f=88 MHz to 108 MHz,
VIN=50 mV
3.8
100
mΩ
VIH
VIL
Input High Voltage
Input Low Voltage
2.7 to 4.4
2.7 to 4.4
1.1
0
VDD
V
V
0.55
Increase in Quiescent Supply
Current
ICCT
Current
IOZ
4.4
EN=1.3 V
3
µA
GND/MICn=1 V, 4.3 V;
MIC=4.3V, 1V; EN=LOW
Switch Leakage Current
4.4
-75
75
nA
IIN
Input Leakage Current
Disabled Current
0 to 4.4 EN Input 0 to 4.3 V
2.7 to 4.4 EN=0
0.1
µA
nA
nA
ICC-DIS
ICC-EN
100
100
Enabled Current After Detection
2.7 to 4.4 EN=1
EN=0→1, 3-Pole Mode,
2.7 to 4.4
ICC-DET
Current During Detection Mode
0.5
2.0
mA
GND/MIC1=GND/MIC2
Notes:
3. Guaranteed by characterization.
4. Guaranteed by design.
© 2011 Fairchild Semiconductor Corporation
FSA8049 • Rev. 1.0.2
www.fairchildsemi.com
4
AC Electrical Characteristics
All typical values are at TA=25°C unless otherwise specified.
TA = -40 to +85°C
Symbol
Parameter
VDD (V)
Condition
Unit
Min.
Typ.
Max.
MIC Switch
RT=600 Ω, VSW=0.5 VPP
f=20 Hz to 20 kHz,
VIN=1.8 V and 2.2 V
(Figure 4)
,
THD
OIRR
Total Harmonic Distortion(5)
3.8
0.002
%
f=20 kHz, RS=32 Ω,
CL=0 pF, RT=32 Ω
(Figure 5)
-108
-85
Off Isolation(5)
3.8
dB
f=20 KHz, RS=600 Ω,
CL=0 pF, RT=600 Ω
(Figure 5)
Parallel I/O
CEXT=Float
RL=10 kΩ, CL=10 pF
200
140
20
µs
ms
µs
Switch Turn-On Time (MIC & GND
Switch), Measure 10/90
tON-GNDA
3.8
3.8
CEXT=0.1 µF
RL=10 kΩ, CL=10 pF
CEXT=Float
RL=10 kΩ, CL=10 pF
Switch Turn-Off Time (MIC & GND
Switch), Measure 10/90
tOFF-GNDA
CEXT=0.1 µF
RL=10 kΩ, CL=1 0pF
6
ms
ns
Switch Turn-Off Time (MIC
Switch), Measure 10/90
tOFF-MIC
3.8
RL=10 kΩ, CL=10 pF
100
tON-DET
Detection Circuit NMOS On time
2.7 to 4.4
20
20
µs
µs
tOFF-DET
Detection Circuit NMOS OFF time 2.7 to 4.4
Detection Time of Audio Jack
tDET
2.7 to 4.4 EN=1
50
15
ms
µs
GND and MIC Terminals(6)
Enable / Disable Time
tEN
2.7 to 4.4 EN=01, EN=10
Power
Power Supply Noise
300mVPP, Measured
10/90%, f=217 Hz Square
Wave
PSRR
Power Supply Rejection Ratio(5)
3.8
-89
dB
Notes:
5. Guaranteed by characterization.
6. Detection time may be longer if there is noise in the system or a poor audio jack connection.
© 2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA8049 • Rev. 1.0.2
5
Typical Performance Characteristics
Figure 4.
THD Test Setup
Figure 5.
Off Isolation
© 2011 Fairchild Semiconductor Corporation
FSA8049 • Rev. 1.0.2
www.fairchildsemi.com
6
Physical Dimensions
F
0.03 C
2X
A
E
0.40
A1
B
D
Ø0.20
Cu Pad
0.40
PIN A1
INDEX AREA
Ø0.30
Solder Mask
0.03 C
2X
LAND PATTERN RECOMMENDATION
(NSMD PAD TYPE)
TOP VIEW
0.06 C
0.378±0.018
0.208±0.021
0.625
0.547
0.05 C
E
C
SEATING PLANE
D
SIDE VIEWS
NOTES:
A. NO JEDEC REGISTRATION APPLIES.
B. DIMENSIONS ARE IN MILLIMETERS.
Ø0.260±0.020
9X
0.40
C. DIMENSIONS AND TOLERANCE
PER ASMEY14.5M, 1994.
C
B
A
D. DATUM C IS DEFINED BY THE SPHERICAL
CROWNS OF THE BALLS.
(Y)±0.018
0.40
E. PACKAGE NOMINAL HEIGHT IS 586 MICRONS
±39 MICRONS (547-625 MICRONS).
F
1
2 3
(X)±0.018
F. FOR DIMENSIONS D, E, X, AND Y SEE
PRODUCT DATASHEET.
BOTTOM VIEW
G. DRAWING FILNAME: MKT-UC009ABrev2
Figure 6. 9-Ball, Wafer-Level Chip-Scale Package (WLCSP), 3x3 Array, 0.4 mm Pitch, 250 µm Ball
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without
notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most
recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which
covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Ordering Information
Operating
Part
Top
Mark
Temperature
Range
Package
D
E
X
Y
Number
9-Ball, Wafer-Level Chip-Scale Package
FSA8049UCX -40 to +85°C
M3 (WLCSP), 3x3 Array, 0.4 mm Pitch,
250 µm Ball
1.16 mm 1.16 mm 0.018 mm 0.018 mm
© 2011 Fairchild Semiconductor Corporation
FSA8049 • Rev. 1.0.2
www.fairchildsemi.com
7
© 2011 Fairchild Semiconductor Corporation
FSA8049 • Rev. 1.0.2
www.fairchildsemi.com
8
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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