FSA805UMX [ONSEMI]

配件开关;
FSA805UMX
型号: FSA805UMX
厂家: ONSEMI    ONSEMI
描述:

配件开关

开关 光电二极管
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July 2013  
FSA805 — USB2.0 High-Speed (480Mbps), UART, and  
Audio Switch with Negative Signal Capability  
Features  
Description  
The FSA805 is a 3:1 USB accessory switch that enables  
USB data, stereo/mono audio, and UART data to share  
a common connector port. It is designed for high-speed  
USB 2.0 signaling. The architecture is designed to allow  
audio signals to swing below ground (to -0.8V) so a  
common USB and headphone jack can be used for  
personal media players and portable peripheral devices.  
.
.
.
.
.
.
3:1 Switch Handles:  
Audio Headsets  
UART  
Up to 2 High-Full and Low-Speed USB Data  
Negative-Swing-Capable Audio Channel  
The FSA805 meets both USB Rev. 2.0 and micro-USB  
specifications.  
Built-in Termination Resistors for Audio Pop  
Reduction  
.
Simple Switch Control Using Two Select Pins  
Applications  
.
Cell Phones, MP3 Players, PDAs  
Ordering Information  
Operating  
Temperature Range  
Part Number  
Top Mark  
Package  
Eco Status  
FSA805UMX  
-40 to +85°C  
JZ  
Green  
12-Lead Quad, UMLP, 1.8x1.8mm  
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.  
VCC  
FSA805  
R_HOST  
L_HOST  
R
3:1  
RxD_HOST  
MUX  
TxD_HOST  
and  
DP_CON  
Charge  
Pump  
DM_CON  
DP_HOST  
DM_HOST  
GND  
SEL[0]  
Switch  
SEL[1]  
Control  
Figure 1. Functional Block Diagram  
© 2009 Fairchild Semiconductor Corporation  
FSA805 • Rev. 1.0.0  
www.fairchildsemi.com  
Application Diagram  
Baseband  
Processor  
VCC FSA805  
Micro  
USB  
L_HOST  
Audio  
Codec  
R_HOST  
R
3:1  
MUX  
and  
VBUS  
TxD_HOST  
RxD_HOST  
UART or  
HSUSB  
DM_CON  
Charge  
Pump  
DP_CON  
DM_HOST  
DP_HOST  
ID  
UART or  
HSUSB  
GND  
SEL[0]  
SEL[1]  
Switch  
Control  
Figure 2. Typical Application  
© 2009 Fairchild Semiconductor Corporation  
FSA805 • Rev. 1.0.0  
www.fairchildsemi.com  
2
Functional Description  
The FSA805 USB2.0 accessory switch is designed to  
consolidate wired accessories for portable devices, such  
as cellular telephones and portable audio players. The  
benefits of consolidation include reduced space  
requirements from a reduction of connectors and their  
size. The micro-USB connector, for example, reduces  
connector height and depth, allowing for slimmer overall  
designs. Using the USB industry standard and a  
common connector type for devices such as chargers  
and headsets, greatly reduces the waste associated with  
new phone purchases by allowing re-use of the devices.  
Applications with Multiple USB Controllers  
The FSA805 UART port (RxD_HOST, TxD_HOST) can  
be used as a High-speed USB interface. This allows it to  
operate in an application with two USB controllers (one  
full speed, and the other full or high speed).  
In this configuration, it is recommended to configure the  
switches to OPEN before switching to the other (second)  
USB interface. The OPEN setting duration should be  
long enough for the accessory to go to a SE0 state, so  
when the switch is set to the other (second) USB port,  
the new controller re-enumerates.  
Using just five wires for all connection types  
considerably reduces the cost of wired accessories and  
simplifies their construction. The FSA805 facilitates  
adopting this methodology because it is designed to  
redirect the DP/DM pins from the USB connector to one  
of three ports at the baseband’s discretion.  
Mode Descriptions  
The FSA805 has two select pins to control the switching  
operations, SEL[0], and SEL[1]. Table 1 describes mode  
operation.  
Table 1. Selection Truth Table  
SEL[1] SEL[0]  
Switch Action  
Description  
0
0
OPEN  
Open all switch paths (device in low-power mode)(1)  
Closes USB/UART1 path to D+/D-, default condition(2)  
- DP_CON connected to RxD_HOST  
- DM_CON connected to TxD_HOST  
0
1
USB, UART  
USB, UART  
AUDIO  
Closes USB/UART2 path to D+/D-  
- DP_CON connected to DP_HOST  
- DM_CON connected to DM_HOST  
1
0
1
Closes audio path to D+/D- only  
- DP_CON connected to R_HOST  
- DM_CON connected to L_HOST  
1
Notes:  
1. When the audio switch is in the OPEN position (Table 1, line1), the R and L are terminated to GND with internal  
termination resistors to discharge any stray capacitance that could cause audio pop.  
2. The SELECT pins are CMOS inputs and should not be left in a floating condition. Some applications require the  
UART path be in the CLOSED position on power-up for initial programming of the device under test. If that  
condition is desired, the two SELECT pins should be pulled to the correct levels with external resistors that  
should exceed 100Kto reduce the static power consumption. In other applications, adding weak pull-down  
resistors to GND defaults the device to all paths open (low-power mode).  
© 2009 Fairchild Semiconductor Corporation  
FSA805 • Rev. 1.0.0  
www.fairchildsemi.com  
3
Pin Configuration  
12 11 10  
1
9
SEL[0]  
VCC  
L_HOST  
R_HOST  
8
2
7
3
4
5
6
Figure 3. 12-Pin, UMLP Pin Assignments (Top-Through View)  
Pin Descriptions  
Name  
Pin #  
Description  
USB Interface  
D+ signal, dedicated USB port to be connected to the resident USB transceiver on the phone.  
Can also be used for UART signaling.  
DP_HOST  
DM_HOST  
3
4
D- signal, dedicated USB port to be connected to the resident USB transceiver on the phone.  
Can also be used for UART signaling.  
Audio Interface  
R_HOST  
7
8
Right audio channel from phone audio-out codec  
Left audio channel from phone audio-out codec  
L_HOST  
UART Interface  
5
6
Tx connection from resident UART transceiver on the phone. Can also be used for HS USB  
signaling.  
TxD_HOST  
RxD_HOST  
Rx connection from resident UART transceiver on the phone. Can also be used for HS USB  
signaling.  
Power Interface  
VCC  
2
Input voltage supply pin to be connected to the phone battery output  
Connector Interface  
GND  
9
Ground  
11  
Connected to the USB connector D+ pin; depending on the signaling mode, this pin can share  
D+, R, Rxd, or MIC signals  
DP_CON  
10  
Connected to the USB connector D- pin; depending on the signaling mode, this pin can share  
D-, L, or Txd signals  
DM_CON  
Switch Control  
SEL[1:0]  
1,12 Switch selection pins; refer to Table 1 for truth table  
© 2009 Fairchild Semiconductor Corporation  
FSA805 • Rev. 1.0.0  
www.fairchildsemi.com  
4
Absolute Maximum Ratings  
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be  
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.  
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.  
The absolute maximum ratings are stress ratings only.  
Symbol  
Parameter  
Supply Voltage from Battery / Baseband  
USB  
Min.  
-0.5  
-1.0  
-1.5  
-0.5  
-50  
Max.  
6.0  
Unit  
VCC  
V
V
CC +0.5  
VSW  
Switch I/O Voltage  
Stereo/Mono Audio Path Active  
VCC +0.5  
VCC +0.5  
V
All Other Channels  
IIK  
Input Clamp Diode Current  
Switch I/O Current (Continuous)  
mA  
mA  
USB  
50  
60  
ISW  
Audio  
All Other Channels  
USB  
50  
150  
150  
150  
+150  
+150  
+260  
13.0  
8.0  
mA  
mA  
mA  
Peak Switch Current (Pulsed at 1ms  
Duration, <10% Duty Cycle)  
Audio  
ISWPEAK  
All Other Channels  
TSTG  
TJ  
Storage Temperature Range  
-65  
C  
C  
C  
Maximum Junction Temperature  
TL  
Lead Temperature (Soldering, 10 Seconds)  
Air Gap  
Contact  
All Pins  
All Pins  
USB Connector Pins  
(D+, D-)  
IEC 61000-4-2 System  
ESD  
kV  
JEDEC JESD22-A114, Human Body Model  
JEDEC JESD22-C101, Charged Device Model  
4.5  
1.5  
Recommended Operating Conditions  
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended  
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not  
recommend exceeding them or designing to Absolute Maximum Ratings.  
Symbol  
Parameter  
Min.  
2.7  
0
Max.  
4.4  
Units  
VCC  
Battery Supply Voltage  
Switch I/O Voltage  
V
V
USB Path Active  
Audio Path Active  
UART Active  
3.6  
VSW  
-0.8  
0
0.8  
V
4.4  
V
TA  
Operating Temperature  
-40  
+85  
ºC  
© 2009 Fairchild Semiconductor Corporation  
FSA805 • Rev. 1.0.0  
www.fairchildsemi.com  
5
Switch Path DC Electrical Characteristics  
All typical values are at TA=25ºC unless otherwise specified.  
TA = -40 to +85°C  
Min. Typ. Max.  
Symbol  
Parameter  
VCC (V)  
Conditions  
Unit  
Host Interface Pins (SEL[1:0])  
VIH  
VIL  
Input High Voltage  
Input Low Voltage  
3.2 to 4.4  
3.2 to 4.4  
1.3  
V
V
0.7  
Switch Off Characteristics  
All Ports Except Audio Path  
VSW=0V to 4.4V,  
Figure 9  
IOFF  
Power Off Leakage Current  
0
10  
µA  
USB Switch On Path  
USB Analog Signal Range  
3.2 to 4.4  
3.2 to 4.4  
0
3.6  
9
V
VD+/D-=0V, 0.4V, ION=8mA,  
Figure 8  
RONUSB HS Switch On Resistance(3)  
6
Audio R/L Switch On Paths  
Audio Analog Signal Range  
3.2 to 4.4  
-0.8  
0.8  
3
V
RONAUD Audio Switch On Resistance(3) 3.2 to 4.4  
V
L/R=-0.8V, 0.8V, ION=30mA,  
Audio RON Flatness(4)  
3.2 to 4.4  
0.1  
1
Figure 8  
RFLAT  
Internal Termination  
Resistors(5)  
RTERM  
k  
UART Switch On Path  
Analog Signal Range  
3.2 to 4.4 VSW=0V, 4.4V, ION=8mA  
0
VCC  
V
VTxD/RxD=0V, 3.2V, ION=8mA,  
RONUART Switch On Resistance(3)  
Total Switch Current Consumption  
3.2 to 4.4  
Figure 8  
25  
Battery Supply Sleep Mode  
Average Current  
Static Current During Sleep  
3.2 to 4.4  
ICCSL  
10  
80  
15  
µA  
µA  
Mode (SEL[1:0]=0)  
Battery Supply Active Mode  
Average Current  
Average Pulse Current  
3.2 to 4.4  
ICCWK  
110  
(~100µs Pulse)  
VSEL = 2.8V and VCC = 4.4V  
3.2 to 4.4  
8
µA  
µA  
Increase in ICCSL/ICCWK Current  
ICCSELT  
per Control Voltage and VCC  
VSEL = 1.8V and VCC = 4.4V  
10  
Notes:  
3. On resistance is determined by the voltage drop between the both sides of the switch at the indicated current through  
the switch.  
4. Flatness is defined as the difference between the maximum and minimum values of on resistance over the  
specified range of conditions.  
5. Guaranteed by characterization; not production tested.  
© 2009 Fairchild Semiconductor Corporation  
FSA805 • Rev. 1.0.0  
www.fairchildsemi.com  
6
Switch Path AC Electrical Characteristics(6)  
All typical value are for VCC =3.8V at TA=25ºC unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Typical Unit Figure  
Audio Mode  
4
1.0nF, VS=0V,  
RS=0Ω  
Q
Charge Injection  
UART Mode  
USB Mode  
4
6
pC Figure 13  
f=20kHz, RT=32,  
CL=0pF  
Audio Mode  
-95  
-75  
Active Channel Crosstalk  
DP_CON to DM_CON  
UART Mode  
USB Mode  
f=1MHz, RT=50,  
CL=0pF  
Xtalk  
dB Figure 12  
MIC on VBUS to  
R_HOST, L_HOST  
Active Channel Crosstalk  
MIC  
f=20kHz, RT=32,  
CL=0pF  
-105  
-100  
MIC on DP_CON to  
L_HOST (DM_CON)  
Audio Path  
L_HOST to DM_CON,  
R_HOST to DP_CON  
f=20kHz, RT=32,  
CL=0pF  
USB Path  
OIRR  
Off Isolation Rejection Ratio  
dB Figure 11  
DM_HOST to  
DM_CON, DP_HOST  
to DP_CON  
-80  
-85  
f=1 MHz, RT=50,  
CL=0pF  
UART Path  
TxD_HOST to  
DM_CON, RxD_HOST  
to DP_CON  
20Hz to 20kHz,  
RL=16, Input  
Signal Range 1.6VPP  
0.037  
0.025  
%
%
Figure 16  
Figure 16  
THD+N Total Harmonic Distortion + Noise (Audio Path)  
20Hz to 20kHz,  
RL=32, Input  
Signal Range 1.6VPP  
RL=50, CL=50pF,  
tr=tf=500ps (10-90%)  
at 480Mbps  
tJ  
Total Jitter (USB Mode)  
130  
ps  
(PRBS=215–1)  
RL=50, CL=0pF  
RL=50, CL=5pF  
1150  
550  
MHz Figure 10  
MHz Figure 10  
BW  
-3db Bandwidth (USB Mode DPHost/DMHost)  
Note:  
6. Guaranteed by characterization; not production tested.  
© 2009 Fairchild Semiconductor Corporation  
www.fairchildsemi.com  
FSA805 • Rev. 1.0.0  
7
Capacitance  
TA = -40 to +85°C  
Min. Typ. Max.  
2.0  
Symbol  
Parameter  
VCC (V)  
Conditions  
Unit  
Figure  
CIN  
Select Pins Capacitance(7)  
0
VBIAS=0.2V  
BIAS=0.2V, f=1MHz  
pF  
pF  
Figure 14  
Figure 15  
D+, D- On Capacitance  
(HS USB Mode)(7)  
CON(D+, D-)  
3.8  
V
6.5  
Note:  
7. Guaranteed by characterization; not production tested.  
High Speed USB Eye Compliance Results for All FSA805 Signal Paths  
The following figures show high-speed USB 2.0 eye diagrams for each path of the FSA805. Full compliance reports  
are available upon request. Figure 4 shows the eye diagram of the high-speed USB source used for testing of the  
FSA800 and FSA805 paths.  
Figure 4. High-Speed Eye Diagram for Source  
Used for All Testing  
Figure 5. USB (DP_HOST/DM_HOST) Path  
High-Speed Eye Diagram  
Figure 6. UART (TxD_HOST/RxD_HOST) High-Speed  
Eye Diagram  
Figure 7. Audio Path High-Speed Eye Diagram  
© 2009 Fairchild Semiconductor Corporation  
FSA805 • Rev. 1.0.0  
www.fairchildsemi.com  
8
Test Diagrams  
VON  
IA(OFF)  
NC  
A
nB  
n
nA  
V
IN  
V
IN  
Select  
ION  
GND  
GND  
Select  
GND  
V
= 0 orV  
cc  
Sel  
V
= 0 or V  
cc  
Sel  
**Each switch port is tested separately.  
RON = VON / ION  
Figure 8. On Resistance  
Figure 9. Off Leakage  
Network Analyzer  
Network Analyzer  
R
S
R
S
V
IN  
V
GND  
V
S
GND  
S
R
T
GND  
GND  
V
V
GND  
Sel  
Sel  
V
OUT  
V
OUT  
GND  
GND  
GND  
GND  
R
R
T
T
RS and RT are functions of the application  
environment (see AC/DC tables).  
RL and CL are functions of the application  
environment (see AC/DC tables).  
GND  
GND  
Off-Isolation = 20 Log (VOUT / VIN  
)
L
CL includes test fixture and stray capacitance.  
Figure 10. Bandwidth  
Figure 11. Channel Off Isolation  
Network Analyzer  
NC  
R
S
V
IN  
VS1, S2, S3  
V
GND  
S
GND  
R
T
GND  
GND  
V
OUT  
R
T
GND  
GND  
RS and RT are functions of the application  
environment (see AC tables for values).  
CROSSTALK = 20 Log (VOUT/ VIN  
)
Figure 12. Adjacent Channel Crosstalk  
© 2009 Fairchild Semiconductor Corporation  
FSA805 • Rev. 1.0.0  
www.fairchildsemi.com  
9
Test Diagrams (Continued)  
Generator  
B
VCC  
Input – VSEL  
VIN  
RS  
Off  
On  
Off  
mA  
VS  
0V  
VOUT  
CL  
GND  
GND  
nSn  
VOUT  
VOUT  
V
SEL  
CL includes test fixture and stray capacitance  
Q = VOUT • C  
L
GND  
Figure 13. Charge Injection Test  
nB  
n
nB  
Capacitance  
Meter  
n
nS  
n
nS  
n
Capacitance  
Meter  
VSel = 0 or Vcc  
V
Sel= 0 orVcc  
f = 1MHz  
nB  
f = 1MHz  
n
nB  
n
Figure 14. Channel Off Capacitance  
Figure 15. Channel On Capacitance  
Audio Analyzer  
R
S
V
IN  
V
S
GND  
GND  
VCNTRL  
V
OUT  
GND  
GND  
R
T
VSel = 0 or Vcc  
GND  
RS and RT are functions of the application  
environment (see AC Tables for specific values).  
Figure 16. Total Harmonic Distortion  
© 2009 Fairchild Semiconductor Corporation  
FSA805 • Rev. 1.0.0  
www.fairchildsemi.com  
10  
Physical Dimensions  
0.10 C  
1.80  
A
2.55  
2X  
12X  
0.75  
B
1
2.55  
1.80  
PIN #1 QUADRANT  
0.40  
0.10 C  
12X  
0.20  
2X  
TOP VIEW  
RECOMMENDED LAND PATTERN  
ALL DIMENSIONS REFERENCE  
0.55 MAX.  
0.10 C  
0.152  
C
SEATING  
PLANE  
0.08 C  
0.05  
0.00  
SIDE VIEW  
3
6
0.40  
0.425 TYP  
0.100  
11X  
0.45  
0.35  
1
0.100  
12  
9
0.44  
0.40  
0.100  
0.10 C A B  
0.05 C  
0.22  
0.18  
10X  
DETAIL A  
PIN #1 TERMINAL  
SCALE: 2X  
BOTTOM VIEW  
A. DIMENSIONS ARE IN MILLIMETERS.  
B. DIMENSIONS AND TOLERANCES PER  
ASME Y14.5M, 1994  
C. LANDPATTERN PER IPC LANDPATTERN CALCULATOR V 2009.18.00  
D. DRAWING FILENAME: MKT-UMLP12A REVISION2  
Figure 17. 12-Lead Quad, UMLP, 1.8x1.8mm  
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner  
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or  
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the  
warranty therein, which covers Fairchild products.  
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:  
http://www.fairchildsemi.com/packaging/.  
© 2009 Fairchild Semiconductor Corporation  
FSA805 • Rev. 1.0.0  
www.fairchildsemi.com  
11  
© 2009 Fairchild Semiconductor Corporation  
FSA805 • Rev. 1.0.0  
www.fairchildsemi.com  
12  
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