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September 2014

FSA9285 — MCPC-Compliant, USB-Port, Multimedia Switch

with Auto-Detection

Features

Description

The FSA9285 is

a high-performance multimedia switch

Switch Type

Audio, FS/HS-USB, Charging

featuring automatic switching and accessory detection for a

USB port. The FSA9285 allows sharing of a common USB port

to pass audio and USB data while simultaneously charging.

Programmable Switching with

Available Interrupt

Switch Mechanism

Headsets with MIC and Send/End

USB Data Cable

USB Chargers (Car, CDP, DCP)

USB On-The-Go (OTG)

In addition, the FSA9285 integrates detection of accessories

such as headphones, headsets Mobile Computing Promotion

Consortium (MCPC) with MIC and Send/End, car chargers,

USB chargers, USB On-The-Go (OTG), and Accessory

Charging Adapters (ACA) to use a common USB connector.

The FSA9285 can be programmed for manual or automatic

switching of USB data paths based on the accessory detected.

With an integrated 28 V over-voltage and 1.45 A over-current

protected FET, the FSA9285 integrates common USB

Accessory Detection

MCPC Specification Compliant

Programmable Modes

USB

FS and HS 2.0 Compliant

Battery Charging 1.2 Compliant

Integrated FET, Charger Detect,

OCP (1.45 A), OVP (6.5 V - 28.0 V)

USB Charging

protection functions for V_BUS

.

Left, Right, MIC (Negative Swing)

Built-in Termination Resistors for

Audio Pop Reduction

Audio

Applications

.

Mobile Phones, Portable Media Players

V_BAT

2.7 to 4.4 V

I²C

Programmability

ESD

15 kV IEC 61000-4-2 Air Gap

20-Lead, WLCSP (2.010 x 1.672 x

0.625 mm, 0.4 mm Pitch)

Package

Ordering Information

FSA9285UCX

Figure 1.

Typical Application

www.fairchildsemi.com

FSA9285 • Rev 1.0.3

Block Diagram

V

BAT

Phone

Power

FSA9285

V

BUS_OUT

Charger

IC

CHG_DETB

MIC

USB Port

V

BUS_IN

Audio

Codec

Audio_R

Audio_L

V_{BUS_IN}

Detection

OCP, OVP

3:1

MUX

and

Charge

Pump

DM_CON

DP_CON

DP_HOST2

DM_HOST2

DM_CON

DP_CON

HS-USB

DP_HOST1

DM_HOST1

ID_CON

GND

ID_CON

GND

Charger

Detect

INTB

I2C_SCL

I2C_SDA

Interrupt

I2C

Baseband

Switch

Control

and

Processor

Float / Short

Detect

V

DDIO

I2C

Slave

Resistance

Detection

Figure 2.

Block Diagram

Pin Configuration

1

2

3

4

GND

DP_HOST2

DM_HOST2

VBAT

A

B

C

D

E

MIC

I2C_SDA

I2C_SCL

AUDIO_L

DM_CON

VDDIO

GND1

INTB

CHG_DETB

AUDIO_R

DP_CON

DM_HOST1

DP_HOST1

VBUS_OUT

VBUS_IN

ID_CON

Figure 3.

Pin Assignments (Top-Through View)

www.fairchildsemi.com

FSA9285 • Rev 1.0.3

2

Pin Descriptions

Default

State

Name

Pin #

Type

Description

USB Interface

DP_HOST1

D+ signal switch path, dedicated USB port to be connected to the

resident USB transceiver on the phone

D1

C1

A2

A3

E4

D4

C2

Signal Path

Power Path

Open

N/A

D- signal switch path, dedicated USB port to be connected to the

resident USB transceiver on the phone

DM_HOST1

DP_HOST2

DM_HOST2

V_{BUS_IN}

D+ signal switch path, dedicated USB port to be connected to the

resident USB transceiver on the phone

D- signal switch path, dedicated USB port to be connected to the

resident USB transceiver on the phone

Input voltage supply pin to be connected to the V_BUSpin of the USB

connector

Output voltage supply pin to be connected to the source voltage pin on

the charger IC

V_{BUS_OUT}

N/A

Open-Drain

Output

Open-drain active LOW output, used to signal the charger IC that a

charger has been attached

CHG_DETB

Hi-Z

Audio Interface

Audio_R

D2

D3

Signal Path

Open

Right audio channel switch path from mobile phone audio CODEC

Left audio channel switch path from mobile phone audio CODEC

Audio_L

Connected to the mobile phone audio CODEC MIC input pin to

complete the MIC switch path

MIC

B2

Signal Path

Open

Connector Interface

Connected to the USB connector ID pin and used for detecting

accessories or button presses

ID_CON

E1

Signal Path

Open

Connected to the USB connector D+ pin; depending on the signaling

mode, can be switched to DP_HOST1, DP_HOST2, or Audio_R pins

DP_CON

E2

E3

Connected to the USB connector D- pin; depending on the signaling

mode, can switched to DM_HOST1, DM_HOST2, or Audio_L pins

DM_CON

Power Interface

V_BAT

Input voltage supply pin to be connected to the mobile phone battery

output or to an internal regulator on the phone

A4

Power Path

N/A

V_DDIO

GND1

B4

B1

A1

Power Path

Ground

N/A

Baseband processor interface I/O supply pin

Ground

GND

Ground

I²C Interface

I2C_SCL

I2C_SDA

I²C serial clock signal to be connected to the phone-based I²C master

I²C serial data signal to be connected to the phone-based I²C master

C3

B3

Input

Hi-Z

Open-Drain I/O

Interrupt active LOW output used to prompt the phone baseband

processor to read the I²C register bits, indicates a change in ID_CON or

V_{BUS_IN}pin status or accessories’ attach status

INTB

C4

CMOS Output

LOW

www.fairchildsemi.com

FSA9285 • Rev 1.0.3

3

1. Functional Description

The FSA9285 is a USB port accessory-detection switch with

integrated 28 V over-voltage and 1.45 A over-current protected

FET. Fully controlled using I²C protocols, the FSA9285 enables

all of the following to use a common connector (micro / mini

USB 2.0 port): high-speed USB 2.0 standard downstream data

port, stereo and mono audio headphones / headsets with or

without a microphone, wired remote controller with optional

send / end button, USB Charging Downstream Port (CDP)

battery charger, USB Dedicated Charging Port (DCP) charger,

and ANSI/CEA-936-A USB Car Kit charger.

Detection of USB accessories utilizing a USB micro-B or micro-

A/B connector is made possible by the presence of a standard

resistor between the ID pin and ground of the accessory.

Advanced modes manage wired remote-control sensing for

audio accessories. The FSA9285 is designed to allow audio

signals to swing below ground on the USB 2.0 port data lines.

Internal power for the FSA9285 is automatically derived from

either the battery voltage (V_BAT) or the USB supply (V_{BUS_IN}) for

simplicity and long battery life.

2. I²C and Digital Core

The FSA9285 enables factory-mode testing by defaulting to

manual mode (EN_MAN_SW = 1) and defaulting the MANUAL

SW register to USB switches DP_HOST1 / DM_HOST1 closed

and the V_BUSFET closed. In manual configuration, USB

switches DP_HOST1 / DM_HOST1 only close when an

accessory is attached that has an ID_CON resistance (ID_CON

not floating) and / or valid V_BUSvoltage is present. The V_BUS

FET only closes when V_BUSis valid. All switches remain open to

protect the system when there is no accessory attached. This

default switch condition can be overridden with I²C commands.

The FSA9285 includes a full I²C slave controller. The I²C slave

fully complies with version 2.1 of the I²C specifications. This

block is designed for fast-mode, 400 kHz signals. The slave

addresses are shown in Table 1. This block also includes the

chip master controller. The chip controller monitors commands

sent to the FSA9285 via I²C from the baseband processor and

takes action. The digital core takes inputs from the various

functional blocks and the I²C commands received from the

mobile phone baseband processor and relays relevant status

updates to the phone.

Table 1. I²C Slave Address

Name

Size (Bits)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Slave Address

8

0

1

0

1

0

1

Read / Write

Examples of I²C write and read sequences are shown in Figure 4 and Figure 5, respectively.

8bits 8bits 8bits

S Slave Address WR A Register Address K A Write Data A Write Data K+1 A Write Data K+2 A Write Data K+N-1 A P

Note: Single byte read is initiated by master with P immediately following first data byte.

Figure 4.

I²C Write Sequence

8bits

S

Slave Address WR A Register Address K

Register address to read specified

A S Slave Address RD A Read Data K A Read Data K+1 A Read Data K+N-1 NA P

Single- or multi byte read executed from current register location (single-byte read is

initiated by master with NA immediately following first data byte)

Note: If register is not specified, master begins reading from current register. In this case, only red bracketed sequence is needed.

Figure 5.

I²C Read Sequence

From Master to Slave

From Slave to Master

S

A

Start Condition

Acknowledge (SDA Low)

NA NOT Acknowledge (SDA High)

WR Write=0

RD

P

Read =1

Stop Condition

www.fairchildsemi.com

FSA9285 • Rev 1.0.3

4

3. Power-Up Initialization and Reset

FSA9285 operates correctly without special power sequencing.

When power is first applied, the device undergoes a hardware

reset and all the registers are initialized to the default values

shown in Table 6. All of the combinations of valid V_BUS

V_BATare shown in Table 2.

When the device is reset, all I²C registers are initialized to the

default values shown in Table 6 (see Section 4 - Configuration).

After reset or power up, the FSA9285 enters Standby Mode

and is ready to detect accessories sensed on its V_{BUS_IN}or

ID_CON pins.

_

and

IN

As shown in Table 2, V_BATis used as the primary power supply.

V_DDIOis the dedicated baseband IO voltage and is only used for

I²C interface and interrupt processing within the FSA9285.

The device has three hardware reset mechanisms:

.

Power-on reset caused by the initial rising edge of V_BUS

(if V_BAT< 1.0 V) or rising edge of V_BAT(If not V_{BUS_VALID}

)

When V_BATis not valid, but V_{BUS_IN}is; the FSA9285 powers off

V_{BUS_IN}. In this condition, the FSA9285 operates in its default

state and is able to detect USB accessories and all chargers.

The FSA9285 always turns on the V_BUSFET upon any attach

state with V_{BUS_Valid}(unless Manual Mode is enabled with the

V_BUSFET switch state configured open). This allows charging

of a dead battery when the rest of the system is not powered to

configure the FSA9285.

.

The falling edge of V_DDIO

I²C reset: holding I2C_SDA and I2C_SCL LOW for 30ms

The device has one software reset mechanism:

.

Writing the ResetB bit (bit 6) in the Control register (02h)

Table 2. Power States Summary

Enabled Functionality

Valid

V_{BUS_IN}

Valid

(1)

V_DDIO

Valid V_BAT

Power State

Charging

through FET

Processor Communication

Detection

(I²C & Interrupts)

NO

YES⁽²⁾

NO

Power Down

NO

ILLEGAL STATE

NO

YES

Powered Off V_BAT

NO

YES

Powered Off

V_{BUS_IN}

YES

NO

YES

NO

Yes

YES

NO

YES

Powered Off V_BAT

Powered Off

V_{BUS_IN}

YES⁽²⁾

YES

Powered Off V_BAT

Notes:

1. V_DDIOis expected to be the same supply used by the baseband I/Os.

2. This is not a typical state. Both V_BATand V_DDIOare typically provided from the same regulator.

4. Configuration

The FSA9285 must be configured for operation upon reset.

There are several options to note about reset configuration:

4. To enable manual configuration of the USB switches, the

EN_MAN_SW bit must be set to 1. The switch settings

then override any automatic settings (this assumes that the

USB discovery state machine has completed its operations

and a device is attached). For the weak (or dead) battery

case to work reliably, V_DDIOmust be removed (to reset the

FSA9285 state) whenever the battery is too low for reliable

I²C communication.

5. Performing a software reset sets all I²C Register Map

(Table 6) registers to default, with the exception of the

Control register, Manual SW register, and the Manual

CHG_CTRL register. These registers are only reset to

default on a hardware reset.

1. The Interrupt Mask bit is set and must be cleared for the

FSA9285 to interrupt the host processor.

2. Upon hardware reset, the USB Path DP_HOST1

/

DM_HOST1 switches are configured to close when an

accessory is attached (with an ID_CON resistance or valid

V_BUSvoltage) to support production programming. These

switches may be opened using I²C commands.

3. If MIC Mode is going to be used, it is recommended that

MIC_OVP_EN bit be set to 1 at reset.

www.fairchildsemi.com

FSA9285 • Rev 1.0.3

5

power-up before interrupts can be signaled by the FSA9285.

Individual Interrupt Masks bits can be enabled by writing the

Interrupt Mask register (see Table 6).

5. Interrupt Operation

The baseband processor recognizes interrupt signals by

observing the INTB signal, which is active LOW. Interrupts are

masked upon reset via the INT Mask register bit (bit 0 of

Control register, address 02h in Table 6 of the I²C register map)

and INTB pin defaults HIGH. After the INT Mask bit is cleared

by the baseband processor, the INTB pin is generally driven

HIGH (INTB is not an open-drain output) in preparation for a

future interrupt. The INTB remains HIGH until the INTB mask is

cleared. If the Interrupt Mask bit in the I²C Control register is

written LOW when an interruptible event occurs, INTB

transitions LOW and returns HIGH when the processor reads

the Interrupt register at addresses 03h.

ID_CON resistor detection is accomplished in a little more than

three times the “Resistor Detection Time,” where Resistor

Detection Time bits are programmable in the Timing Set

register. The FSA9285 is designed to allow up to 1nF

capacitance on the ID_CON pin. ID_CON is short-circuit

protected from a faulty resistor or an accidental short where the

current is limited to 5mA sourced by the FSA9285.

The detection of a V_{BUS_IN}goes through the USB detection flow

only once. V_{BUS_IN}must be removed before the USB detection

state machine reverts to its initial state.

After an initial attach, the FSA9285 continuously monitors the

ID pin for changes and reports those changes to the baseband

processor. To provide the fastest response for changes in

button checking after initial attach, the FSA9285 indicates a

change in ID_CON resistor after two samples are taken instead

of the three consecutive samples taken on initial attach. To

save power, the resistor detection block can be disabled after

an initial attach with the ID_DIS bit in the Control register. The

resistor detection block is normally disabled when no ID_CON

resistance is present (ID_CON floating) to save power. The

condition of ID_FLOAT continues to be monitored regardless of

the ID_DIS setting.

6. Analog Switch Descriptions

The FSA9285 has a three-port data switch, providing routing

capability to two data ports and one audio port. The two data

switches are high bandwidth to provide high-speed USB 2.0

“eye” compliance. These switches also operate full-swing for

full-speed USB and UART signals up to 4.4 V.

The high-performance negative-swing-capable audio switch

utilizes a termination resistor for audio pop reduction. The audio

configuration also provides for routing a microphone signal from

a headset. The MIC signals can be routed to either the V_{BUS_IN}

pin for stereo audio configurations or the DP_CON pin for mono

audio configurations that also allow simultaneous charging over

the V_BUSline.

Whenever a resistance is measured on ID_CON, the USB

discovery state machine halts after completion of its current

state and the ID_CON state machine continues for accessory

detection. The only exception is when an ACA RID-A accessory

is detected. In this case, the USB discovery state machine is

used to differentiate between a docking station and a powered

A-device attached to a docking station (per USB Battery

Charging Specification 1.2).

7. Accessory Detection

In Standby Mode, after power-up or reset, the FSA9285

monitors the V_{BUS_IN}and ID_CON pins for any connectivity

using very low power (see “Battery Supply Standby Mode

Current” in the Switch Path DC Electrical Characteristics

section). To minimize standby power, many functional blocks

are powered down until an accessory attach is detected. The

V_{BUS_IN}detection recognizes if the voltage on V_{BUS_IN}is within

the valid range (>4.0 V). For resistance to GND on the ID_CON

pin, the FSA9285 measures voltage with an injected current to

determine this resistance. All accessories attached or detached

are reported to the processor via the Interrupt register. Any

changes of resistance on the ID_CON pin are reported as a

Resistor_Change interrupt. Additional information about the

accessory is reported in the Device Type, Resistor Code, and

Status registers. For USB accessories without an ID_CON

resistance, a V_{BUS_Valid}Change interrupt is reported to signal an

attach or detach condition. Status of V_{BUS_Valid}and ID_CON

resistance is always available after any interrupt.

If the EN_MAN_SW bit is set on attach, FSA9285 configures

the switches to the state in the MANUAL SW register.

Upon the removal of any accessory, the FSA9285 detects and

indicates a change in ID_CON resistance (regardless of ID_DIS

bit setting), a removal of V_{BUS_IN}, or both. The FSA9285

automatically opens all switches (and V_BUSFET) on detach

(ID_FLOAT and V_BUSnot valid), even if the FSA9285 is set to

Manual Switching Mode.

For the weak battery case, the FSA9285 needs to be in

Automatic Switching Mode. Should the processor NOT be able

to respond to INTB, FSA9285 must be placed in Automatic

Switching Mode explicitly or V_DDIOmust be removed, resetting

the FSA9285 state to its default values.

Note: If the FSA9285 is to be used in automatic switching

mode (EN_MAN_SW = 0) then the Manual SW register must

be configured for all switches OPEN).

The USB detection flow is show in Figure 6. Note that the INTB

Mask bit in the Control register must be cleared after a reset or

www.fairchildsemi.com

FSA9285 • Rev 1.0.3

6

V_BUSand ID Detection State

Machines Operate in Parallel

Check V_BUS

Check ID

No

Yes

V_BUSValid?

ID Float?

No

Yes

Perform DCD

ADC Change

ID=RID_A?

No

Yes

Charger?

No

Yes

ID=200k/442k

Car Kit1/2

ID=ACA RID-B

ACA_B

ID=ACA RID-C

ACA_C





ACA_A

Dock

Other

Charger?

Yes

DP/DM

Shorted?

No

Yes

DCP

CDP

SDP

Figure 6.

Accessory Discovery State Machine Flow Diagram

Note:

3. Figure 6 illustrates operation with a valid V_DDIOsupply voltage. Figure 6 does not illustrate Dead Battery Provision (DBP) See

Section 9 for details.

www.fairchildsemi.com

FSA9285 • Rev 1.0.3

7

Table 3. ID_CON Resistor Identification

ID_CON Resistance to GND

Resistor

Code⁽⁴⁾

Auto Switch

USB Switches

Unit

Accessory Detected

Min.

Typ.

Max.

22

20

19

18

17

16

15

14

13

12

11

10

9

0

18

Ω

OTG

Resistor 20 kΩ

19000

22800

27265

34675

39798

44650

55638

64600

80275

96900

117800

148500

171000

198000

229680

272650

370500

437580

529150

757150

970000

20000

24000

21000

25200

30135

36865

40602

49350

56762

71400

88725

107100

130200

151500

183600

202000

234320

301350

401700

446420

584850

836850

Open

Resistor 24 kΩ

28700

Resistor 28.7 kΩ

ACA RID-C⁽⁵⁾

36500

YES

40200

Resistor 40.2 kΩ

MCPC Send/End

Resistor 56.2 kΩ

ACA RID-B⁽⁵⁾

47000

56200

68000

YES

84500

Resistor 84.5 kΩ

Phone Power Device

ACA RID-A⁽⁵⁾

102000

124000

150000

180000

200000

232000

287000

390000

442000

557000

797000

Resistor 150 kΩ

MCPC Maintenance

Car Kit Type-1 Charger⁽⁵⁾

Resistor 232 kΩ

MCPC Mode 1

8

7

6

5

4

MCPC Reserved

Car Kit Type-2 Charger⁽⁵⁾

MCPC Mode 3

3

2

1

MCPC Mode 2

0

Float⁽⁶⁾

Notes:

4. The resistor code values are reported in the Resistor Code register whenever a valid resistor code value changes.

5. See Table 4 for details, additional requirements may be applicable for detection.

6. Resistance 970 kΩ status bit /ID_FLOAT=0.

www.fairchildsemi.com

FSA9285 • Rev 1.0.3

8

8. USB Port and Charger Detection

The FSA9285 can detect the USB 2.0 port types summarized in

Table 4. V_BUSmust be present to detect these accessories.

For USB chargers that do not automatically close USB

switches, the switches can be closed manually through the

Manual Switch register when EN_MAN_SW is enabled.

For SDP, CDP, and ACA USB accessories; the following pin

mapping is automatically configured:

Whenever V_{BUS_IN}becomes valid, the integrated 28 V charger

FET is closed (unless EN_MAN_SW

= 1 and Manual

.

DP_HOST1 = DP_CON (If EN_MAN_SW = 0)

DM_HOST1 = DM_CON (If EN_MAN_SW = 0)

V_{BUS_OUT}= V_{BUS_IN}

SW[1:0]≠11) and V_{BUS_IN}voltage is continuously monitored to

incorporate Over-Voltage Protection (OVP). If the attached

device is recognized as one of the chargers in Table 4

(excluding SDP), the CHG_DETB pin goes LOW to send a

signal to the charger IC, external to the FSA9285, to increase

the charging current to the maximum allowed level by the Over-

Current Protection (OCP) trigger (see the Switch Path DC

Electrical Characteristics section). V_{BUS_OUT}must be valid 10ms

before sourcing greater than 100 mA.

The FSA9285 allows factory testing or programming through

the DP_HOST1 and DM_HOST1 switches by closing these

switches when a USB cable with an ID resistance or V_BUS

voltage is detected.

Table 4. ID_CON and V_BUSDetection for USB and Car Kit Devices

ID_CON Resistance

Resistor

USB

to GND (kΩ)

V_{BUS_IN}

CHG_DETB⁽⁸⁾

Accessory Detected

Code⁽⁷⁾

Switches⁽⁸⁾

Min.

198

Typ.

200

Max.

00111

00011

5V

Open

Asserted

202

Car Kit Type-1 Charger

437.58

442.00

446.42 Car Kit Type-2 Charger

USB Dedicated Charging Port, Travel

00000

5V

Open

Asserted

3 MΩ

Open

Adapter or Dedicated Charger (DCP)⁽⁹⁾

USB Charging Downstream Port (CDP)⁽⁹⁾

USB Standard Downstream Port (SDP)⁽⁹⁾

00000

5V

Auto_close

Asserted

Not Asserted

Asserted

3 MΩ

34.675

64.6

Open

36.500

68.0

Open

10001

36.865 ACA RID-C

01101

Asserted

71.4

ACA RID-B

ACA RID-A

01010

Asserted

117.8

124.0

130.2

Notes:

7. The resistor code values are reported in the Resistor Code register, independent of the state of USB switches or V_{BUS_IN}

8. In Table 4, switches auto-close and CHG_DETB are asserted only if V_{BUS_VALID}

.

9. The FSA9285 follows the Battery Charging 1.2 specification, which uses DP_CON and DM_CON to determine the USB

accessory attached. Refer to Battery Charging 1.2 Specification for details.

www.fairchildsemi.com

FSA9285 • Rev 1.0.3

9

below 6.5V or it senses an accessory detach. Upon exiting an

OVP condition, another OVP interrupt is triggered (reflecting a

change in OVP state) and the OVP status bit is cleared

(indicating an OVP condition is not present).

9. Dead Battery Provision

Since V_BUScharging power connects through it, the FSA9285

must automatically turn on the V_BUSFET to allow the mobile

device to charge after shutdown due to a dead battery. When

detecting that V_BUSis valid, the FSA9285 automatically turns on

the V_BUSFET after BC1.2 charger detection is complete.

Turning on at this time allows the DP / DM switches to turn on

at the same time as the V_BUSFET.

The Over-Current Protection (OCP) feature limits current

through the charger FET to nominally 1.45 A. OCP is only

implemented when V_{BUS_IN}is provided by the attached

accessory. The FSA9285 senses an over-current event, opens

(turns off) the V_BUSFET, and reports this to the baseband by

asserting the OCP bit (to reflect a change in OCP state) in the

Interrupt register. When in an OCP state, the OCP status bit is

written HIGH. While the OCP condition is present, the FSA9285

continually monitors the V_BUScurrent and exits Shutdown Mode

when the V_BUScurrent drops below nominally 1.45 A or it

senses an accessory detach. Upon exiting OCP state, the OCP

Interrupt bit is again written HIGH, indicating a change in OCP

state and the OCP Status bit is written LOW, indicating an OCP

state is not present.

If the FSA9285 detects a USB port (SDP, CDP, or DCP) when

V_BATand V_DDIOare not valid, it applies 0.6V to DP_CON in

accordance with the USB BC1.2 Dead Battery Provision. The

FSA9285 automatically removes the 0.6V on DP_CON upon

detach of an accessory, when V_DDIOreturns to a valid voltage,

or when V_BAT> V_{BAT_TH}. If the mobile device should manually

assert the 0.6V on DP_CON, it can do so using the

ASSERT_D+ bit (bit 2) of the Manual CHG_CTRL register

(14h); V_BUSmust be valid to do so.

10.Over-Voltage Protection (OVP) and Over-

Current Protection (OCP)

11.Audio Accessory Detection

After an audio device is attached and a change in ID_CON

resistance is detected (if ID_DIS=0), the FSA9285 asserts an

interrupt and the baseband processor can read the Resistor

Code register to determine the ID_CON resistance change to

detect if a key, such as MCPC SEND / END, was pressed.

When V_{BUS_IN}is less than nominally 6.5V, the FSA9285 allows

the V_{BUS_IN}supply to enter the chip-power select voltage

regulator block. For V_{BUS_IN}greater than nominally 6.5V, the

input is disconnected, protecting the FSA9285 from excess

voltage. Upon entering Shutdown Mode, the OVP bit in the

Interrupt register is set HIGH (to reflect a change in OVP state)

and an interrupt is sent to the baseband. The OVP Status

register is also written HIGH to indicate that an OVP condition

is present. In Shutdown Mode, the FSA9285 continually

monitors V_BUSand exits Shutdown Mode when V_BUSdrops to

For powered audio accessories with V_BUSpresent, the

FSA9285 detects when V_BUSis valid and interrupts the

baseband processor. The baseband processor must manually

control the FSA9285 switches for proper functionality. MIC can

be switched to either V_BUSor DP_CON through the Manual SW

register, allowing more flexibility.

www.fairchildsemi.com

FSA9285 • Rev 1.0.3

10

12.Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the

recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to

stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress

ratings only.

Symbol

Parameter

Min.

Max.

Unit

V

V_BAT/V_DDIOSupply Voltage from Battery / Baseband

-0.5

-1.0

-2.0

-0.5

-50

6.0

28.0

6.0

V_{BUS_IN}

Supply Voltage from Micro-USB Connector

Switch I/O Voltage

V

USB

V_SW

Stereo/Mono Audio Path Active

All Other Channels

6.0

V

6.0

I_IK

Input Clamp Diode Current

mA

I_CHG

Charger Detect CHG_DETB Pin Current Sink Capability

USB

30

50

I_SW

Switch I/O Current (Continuous)

Audio

60

mA

All Other Channels

USB

50

150

2

mA

A

Audio

Peak Switch Current (Pulsed at 1ms Duration,

<10% Duty Cycle)

I_SWPEAK

Charger FET

All Other Channels

150

+150

+260

mA

C

T_STG

T_J

Storage Temperature Range

-65

Maximum Junction Temperature

Lead Temperature (Soldering, 10 Seconds)

T_L

USB Connector Pins

IEC 61000-4-2 System Level (DP_CON, DM_CON, V_{BUS_IN}

ID_CON) to GND

Air Gap

15000

,

Contact

All Pins

8000

5000

1500

ESD

V

Human Body Model, JEDEC JESD22-A114

Charged Device Model, JEDEC JESD22-C101

13.Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating

conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding

them or designing to Absolute Maximum Ratings.

Symbol

Parameter

Min.

Typ.

3.8

Max.

Unit

V_BAT

V_{BAT_TH}

V_{BUS_IN}

V_DDIO

Battery Supply Voltage

2.7

4.0

1.7

0

4.4

3.3

5.5

3.6

4.4

3.0

5.0

1.0

+85

V

Battery Supply Voltage Threshold for Weak / Dead Battery

Supply Voltage from V_{BUS_IN}Pin

Processor Supply Voltage

3.0

USB Path Active

V_SW

Switch I/O Voltage

Audio Path Active

All Other Pins

-1.5

0

V

ID_CAP

T_A

Capacitive Load on ID_CON Pin for Reliable Accessory Detection

Operating Temperature

nF

ºC

-40

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FSA9285 • Rev 1.0.3

11

14.Switch Path DC Electrical Characteristics

All typical values are at T_A=25°C unless otherwise specified.

T_A= -40 to +85°C

Unit

Symbol

Parameter

V_BAT(V)

Condition

Min.

Typ.

Max.

Host Interface Pins (INTB, CHG-DETB)

V_OH

V_OL

Output High Voltage⁽¹⁰⁾

Output Low Voltage

3.0 to 4.4 I_OH=2 mA

3.0 to 4.4 I_OL=8 mA

0.7 x V_DDIO

V

0.4

I²C Interface Pins – Fast Mode (I2C_SDA, I2C_SCL)

V_IL

V_IH

Low-Level Input Voltage

High-Level Input Voltage

3.0 to 4.4

0.3 x V_DDIO

V

0.7 x V_DDIO

-10

Input Current of I2C_SDA and I2C_SCL

Pins, Input Voltage 0.26 V to 2.34 V

I_I2C

3.0 to 4.4

10

µA

Switch Off Characteristics

All Data Ports Except

Audio & MIC, V_SW=4.4 V

I_OFF

Power-Off Leakage Current

0

4.4

10

µA

All Ports Except Audio &

MIC, I/O Pins=0.3 V,

4.1 V, or Floating

I_NO(OFF)Off Leakage Current

-0.100

0.001

5

0.100

Current Limit if

ID_CON=0V

I_IDSHRTShort-Circuit Current

3.0 to 4.4

mA

USB Switch (DP_HOSTn, DM_HOSTn) ON Paths

V_D+/D-=0 V, 0.4 V,

I_ON=8 mA

8

10

17

Ω

R_ON

USB Switch Paths On Resistance^(11,12)

3.0 to 4.4

V_D+/D-=0V, 3.6 V,

I_ON=8 mA

11

Charging FET ON Path

Over-Voltage Protection (OVP)

Threshold Voltage

V_OVP

R_ON

I_OCP

3.0 to 4.4

6.2

1.2

6.5

6.9

V

mΩ

A

V_{BUS_IN}=4.2 V-5.0 V,

I_ON=1 A

Charging FET On Resistance^(11,12)

200

Over-Current Protection (OCP)

Threshold Current

3.0 to 4.4 V_{BUS_IN}=5.2 V

1.65

Audio_R / Audio_L Switch ON Paths

V_L/R=-0.8 V, 0.8 V,

I_ON=30 mA, f=0-470 kHz

3.5

4.0

0.1

0.2

R_ON

Audio Switch On Resistance^(11,12)

3.0 to 4.4

Ω

V_L/R=-1.5 V, 1.5 V,

I_ON=30 mA, f=0-470 kHz

V_L/R=-0.8 V, 0.8V,

I_ON=30 mA, f=0-470 kHz

R_FLATAudio R_ONFlatness^(11,13)

Ω

V_L/R=-1.5V, 1.5V,

I_ON=30 mA, f=0-470 kHz

R_TERMInternal Termination Resistors

1.5

kΩ

Continued on the following page…

www.fairchildsemi.com

FSA9285 • Rev 1.0.3

12

14.

Switch Path DC Electrical Characteristics (Continued)

All typical values are at T_A=25°C unless otherwise specified.

T_A= -40 to +85°C

Symbol

Parameter

V_BAT(V)

Condition

Unit

Min.

Typ.

Max.

MIC Switch ON Paths

MIC Connected to V_{BUS_IN}

V_SW=0 V, 2.8 V, I_ON=30 mA

,

40

R_ON

MIC Path ON Resistance^(11,12)

Ω

MIC Connected to DP_CON,

V_SW=0 V, 2.8 V, I_ON=30 mA

3.0 to

4.4

Over-Voltage Protection (OVP)

MIC Connected to V_{BUS_IN}

Entering OVP

MIC_OVPThreshold Voltage with MIC on

2.80

3.35

15

V

(14)

V_{BUS_IN}

Total Current Consumption⁽¹⁶⁾

Battery Supply Standby Mode Current

No Accessory Attached (ID_CON

VBUS Floating VBUS Floating

10

Floating)

3.0 to

4.4

I_BAT

µA

Average Battery Supply Standby

Mode Current with Accessory

Attached (ID_CON Not Floating)

V_BUS= 0 V

V_BUS= 5 V

ID_DIS=1

35

50

100⁽¹⁶⁾

150⁽¹⁶⁾

Notes:

10. Does not apply to the CHG_DETB pin because it is open drain.

11. Limits based on Electrical Characterization data.

12. On resistance is the voltage drop between the two terminals at the indicated current through the switch.

13. Flatness is the difference between the maximum and minimum values of on resistance over the specified range of conditions.

14. The MIC bias applied should not exceed 2.8 V.

15. V_DDIOof either 0 V or in the valid range of 1.7 V to 3.6 V.

16. Typically the battery charges from V_BUS

.

15. Capacitance

T_A= -40 to +85°C

Symbol

Parameter

V_BAT(V)

Condition

Unit

Min. Typ. Max.

DP_CON, DM_CON On Capacitance

(USB Mode, Both HOST1 and HOST2)

C_ONUSB

3.8

V_BIAS=0.2 V, f=1 MHz

8

pF

C_I

Capacitance for Each I/O Pin

3.8

2

pF

C_OFF

Off Capacitance (HOST1 and HOST2)

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FSA9285 • Rev 1.0.3

13

16. I²C AC Electrical Characteristics

Fast Mode

Max.

Symbol

Parameter

Min.

Unit

kHz

µs

f_SCL

t_HD;STA

t_LOW

SCL Clock Frequency

0

0.6

400

Hold Time (Repeated) START Condition

LOW Period of SCL Clock

1.3

µs

t_HIGH

t_SU;STA

t_HD;DAT

t_SU;DAT

t_r

HIGH Period of SCL Clock

0.6

µs

Set-up Time for Repeated START Condition

0.6

µs

Data Hold Time

Data Set-up Time⁽¹⁷⁾

0

0.9

µs

100

ns

Rise Time of SDA and SCL Signals⁽¹⁸⁾

Fall Time of SDA and SCL Signals⁽¹⁸⁾

Set-up Time for STOP Condition

BUS-Free Time between STOP and START Conditions

Pulse Width of Spikes that Must Be Suppressed by the Input Filter

20+0.1C_b

0.6

300

ns

(17)

t_f

ns

t_SU;STO

t_BUF

µs

1.3

µs

t_SP

0

50

ns

Notes:

17. C_bequals the total capacitance of one BUS line in pf. If mixed with high-speed devices; faster fall times are allowed, according

to the I²C Bus specification.

18. A fast-mode I²C-Bus^®device can be used in a Standard-Mode I²C-Bus system, but the requirement that t_SU;DAT≥ 250 ns must

be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If a device does stretch

the LOW period of the SCL signal, it must output the next data bit to the SDA line t_{r_max}+ t_SU;DAT= 1000 + 250 = 1250 ns before

the SCL line is released (according to the Standard-Mode I²C Bus specification).

Figure 7.

Definition of Timing for Full-Speed Mode Devices on the I²C Bus^®

Table 5. I²C Slave Address

Name

Size (Bits)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Slave Address

8

0

1

0

1

0

1

R/W

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FSA9285 • Rev 1.0.3

14

17.Switch Path AC Electrical Characteristics

All typical values are for V_BAT=3.8 V at T_A=25ºC unless otherwise specified.

T_A= -40 to +85°C

Symbol

Parameter

Conditions

Unit

Min.

Typ.

Max.

Audio Mode

USB Mode

Audio Mode

USB Mode

f=20 kHz, R_T=32 Ω, C_L=0 pF

f=1 MHz, R_T=50 Ω, C_L=0 pF

f=20 kHz, R_T=32 Ω, C_L=0 pF

f=1 MHz, R_T=50 Ω, C_L=0 pF

-90

-60

Active Channel Crosstalk

DP_CON to DM_CON

Xtalk

O_IRR

dB

-100

-60

Off Isolation

Power Supply Rejection Ratio, MIC on

V_{BUS_IN}

Power Supply Noise 300Mv_PP

f=217 Hz Sine Wave

,

PSRR

THD

-100

0.07

35

dB

%

20 Hz to 20 kHz, R_L=32/16 Ω,

Input Signal Range -1.5 V, 1.5 V

Total Harmonic Distortion (Audio Path)

Skew of Opposite Transitions of the Same

Output (USB Mode)

t_r=t_f=750 ps (10-90%) at 240 MHz,

C_L=0 pF, R_L=50 Ω

t_SK(P)

ps

ms

Time When I2C_SDA and I2C_SCL Both

LOW to Cause Reset

t_I2CRST

See Figure 8

See Figure 10

30

Time from V_{BUS_IN}Valid to V_{BUS_OUT}Valid with

Charger FET Closed and USB Switches

Closed for USB Standard Downstream Port

t_SDPDET

120

ms

Time from V_{BUS_IN}Valid to V_{BUS_OUT}Valid with

t_CHGOUT

Charger FET Closed for Both USB Charging See Figure 11

Ports (CDP and DCP)

160

140

ms

Time from V_{BUS_IN}Valid to Car Kit Type-1 or

See Figure 12

t_CARKIT

Type-2 Charger Detected

Time from ID_CON Not Floating to INTB

LOW to Signal Accessory Attached that is

t_IDDET

ID_CON Resistance-Based Only

(V_{BUS_IN}Not Valid, Default timing

configuration)

See Figure 13

150

600

ms

t_BC11

Timeout for Data Contact During DCD Check

300

900

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FSA9285 • Rev 1.0.3

15

18. Timing Diagrams

V_BAT

I2C_SDA

30ms

Internal Reset Time

400µs

Standby Mode

400µs

Figure 8.

I²C Reset Mode Timing

VBAT

VDDIO

INT_Mask

INTB

INT Mask Clear

INT Event

INT Read

INT Mask

written via I²C

command

Figure 9.

INT Mask to INTB Interrupt Timing Diagram

Charger FET Closed

USB Switches Closed

V_BUS>4.0V

VBUS_IN

XXXXFXLOXATXXXXXXXXXXXXXXXXXXXXXXXXXXXXXFXLOXAXT XXXXXXXXXXX

ID Resistance

VBUS_OUT

120ms

Open

USB Switch State

Closed

120ms

Figure 10. USB Standard Downstream Port Attach Timing⁽¹⁹⁾

FSA9285 • Rev 1.0.3

www.fairchildsemi.com

16

Charger FET Closed, USB

Switches Closed, and

INTB and CHG_DETB Asserted

V_BUS>4.0V

V_BUSVoltage

XXXXFXLOXATXXXXXXXXXXXXXXXXXXXXXXXXXXXXXFXLOXAXT XXXXXXXXXXX

ID Resistance

V_{BUS_OUT}

160ms

Open

USB Switch State

Closed

CHG_DETB Pin

INTB Pin

Charger Detection Time 160ms

Figure 11. USB Dedicated Charging Port (DCP) or Charging Downstream Port (CDP) Attach Timing⁽¹⁹⁾

Charger FET Closed, USB

Switches Closed, and INTB

and CHG_DETB Asserted

V_BUS>4.0V

V_BUSVoltage

FLOAT

XXXXXXXX

ID Resistance

140ms

V_{BUS_Out}

Open

BB Configures

Switches Closed

USB Switch State

Closed

CHG_DETB Pin

INTB Pin

VBUS Detection Time 140ms

Figure 12. Car Kit Type-1 and Type-2 Attach Timing

Accessory

Attached

INTB Asserted

BB Reads INTB

FLOAT

XXXXXX

ID Resistance

Open

BB Configures

USB Switch State

INTB Pin

Switches Closed

Closed

150ms

BB Read

and Clear

Figure 13. ID-Based Accessories, No V_{BUS_IN}Attach Timing⁽²⁰⁾

Notes:

19. USB Switch State timing is based on Automatic Switching mode (EN_MAN_SW = 0). Automatic switching excludes DCP.

20. ID_CON resistance detection based on default Timing Set and Applications register values and on initial ID_CON accessory

attach only (50 ms Resistor Detection Time with 3 ID checks on initial attach = 150 ms typical detection time).

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FSA9285 • Rev 1.0.3

17

19.Bit Definitions

Table 6. I²C Register Map

Reset

Value

Address Register Type

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

01H

02H

Device ID

Control

R

00010000

Version ID

Do Not Use

DCD Timeout

EN

R/W

11010001

00000000

RESETB ID_DIS EN_MAN_SW Do Not Use

Do Not Use

INT Mask

OCP

OVP

MIC_OVP

Change

Resistor Code V_BUS_Valid

03H

05H

07H

Interrupt

R/C

R/W

R

Do Not Use

BC1.2_Complete Do Not Use

Change Change

Change

Interrupt

Mask

Resistor Code

Change

OCP

OVP

MIC_OVP

V_BUS_Valid BC1.2_Complete Do Not Use

Resistor

Code

Do Not

Use

Do Not

Use

Resistor Code

08H

09H

Timing Set R/W

00000000

Do Not Use

Resistor Detection Time

Status

R

ID_SHORT

Do Not Use

OCP

OVP

MIC_OVP

/ID_FLOAT

Do Not Use

V_BUS_Valid

BC1.2_Active

DCD

USB

USB Charging USB Standard

Downstream Port Downstream

Do Not

Use

Dedicated

Charging

Port (DCP)

0AH

Device Type

DAC SAR

00000000

Dock

Do Not Use

(CDP)

Port (SDP)

0BH

13H

00000000

00100111

DAC SAR Value

D+ Switching

Manual SW R/W

D- Switching

Do Not

V_BUSSwitching

Do Not Use

Do Not Use Do Not Use

Max. Capacitance on ID

Manual

R/W

Do Not

Use

Assert

CHG_DETB

14H

1BH

1CH

00000000

X0001000

Do Not Use

MIC_OVP_EN Assert_D+

CHG_CTRL

Use

Do Not

Use

Do Not

Use

Applications1 R/W

Do Not Use

# of Consecutive ID Matches for Attach

Do Not

Use

Do Not

Use

# ID Checks for Resistor

Do Not Use

Applications2 R/W XXXX0101

Code Change

Table 7. Device ID

.

Address: 01H

Reset Value: 00010000

Type: Read

Bit #

Name

Size (Bits)

Description

7:3

2:0

Version ID

5

3

Rev 0.0=00010

Do not use

Do Not Use

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FSA9285 • Rev 1.0.3

18

Table 8. Control

.

Address: 02H

Reset Value: 11010001

Type: Read/Write

Size

(Bits)

Bit #

Name

Description

1: DCD timeout is enabled.

0: DCD timeout is disabled.

7

6

DCDTimeout_EN

1

1: Do nothing.

0: Reset FSA9285 – resets all of FSA9285 except the Control register (02H), Manual

SW (13H), and Manual CHG_CTRL(14H).

Note: This bit is momentarily set to 0 on a write. It immediately reverts to 1.

RESETB

ID_DIS

1: ID_CON resistor detection is disabled after a resistance is detected on ID_CON.

0: ID_CON resistor detection is enabled after a resistance is detected on ID_CON.

Note: The FSA9285 continues to monitor for an ID_FLOAT condition.

5

4

1

1: Configure switches based on Manual SW register settings.

0: Use only defined automatic switch settings.

EN_MAN_SW

This bit needs to be cleared in case of a weak battery explicitly or the device must be

defaulted via a V_DDIOreset for the dead battery case to operate properly.

3

2

1

Do Not Use

1

Do not use.

1: Mask Interrupt – Do not interrupt baseband processor when a bit is set in the

Interrupt register.

0

INT Mask

1

0: Unmask Interrupt – Interrupt baseband processor if any bit is set in the Interrupt

register.

Table 9. Interrupt

.

Address: 03H

Reset Value: 00000000

Type: Read/Clear

Size

(Bits)

Bit #

Name

Description

7

6

Do Not Use

1

N/A

1: OCP state changed.

0: OCP state has not changed.

OCP

Change

1

1: OVP state changed.

OVP

Change

5

4

0: OVP state has not changed.

1: MIC OVP state changed.

MIC_OVP

Change

0: MIC OVP state not changed.

1: Resistor Code value changed.

Resistor Code

Change

0: Resistor Code value has not changed.

Note: This interrupt is disabled when ID_DIS=1. The FSA9285 interrupts if transitioning

from a non-zero Resistor Code to a Resistor Code=zero (ID_CON floating).

3

2

1

1: V_BUS_Valid state changed.

V_BUS_Valid

Change

0: V_BUS_Valid state has not changed.

1: BC1.2 charger detection complete.

1

0

BC1.2_Complete

Do Not Use

1

0: No change in BC1.2 charger detection status.

N/A

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FSA9285 • Rev 1.0.3

19

Table 10. Interrupt Mask

.

Address: 05H

Reset Value: 00000000

Type: Read/Write

Bit #

Name

Size (Bits)

Description

7

Do Not Use

1

N/A

1: Mask OCP state-change interrupt.

6

5

4

3

2

OCP

OVP

1

0: Do not mask OCP state-change interrupt.

1: Mask OVP state-change interrupt.

0: Do not mask OVP state-change interrupt.

1: Mask MIC_OVP state-change interrupt.

MIC_OVP

0: Do not mask MIC_OVP state-change interrupt.

1: Mask Resistor Code value-change interrupt.

Resistor Code

Change

0: Do not mask Resistor Code value-change interrupt.

1: Mask V_BUS__Validstate-change interrupt.

0: Do not mask V_{BUS_Valid}state-change interrupt.

V_BUS_Valid

1: Mask BC1.2_complete interrupt.

1

0

BC1.2_Complete

Do Not Use

1

0: Do not mask BC1.2_complete interrupt.

N/A

Table 11. Resistor Code

.

Address: 07H

Reset Value: 00000000

Type: Read

Bit #

Name

Size (Bits)

Description

7:5

4:0

Do Not Use

3

5

N/A

Resistor Code

Resistor code value read from ID_CON (see Table 3 Resistor Identification).

Table 12. Timing Set

.

Address: 08H

Reset Value: 00000000

Type: Read/Write

Bit #

Name

Size (Bits)

Description

7:4

3:0

Do Not Use

4

N/A

Resistor Detection

Time

Time to complete the ID_CON resistance measurement for accessory detection

(see Table 13).

4

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FSA9285 • Rev 1.0.3

20

Table 13. Timing Table for Timing Set Register

Setting Value

Resistor Detection Time (ms)

0000

0001

50

100

150

200

300

400

500

600

700

800

900

1000

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101-1111

Table 14. Status

.

Address: 09H

Reset Value: 00000000

Type: Read/Write

Bit #

Name

Size (Bits)

Description

1: ID_SHORT detected.

7

6

5

4

3

2

ID_SHORT

1

0: ID_SHORT not detected.

1: V_BUSin over-current state.

OCP

1

0: V_BUSnot in over-current state.

1: V_BUSin over-voltage state.

0: V_BUSnot in over-voltage state.

OVP

1: MIC in over-voltage state

MIC_OVP

/ID_FLOAT

V_BUS_Valid

0: MIC not in over-voltage state

1: ID_CON not floating (resistor detected).

0: ID_CON floating (no resistor detected).

1: V_BUSis valid.

0: V_BUSis not valid.

1: BC1.2 is active. (This is true if a connect is attempted with DCD Timeout

disabled and no DCD.)

1

0

BC1.2_Active

DCD

1

0: BC1.2 IDLE.

1: Data contact detected on last charger-detect sequence.

0: No data contact detected on last charger-detect sequence.

www.fairchildsemi.com

FSA9285 • Rev 1.0.3

21

Table 15. Device Type

.

Address: 0AH

Reset Value: 00000000

Type: Read

Bit #

Name

Size (Bits)

Description

7

6

Do Not Use

1

Do not use.

1: Charging dock detected.

5

Dock

1

0: Charging dock not detected.

4

3

Do Not Use

1

Do not use.

1: USB dedicated charging port (DCP) charger detected.

0: USB dedicated charging port (DCP) charger not detected.

2

1

0

DCP

CDP

SDP

1

1: USB charging downstream port (CDP) charger detected.

0: USB charging downstream port (CDP) charger not detected.

1: USB standard downstream port (SDP) detected.

0: USB standard downstream port (SDP) not detected.

Table 16. DAC SAR

.

Address: 0BH

Reset Value: 00000000

Type: Read

Bit #

Name

Size (Bits)

Description

DAC_SAR Value – Indicates raw 8-bit resistance value detected (see Table 3

Resistor Identification).

7:0

DAC_SAR

8

Table 17. Manual SW⁽²¹⁾

.

Address: 13H

Reset Value: 00100111

Type: Read/Write

Bit #

Name

Size (Bits)

Description

000: Open all switches.

001: DM_CON connected to DM_HOST1 of USB port.

010: DM_CON connected to Audio_L.

7:5

DM_CON Switching

3

011: DM_CON connected to DM_HOST2 of USB port.

000: Open all switches.

001: DP_CON connected to DP_HOST1 of USB port.

DP_CON

Switching

4:2

1:0

3

2

010: DP_CON connected to Audio_R.

011: DP_CON connected to DP_HOST2 of USB port.

100: DP_CON connected to MIC.

00: Open all switches.

01: Do not use.

V_{BUS_IN}Switching

10: V_{BUS_IN}connected to MIC.

11: V_{BUS_IN}connected to V_{BUS_OUT}(phone sinks current from attached

accessory).⁽²²⁾

Notes:

21. When changing manual switch configurations on a single attach, the accessory must pass through an “Open All Switches” state

between configurations. Manual Modes require the EN_MAN_SW Manual Mode bit in the Control register (02H) to be set.

22. V_{BUS_IN}must be valid for the charger FET to close in manual FET switching.

www.fairchildsemi.com

FSA9285 • Rev 1.0.3

22

Table 18. Manual CHG_CTRL

.

Address: 14H

Reset Value: 00000000

Type: Read/Write

Bit #

Name

Size (Bits)

Description

7:5

Do Not Use

3

N/A

1: Assert CHG_DETB LOW.

Assert

CHG_DETB

0: Normal operation (CHG_DETB asserted LOW for DCP, CDP, ACA, and

Car Kit Type 1/2; CHG_DETB is HIGH otherwise.)

Note: EN_MAN_SW is not required for this bit to take effect.

4

3

1

1: Enable MIC_OVP (only use when MIC is connected to V_BUS).

0: Do not enable MIC_OVP.

MIC_OVP_EN

Note: EN_MAN_SW is not required for this bit to take effect.

1: Force 0.6 V on DP_CON.

2

Assert_D+

1

2

0: Do not force 0.6 V on DP_CON.

Note: EN_MAN_SW is not required for this bit to take effect, V_BUSmust be valid.

1:0

Do Not Use

N/A

Table 19. Applications1

.

Address: 1BH

Reset Value: X0001000

Type: Read/Write

Bit #

Name

Size (Bits)

Description

7:5

Do Not Use

3

N/A

000: 1

001: 2

010: 3

011: 4

100: 5

101: 6

110: 7

111: 8

# Consecutive ID

Matches for Attach

4:2

1:0

3

2

Do Not Use

N/A

Table 20. Applications2

.

Address: 1CH

Reset Value: XXXX0101

Type: Read/Write

Bit #

Name

Size (Bits)

Description

7:4

Do Not Use

4

N/A

00: 1

01: 2

10: 3

11: 4

# ID Checks for

Resistor Code

Change

3:2

1:0

2

00: 500 pF

01: 1 nF

Max. Capacitance

on ID

10: 1.5 nF

11: 2 nF

www.fairchildsemi.com

FSA9285 • Rev 1.0.3

23

Product-Specific Dimensions

Product

D

E

X

Y

FSA9285UCX

2.010 mm

1.672 mm

0.236 mm

0.205 mm

Part Number Operating Temperature Range Top Mark

FSA9285UCX -40 to +85°C NX

Package

20-Lead, WLCSP (2.010 x 1.672 x 0.625 mm, 0.4 mm Pitch)

www.fairchildsemi.com

FSA9285 • Rev 1.0.3

24

F

BALL A1

INDEX AREA

E

A

1.20

ꢀꢁꢂꢇꢋ

Cu Pad

ꢀꢁꢂꢀ

Cu Pad

B

A1

0.03 C

2X

1.60

0.40

ꢀꢁꢄꢇꢋꢈ6ROGHU

ꢀꢁꢄꢀꢈ6ROGHU

D

Mask Opening

0.40

0.03 C

option 1

option 2

2X

RECOMMENDED LAND PATTERN

(NSMD TYPE)

TOP VIEW

0.06 C

0.625

0.547

ꢀꢁꢄꢅꢆꢀꢁꢀꢇꢆ

ꢀꢁꢂꢀꢆꢀꢁꢀꢂꢇ

E

0.05 C

C

D

SEATING PLANE

SIDE VIEWS

NOTES:

A. NO JEDEC REGISTRATION APPLIES.

B. DIMENSIONS ARE IN MILLIMETERS.

C. DIMENSIONS AND TOLERANCE

PER ASMEY14.5M, 2009.

D. DATUM C IS DEFINED BY THE SPHERICAL

CROWNS OF THE BALLS.

E. PACKAGE NOMINAL HEIGHT IS 586 MICRONS

ꢈꢈꢈꢈꢄꢉꢈ0,&5216ꢈꢊꢋꢌꢅꢍꢃꢂꢋꢈ0,&5216ꢎꢁ

F. FOR DIMENSIONS D, E, X, AND Y SEE

PRODUCT DATASHEET.

0.005

C A B

1.20

ꢀꢁꢂꢃꢀꢀꢁꢀꢂ

0.40

20X

E

D

C

B

1.60

ꢊ<ꢎꢈꢀꢁꢀꢇꢆ

0.40

A

F

1

2 3

4

ꢊ;ꢎꢈꢀꢁꢀꢇꢆ

G. DRAWING FILNAME: MKT-UC020AArev4.

BOTTOM VIEW

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1


型号：	FSA9285UCX
厂家：	ONSEMI
描述：	符合 MCPC，USB 端口，多媒体开关，带自动检测开关 PC 商用集成电路
文件：	总27页 (文件大小：978K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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