FSB50550BL [ONSEMI]
Intelligent Power Module, 500V, 3A, Slow ver for EMI optimization;
| 型号： | FSB50550BL |
| 厂家： | 
ONSEMI |
| 描述： | Intelligent Power Module, 500V, 3A, Slow ver for EMI optimization 电动机控制 |
| 文件： | 总11页 (文件大小：821K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Motion SPM) 5 Series
FSB50550BL, FSB50550BSL
General Description
The FSB50550BL/FSB50550BSL is an advanced Motion SPM 5
module providing a fully−featured, high−performance inverter output
stage for AC Induction, BLDC and PMSM motors. These modules
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®
integrate optimized gate drive of the built−in MOSFETs (FRFET
technology) to minimize EMI and losses, while also
providing multiple on−module protection features including
under−voltage lockouts and thermal monitoring. The built−in
high−speed HVIC requires only a single supply voltage and translates
the incoming logic−level gate inputs to the high−voltage, high−current
drive signals required to properly drive the module’s internal
MOSFETs. Separate open−source MOSFET terminals are available
for each phase to support the widest variety of control algorithms.
SPM5E−023/23LD
CASE MODEJ
Features
• UL Certified No. E209204 (UL1557)
• Optimized for over 10 kHz Switching Frequency
• 500 V FRFET MOSFET 3−Phase Inverter with Gate Drivers and
Protection
• Built−In Bootstrap Diodes Simplify PCB Layout
• Separate Open−Source Pins from Low−Side MOSFETs for
Three−Phase Current−Sensing
• Active−HIGH Interface, Works with 3.3/5 V Logic,
Schmitt−Trigger Input
• Optimized for Low Electromagnetic Interference
SPM5H−023/23LD
CASE MODEM
• HVIC Temperature−Sensing Built−In for Temperature Monitoring
• HVIC for Gate Driving and Under−Voltage Protection
• Isolation Rating: 1500 V /min.
rms
MARKING DIAGRAM
• Moisture Sensitive Level (MSL) 3 for SMD PKG
• This Device is Pb−Free and is RoHS Compliant
ON
Applications
FSB50550XX
ZKKXYY
• 3−Phase Inverter Driver for Small Power AC Motor Drives
FSB50550XX = Specific Device Code
Related Source
XX
= BL for FSB50550BL
= BSL for FSB50550BSL
= Assembly Code
®
• AN−9080 − Motion SPM 5 Series Version 2 User’s Guide
®
• AN−9082 − Motion SPM 5 Series Thermal Performance by Contact
Z
KK
XYY
= Lot Run Traceability Code
= Date Code
Pressure
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
November, 2019 − Rev. 0
FSB50550BL/D
FSB50550BL, FSB50550BSL
ORDERING INFORMATION
†
Device
Package
Packing Type
Reel Size
Quantity
Device Marking
FSB50550BL
FSB50550BL
SPM5E−023
SPM5H−023
Rail
NA
15
FSB50550BSL
FSB50550BSL
Tape & Reel
330 mm
450
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ABSOLUTE MAXIMUM RATINGS
Conditions
Symbol
Parameter
Rating
Unit
INVERTER PART (Each MOSFET Unless Otherwise Specified)
V
*I
Drain−Source Voltage of Each MOSFET
500
3.0
V
A
DSS
Each MOSFET Drain Current, Continuous
T
C
T
C
T
C
T
C
= 25°C
= 80°C
D 25
*I
D 80
Each MOSFET Drain Current, Continuous
1.9
A
A
= 25°C, PW < 100 ms
= 80°C, F < 20 kHz
*I
Each MOSFET Drain Current, Peak
Each FRFET Drain Current, Rms
7.0
1.3
DP
*I
DRMS
A
rms
PWM
CONTROL PART (Each HVIC Unless Otherwise Specified)
V
Control Supply Voltage
High−Side Bias Voltage
Input Signal Voltage
Applied between V and COM
20
20
V
V
V
DD
DD
V
Applied between V and V
B S
BS
V
Applied between V and COM
−0.3~V + 0.3
IN
IN
DD
BOOTSTRAP DIODE PART (Each Bootstrap Diode Unless Otherwise Specified)
V
Maximum Repetitive Reverse Voltage
Forward Current
500
0.5
2.0
V
A
A
RRMB
* I
T
= 25°C
FB
C
* I
Forward Current (Peak)
T
= 25°C, Under 1 ms Pulse Width
FPB
C
THERMAL RESISTANCE
R
Junction to Case Thermal Resistance
(Note 1)
Inverter MOSFET Part (Per Module)
2.2
°C/W
th(j−c)Q
TOTAL SYSTEM
T
Operating Junction Temperature
−40~150
°C
°C
J
T
Storage Temperature
Isolation Voltage
−40~125
STG
V
ISO
60 Hz, Sinusoidal, 1 minute,
Connect Pins to Heat Sink Plate
1500
V
rms
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
NOTES:
1. For the measurement point of case temperature T , Please refer to Figure 4.
C
2. Marking “*” is calculation value or design factor.
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2
FSB50550BL, FSB50550BSL
PIN DESCRIPTIONS
Pin No.
1
Pin Name
COM
Pin Description
IC Common Supply Ground
2
V
Bias Voltage for U−Phase High−Side MOSFET Driving
Bias Voltage for U−Phase IC and Low−Side MOSFET Driving
Signal Input for U−Phase High−Side
B(U)
3
V
DD(U)
4
IN
(UH)
5
IN
(UL)
Signal Input for U−Phase Low−Side
6
N.C
No Connection
7
V
Bias Voltage for V−Phase High Side MOSFET Driving
Bias Voltage for V−Phase IC and Low Side MOSFET Driving
Signal Input for V−Phase High−Side
B(V)
8
V
DD(V)
9
IN
(VH)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
IN
Signal Input for V−Phase Low−Side
(VL)
V
Output for HVIC Temperature Sensing
TS
V
B(W)
Bias Voltage for W−Phase High−Side MOSFET Driving
Bias Voltage for W−Phase IC and Low−Side MOSFET Driving
Signal Input for W−Phase High−Side
V
DD(W)
IN
(WH)
IN
(WL)
Signal Input for W−Phase Low−Side
N.C
No Connection
P
Positive DC−Link Input
U, V
Output for U−Phase & Bias Voltage Ground for High−Side MOSFET Driving
Negative DC−Link Input for U−Phase
S(U)
U
N
N
Negative DC−Link Input for V−Phase
V
V, V
Output for V−Phase & Bias Voltage Ground for High−Side MOSFET Driving
Negative DC−Link Input for W−Phase
S(V)
W
N
W, V
Output for W Phase & Bias Voltage Ground for High−Side MOSFET Driving
S(W)
(1) COM
(2) V
(17) P
B(U)
(3) V
VDD
HIN
DD(U)
(4) IN(UH)
(5) IN(UL)
(18) U, VS(U)
LIN
VS
LO
COM
(6) N.C
(19) NU
(20) NV
(7) VB(V)
(8) VDD(V)
(9) IN(VH)
(10) IN(VL)
VDD
HIN
LIN
VB
(21) V, VS(V)
COM
VTS
(11)
VTS
(12) VB(W)
(13) VDD(W)
VDD
HIN
VB
LO
(22) NW
(14) IN
(WH)
(23) W, VS(W)
(15) IN
LIN
(WL)
COM
(16)N.C
Figure 1. Pin Configuration and Internal Block Diagram (Bottom View)
NOTE:
3. Source terminal of each low−side MOSFET is not connected to supply ground or bias voltage ground inside Motion SPM 5 product. External
connections should be made as indicated in Figure 3.
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3
FSB50550BL, FSB50550BSL
ELECTRICAL CHARACTERISTICS (T = 25°C, V = V = 15 V Unless Otherwise Specified.)
J
DD
BS
Symbol
Parameter
Test Conditions
Min.
Typ. Max. Unit
INVERTER PART (Each MOSFET Unless Otherwise Specified)
BV
Drain−Source Breakdown Voltage
V
V
V
= 0 V, I = 1 mA (Note 4)
500
−
−
−
−
1
V
mA
W
DSS
IN
D
I
Zero Gate Voltage Drain Current
= 0 V, V = 500 V
DS
DSS
IN
R
Static Drain−Source Turn−On
Resistance
= V = 15 V, V = 5 V, I = 1.0 A
−
2.3
3.0
DS(on)
DD
BS
IN
D
V
t
Drain−Source Diode Forward Voltage
V
= V = 15 V, V = 0 V, I = −1.0 A
−
−
−
1.3
V
SD
DD
BS
IN
D
Switching Times
V
V
= 300 V, V = V = 15 V, I = 1.0 A
650
−
ns
ns
ns
mJ
mJ
ON
PN
IN
DD
BS
D
= 0 V ↔ 5 V, Inductive Load L = 3 mH
t
−
−
−
−
950
150
40
−
−
−
−
High− and Low−Side MOSFET Switching
(Note 5)
OFF
t
rr
E
ON
E
OFF
5
RBSOA Reverse Bias Safe Operating Area
V
V
= 400 V, V = V = 15 V, I = (TBD),
Full Square
PN
DS
DD
BS
D
= BV
, T = 150°C
DSS
J
High− and Low−Side MOSFET Switching (Note 6)
CONTROL PART (Each HVIC Unless Otherwise Specified)
I
Quiescent V Current
V
DD
V
BS
V
DD
= 15 V, V = 0 V Applied between V and
−
−
−
−
−
−
200
100
900
mA
mA
mA
QDD
DD
IN
DD
COM
I
Quiescent V Current
= 15 V, V = 0 V Applied between V
− U,
B(U)
QBS
PDD
BS
IN
V
V
− V, V
− W
B(V)
B(W)
I
Operating V Supply Current
− COM
= 15 V, f
= 20 kHz,
DD
DD
PWM
duty = 50%, Applied to One
PWM Signal Input for
Low−Side
I
Operating V Supply Current
V
B(U)
V
B(V)
V
B(W)
− V
− V
,
V
PWM
= V = 15 V,
−
−
800
mA
PBS
BS
S(U)
S(V)
− V
DD
BS
,
f
= 20 kHz,
Duty = 50%, Applied to
One PWM Signal Input
for High−Side
S(W)
UV
UV
UV
UV
V
Low−Side Under−Voltage Protection
V
DD
V
DD
V
BS
V
BS
V
DD
Under−Voltage Protection Detection Level
Under−Voltage Protection Reset Level
Under−Voltage Protection Detection Level
Under−Voltage Protection Reset Level
7.4
8.0
7.4
8.0
600
8.0
8.9
8.0
8.9
790
9.4
9.8
9.4
9.8
980
V
V
DDD
DDR
BSD
BSR
TS
(Figure 8)
High−Side Under−Voltage Protection
(Figure 9)
V
V
HVIC Temperature Sensing Voltage
Output
= 15 V, T
= 25°C (Note 7)
mV
HVIC
V
ON Threshold Voltage
OFF Threshold Voltage
Logic HIGH Level
Logic LOW Level
Applied between V and
−
−
−
2.9
V
V
IH
IN
COM
V
0.8
−
IL
BOOTSTRAP DIODE PART (Each Bootstrap Diode Unless Otherwise Specified)
V
Forward Voltage
I = 0.1 A, T = 25°C (Note 8)
−
−
2.5
80
−
−
V
FB
rrB
F
C
t
Reverse Recovery Time
I = 0.1 A, T = 25°C
ns
F
C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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4
FSB50550BL, FSB50550BSL
RECOMMENDED OPERATING CONDITION
Symbol
Parameter
Supply Voltage
Conditions
Min.
−
Typ.
300
15.0
15.0
−
Max.
400
Unit
V
V
Applied between P and N
PN
DD
V
Control Supply Voltage
Applied between V and COM
13.5
13.5
3.0
0
16.5
16.5
V
DD
V
BS
High−Side Bias Voltage
Applied between V and V
S
V
B
V
IN(ON)
Input ON Threshold Voltage
Input OFF Threshold Voltage
Blanking Time for Preventing Arm−Short
PWM Switching Frequency
Applied between V and COM
V
DD
V
IN
V
−
0.6
−
V
IN(OFF)
t
V
= V = 13.5~16.5 V, T ≤ 150°C
1.0
−
−
ms
kHz
dead
DD
BS
J
f
T ≤ 150°C
J
15
−
PWM
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Built in Bootstrap Diode V −I Characteristic
F
F
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
V [V]
F
T
C
= 255C
Figure 2. Built−in Bootstrap Diode Characteristics (Typical)
NOTES:
4. BV
is the absolute maximum voltage rating between drain and source terminal of each MOSFET inside Motion SPM 5 product. V should
DSS
PN
be sufficiently less than this value considering the effect of the stray inductance so that V should not exceed BV
in any case.
PN
DSS
5. t and t
include the propagation delay of the internal drive IC. Listed values are measured at the laboratory test condition, and they can
ON
OFF
be different according to the field applications due to the effect of different printed circuit boards and wirings. Please see Figure 6 for the
switching time definition with the switching test circuit of Figure 7.
6. The peak current and voltage of each MOSFET during the switching operation should be included in the Safe Operating Area (SOA). Please
see Figure 7 for the RBSOA test circuit that is same as the switching test circuit.
7. V is only for sensing−temperature of module and cannot shutdown MOSFETs automatically.
ts
8. Built in bootstrap diode includes around 15 W resistance characteristic. Please refer to Figure 2.
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5
FSB50550BL, FSB50550BSL
These values depend on PWM control algorithm
Example Circuit: V phase
*
C
1
+15 V
V
DC
P
HIN
0
LIN
0
Output
Note
VDD
HIN
VB
HO
VS
LO
Inverter
Output
Z
0
Both FRFET Off
Low side FRFET On
High side FRFET On
Shoot through
R
5
V
0
1
LIN
1
0
V
DC
C
3
COM
1
1
Forbidden
Z
C
5
R
3
V
N
TS
Open Open
Same as (0,0)
C
4
One Leg Diagram of Motion SPM 5 Product
C
2
10 mF
* Example of Bootstrap Parameters
:
C
= C = 1 mF Ceramic Capacitor
2
1
Figure 3. Recommended MCU Interface and Bootstrap Circuit with Parameters
NOTES:
9. Parameters for bootstrap circuit elements are dependent on PWM algorithm. For 15 kHz of switching frequency, typical example of
parameters is shown above.
10.RC−coupling (R and C ) and C at each input of Motion SPM 5 products and MCU (Indicated as Dotted Lines) may be used to prevent
5
5
4
improper signal due to surge−noise.
11. Bold lines should be short and thick in PCB pattern to have small stray inductance of circuit, which results in the reduction of surge−voltage.
Bypass capacitors such as C , C and C should have good high−frequency characteristics to absorb high−frequency ripple−current.
1
2
3
Figure 4. Case Temperature Measurement
NOTE:
12.Attach the thermocouple on top of the heat−sink of SPM 5 package (between SPM 5 package and heatsink if applied) to get the correct
temperature measurement.
3.5
3.0
2.5
2.0
1.5
1.0
0.5
20
40
60
80
100
[°C]
120
140
160
T
HVIC
Figure 5. Temperature Profile of VTS (Typical)
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6
FSB50550BL, FSB50550BSL
V
V
IN
V
IN
I
rr
120% of I
100% of I
D
D
I
D
DS
10% of I
D
V
DS
I
D
t
t
rr
t
OFF
ON
(a) Turn−on
(b) Turn−off
Figure 6. Switching Time Definitions
C
BS
V
DD
I
D
VCC
HIN
VB
HO
VS
LO
L
V
DC
LIN
+
COM
V
DS
−
V
TS
One Leg Diagram of Motion SPM 5 Product
Figure 7. Switching and RBSOA (Single−Pulse) Test Circuit (Low−Side)
Input Signal
UV Protection
RESET
SET
RESET
Status
UV
DDR
Low−Side Supply, V
DD
UV
DDD
MOSFET Current
Figure 8. Under−Voltage Protection (Low−Side)
Input Signal
UV Protection
Status
RESET
SET
RESET
UV
BSR
High−Side Supply, V
BS
UV
BSD
MOSFET Current
Figure 9. Under−Voltage Protection (High−Side)
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FSB50550BL, FSB50550BSL
C
1
(1) COM
(2) V
(17) P
B(U)
(3) V
DD(U)
VDD
HIN
VB
HO
VS
LO
R
(4) IN
5
(UH)
(UL)
(18) U, V
S(U)
(5) IN
LIN
C
V
DC
3
COM
C
C
2
5
(6) N.C
(19) N
U
(7) V
(8) V
B(V)
(20) N
(21) V, V
DD(V)
V
VDD
HIN
VB
HO
VS
LO
(9) IN
(VH)
S(V)
(10) IN
(VL)
M
LIN
COM
(11) V
TS
V
TS
(12) V
(13) V
B(W)
(22) N
W
DD(W)
VDD
HIN
VB
HO
VS
LO
(14) IN
(15) IN
(WH)
(WL)
(23) W, V
S(W)
LIN
COM
(16) N.C
C
4
R
For current−sensing and protection
4
15 V
Supply
C
R
3
6
Figure 10. Example of Application Circuit
NOTES:
13.About pin position, refer to Figure 1.
14.RC−coupling (R and C , R and C ) and C at each input of Motion SPM 5 product and MCU are useful to prevent improper input signal
5
5
4
6
4
caused by surge−noise.
15.The voltage−drop across R affects the low−side switching performance and the bootstrap characteristics since it is placed between COM
3
and the source terminal of the low−side MOSFET. For this reason, the voltage drop across R should be less than 1 V in the steady−state.
3
16.Ground−wires and output terminals, should be thick and short in order to avoid surge−voltage and malfunction of HVIC.
17.All the filter capacitors should be connected close to Motion SPM 5 product, and they should have good characteristics for rejecting
high−frequency ripple current.
SPM and FRFET are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other
countries.
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SPM5E−023 / 23LD, PDD STD, FULL PACK, DIP TYPE
CASE MODEJ
ISSUE O
DATE 31 JAN 2017
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13543G
SPM5E−023 / 23LD, PDD STD, FULL PACK, DIP TYPE
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SPM5H−023 / 23LD, PDD STD, SPM23−BD (Ver1.5) SMD TYPE
CASE MODEM
ISSUE O
DATE 31 JAN 2017
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13546G
SPM5H−023 / 23LD, PDD STD, SPM23−BD (Ver1.5) SMD TYPE
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
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onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
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