FSBH0370NY [ONSEMI]
用于 19 W 离线反激式转换器的 700 V 集成电源开关,100 kHz,提供通电/欠压保护;型号: | FSBH0370NY |
厂家: | ONSEMI |
描述: | 用于 19 W 离线反激式转换器的 700 V 集成电源开关,100 kHz,提供通电/欠压保护 开关 信息通信管理 电源开关 光电二极管 转换器 |
文件: | 总18页 (文件大小:1216K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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FSBH0F70A, FSBH0170/A, FSBH0270/A, FSBH0370
Green Mode Fairchild Power Switch (FPS™)
Features
Description
The highly integrated FSBH-series consists of an
integrated current-mode Pulse Width Modulator (PWM)
and an avalanche-rugged 700V SenseFET. It is
specifically designed for high-performance offline
Switch Mode Power Supplies (SMPS) with minimal
external components.
Brownout Protection with Hysteresis
Built-In 5ms Soft-Start Function
Internal Avalanche-Rugged 700V SenseFET
No Acoustic Noise During Light-Load Operation
High-Voltage Startup
The integrated PWM controller features include a
proprietary green-mode function that provides off-time
modulation to linearly decrease the switching frequency
at light-load conditions to minimize standby power
consumption. To avoid acoustic-noise problems, the
minimum PWM frequency is set above 18kHz. This
green-mode function enables the power supply to meet
international power conservation requirements. The
PWM controller is manufactured using the BiCMOS
process to further reduce power consumption. The
FSBH-series turns off some internal circuits to improve
power saving when VFB is lower than 1.6V, which allows
an operating current of only 2.5mA.
Linearly Decreasing PWM Frequency to 18KHz
Peak-Current-Mode Control
Cycle-by-Cycle Current Limiting
Leading-Edge Blanking (LEB)
Synchronized Slope Compensation
Internal Open-Loop Protection
VDD Under-Voltage Lockout (UVLO)
VDD Over-Voltage Protection (OVP)
Internal Auto-Restart Circuit (OVP, OTP)
Constant Power Limit (Full AC Input Range)
Internal OTP Sensor with Hysteresis
The FSBH-series has built-in synchronized slope
compensation to achieve stable peak-current-mode
control. The proprietary external line compensation
ensures constant output power limit over a wide AC
input voltage range, from 90VAC to 264VAC
.
VIN Pin for Pull-HIGH Latch Function and Pull-
LOW Auto-Recovery Protection
The FSBH-series provides many protection functions. In
addition to cycle-by-cycle current limiting, the internal
open-loop protection circuit ensures safety when an
open-loop or output short occurs. PWM output is
disabled until VDD drops below the VTH-OLP, then the
controller starts up again. As long as VDD exceeds 28V,
the internal OVP circuit is triggered.
Applications
General-purpose switch-mode power supplies and
flyback power converters, including:
Auxiliary Power Supply for PC and Server
Compared with a discrete MOSFET and controller or
RCC switching converter solution, the FSBH-series
reduces total component count, design size, and
weight; while increasing efficiency, productivity, and
system reliability. These devices provide a basic
platform that is well suited for the design of cost-
effective flyback converters, such as in PC auxiliary
power supplies.
SMPS for VCR, SVR, STB, DVD & DVCD Player,
Printer, Facsimile, and Scanner
Adapter for Camcorder
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSBH0270 • Rev. 2, Feb-2020
Ordering Information
Operating
Temperature Range
VIN Pin
(PIN #4)
Packing
Method
Part Number
Sense FET
Package
FSBH0F70ANY
FSBH0170ANY
FSBH0270ANY
FSBH0170NY
FSBH0270NY
FSBH0370NY
0.5A 700V
1.0A 700V
2.0A 700V
1.0A 700V
2.0A 700V
3.0A 700V
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
Not Available
Enabled
8-Pin Dual In-Line
Package (DIP)
Tube
Application Diagram
HV
Drain
VIN
FB
VDD
GND
Figure 1. Typical Flyback Application
230VAC ± 15%(2)
Output Power Table(1)
85-265VAC
Product
Adapter(3)
Open Frame(4)
Adapter(3)
Open Frame(4)
FSBH0F70A
FSBH0170/A
FSBH0270/A
7W
10W
10W
15W
20W
25W
6W
9W
8W
13W
16W
19W
14W
11W
13W
FSBH0370
17.5W
Notes:
1. The maximum output power can be limited by junction temperature.
2. 230 VAC or 100/115 VAC with doublers.
3. Typical continuous power in a non-ventilated enclosed adapter with sufficient drain pattern as a heat sink at
50°C ambient.
4. Maximum practical continuous power in an open-frame design with sufficient drain pattern as a heat sink at
50°C ambient.
© 2009 Fairchild Semiconductor Corporation
FSBH0270 • Rev. 2, Feb-2020
www.fairchildsemi.com
2
Internal Block Diagrams
Figure 2. FSBH0170, FSBH0270, FSBH0370 Internal Block Diagram
Figure 3. FSBH0F70A, FSBH0170A, FSBH0270A Internal Block Diagram
© 2009 Fairchild Semiconductor Corporation
FSBH0270 • Rev. 2, Feb-2020
www.fairchildsemi.com
3
Pin Configuration
8
8
F – Fairchild Logo
Z – Plant Code
ZXYTT
BH0F70A
TPM
ZXYTT
BH0170A
TPM
X – 1-Digit Year Code
Y – 1-Digit Week Code
TT – 2-Digit Die Run Code
T – Package Type (N:DIP)
P – Y: Green Package
M – Manufacture Flow Code
1
8
1
8
ZXYTT
BH0270A
TPM
ZXYTT
BH0170
TPM
1
8
1
8
ZXYTT
BH0270
TPM
ZXYTT
BH0370
TPM
1
1
Figure 4. Pin Configuration and Top Mark Information
Pin Definitions
Pin #
Name Description
1
GND
Ground. SenseFET source terminal on primary side and internal controller ground.
Power Supply. The internal protection circuit disables PWM output as long as VDD exceeds the
OVP trigger point.
2
3
VDD
Feedback. The signal from the external compensation circuit is fed into this pin. The PWM duty
cycle is determined in response to the signal on this pin and the internal current-sense signal.
FB
Line-Voltage Detection. The line-voltage detection is used for brownout protection with
hysteresis and constant output power limit over universal AC input range. This pin has additional
protections that are pull-HIGH latch and pull-LOW auto recovery, depending on the application.
VIN
4
NC
HV
No Connection for FSBH0F70A, FSBH0170A and FSBH0270A.
5
6
7
8
Startup. For startup, this pin is pulled HIGH to the line input or bulk capacitor via resistors.
SenseFET Drain. High-voltage power SenseFET drain connection.
SenseFET Drain. High-voltage power SenseFET drain connection.
SenseFET Drain. High-voltage power SenseFET drain connection.
Drain
Drain
Drain
© 2009 Fairchild Semiconductor Corporation
FSBH0270 • Rev. 2, Feb-2020
www.fairchildsemi.com
4
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
700
1.5
4.0
8.0
12.0
10
Unit
VDRAIN
Drain Pin Voltage(5,6)
FSBH0x70/A
FSBH0F70A
FSBH0170/A
FSBH0270/A
FSBH0370
V
IDM
Drain Current Pulsed(7)
A
FSBH0F70A
FSBH0170/A
FSBH0270/A
FSBH0370
50
EAS
Single Pulsed Avalanche Energy(8)
mJ
140
230
30
VDD
VFB
VIN
VHV
PD
DC Supply Voltage
V
V
FB Pin Input Voltage
-0.3
-0.3
7.0
7.0
700
1.5
80
VIN Pin Input Voltage
V
HV Pin Input Voltage
V
Power Dissipation (TA<50°C)
Junction-to-Air Thermal Resistance
Junction-to-Case Thermal Resistance
Operating Junction Temperature
Storage Temperature Range
W
θJA
θJC
TJ
°C/W
°C/W
°C
20
Internally limited(9)
TSTG
TL
-55
+150
+260
°C
Lead Temperature (Wave Soldering or IR, 10 Seconds)
Human Body Model:
°C
3
1
JESD22-A114
Electrostatic Discharge Capability,
All pins except HV pin
ESD
kV
Charged Device Model:
JESD22-C101
Notes:
5. All voltage values, except differential voltages, are given with respect to the network ground terminal.
6. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
7. Non-repetitive rating: pulse width is limited by maximum junction temperature.
8. L = 51mH, starting TJ = 25°C.
9. Internally Limited of TJ refers to TOTP
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
TA
Operating Ambient Temperature
-40
+105
°C
© 2009 Fairchild Semiconductor Corporation
FSBH0270 • Rev. 2, Feb-2020
www.fairchildsemi.com
5
Electrical Characteristics
VDD=15V and TA=25°C unless otherwise specified.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
SenseFET Section(10)
Drain-Source
Breakdown Voltage
BVDSS
FSBH0x70/A
FSBH0x70/A
VDS = 700V, VGS = 0V
700
V
VDS = 700V, VGS = 0V
50
Zero-Gate-Voltage
Drain Current
IDSS
μA
VDS = 560V, VGS = 0V,
TC = 125°C
200
FSBH0F70A
FSBH0170/A
FSBH0270/A
FSBH0370
14.00
8.80
6.00
4.00
162
250
550
315
18
19.00
11.00
7.20
4.75
211
325
715
410
24
Drain-Source On-
RDS(ON)
CISS
COSS
CRSS
tD(ON)
tR
V
GS = 10V, ID = 0.5A
Ω
State Resistance(11)
FSBH0F70A
FSBH0170/A
FSBH0270/A
FSBH0370
VGS = 0V, VDS = 25V,
f = 1MHz
Input Capacitance
Output Capacitance
pF
pF
pF
ns
ns
ns
ns
FSBH0F70A
FSBH0170/A
FSBH0270/A
FSBH0370
25
33
VGS = 0V, VDS = 25V,
f = 1MHz
38
50
47
61
FSBH0F70A
FSBH0170/A
FSBH0270/A
FSBH0370
3.8
5.7
10.0
17.0
9.0
15.0
26.0
24.0
29.0
34.0
50.0
33.0
48
Reverse Transfer
Capacitance
VGS = 0V, VDS = 25V,
f = 1MHz
FSBH0F70A
FSBH0170/A
FSBH0270/A
FSBH0370
9.5
12.0
20.0
11.2
19
Turn-On Delay Time
Rise Time
VDS = 350V, ID = 1.0A
FSBH0F70A
FSBH0170/A
FSBH0270/A
FSBH0370
4
18
VDS = 350V, ID = 1.0A
15
40
34
78
FSBH0F70A
FSBH0170/A
FSBH0270/A
FSBH0370
33.0
30.0
55.0
28.2
42
76.0
70.0
120.0
67.0
94
tD(OFF)
Turn-Off Delay Time
VDS = 350V, ID = 1.0A
VDS = 350V, ID = 1.0A
FSBH0F70A
FSBH0170/A
FSBH0270/A
FSBH0370
10
30
tF
Fall Time
25
60
32
74
Continued on the following page…
© 2009 Fairchild Semiconductor Corporation
FSBH0270 • Rev. 2, Feb-2020
www.fairchildsemi.com
6
Electrical Characteristics (Continued)
VDD=15V and TA=25°C unless otherwise specified.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
Control Section
VDD Section
VDD-ON
Start Threshold Voltage
11
7
12
8
13
9
V
V
VDD-OFF
Minimum Operating Voltage
FSBH0170
FSBH0270
FSBH0370
V
DD-ON – 0.16V
30
IDD-ST
Startup Current
µA
FSBH0F70A
FSBH0170A
FSBH0270A
VDD-ON – 0.16V
240
320
400
IDD-OP
IDD-ZDC
IDD-OLP
VTH-OLP
VDD-OVP
Operating Supply Current
Operating Current for VFB<VFB-ZDC
Internal Sink Current
VDD = 15V, VFB = 3V
VDD = 12V, VFB = 1.6V
VTH-OLP+0.1V
3.0
1.5
30
5
3.5
2.5
70
6
4.0
3.5
90
7
mA
mA
µA
V
IDD-OLP Off Voltage
VDD Over-Voltage Protection
27
28
29
V
VDD Over-Voltage Protection
Debounce Time
tD-VDD-OVP
75
130
200
µs
HV Section
HV 120VDC
,
IHV
Maximum Current Drawn from HV Pin
Leakage Current after Startup
5.0
20
mA
µA
1.5
3.5
1
VDD = 0V with 10µF
HV = 700V,
DD = VDD-OFF+1V
IHV-LC
V
Oscillator Section
fOSC
fOSC-G
DMAX
fDV
Frequency in Nominal Mode
94
14
100
18
106
22
kHz
kHz
%
Center Frequency
Green-Mode Frequency
Maximum Duty Cycle
85
Frequency Variation vs. VDD Deviation VDD = 11V to 22V
5
5
%
Frequency Variation vs. Temperature
TA = -25 to 85°C
fDT
%
Deviation(10)
VIN Section (FSBH0170, FSBH0270, FSBH0370)
VIN-ON
PWM Turn-On Threshold Voltage
PWM Turn-Off Threshold Voltage
1.08
1.13
1.18
V
V
VIN-ON
0.48
–
VIN-ON
0.54
500
–
VIN-ON
0.60
–
VIN-OFF
tIN-OFF
VIN-H
tIN-H
PWM Turn-Off Debounce Time
Pull-HIGH Latch Trigger Level
Pull-HIGH Latch Debounce Time
ms
V
4.4
0.2
4.7
100
0.3
5.0
0.4
µs
Pull-LOW Auto-Recovery Trigger
Level
VIN-L
V
Feedback Input Section
FB Voltage to Current-Sense
Attenuation
AV
1/4.5
4
1/4.0
1/3.5
7
V/V
ZFB
Input Impedance
kΩ
Continued on the following page…
© 2009 Fairchild Semiconductor Corporation
FSBH0270 • Rev. 2, Feb-2020
www.fairchildsemi.com
7
Electrical Characteristics (Continued)
VDD=15V and TA=25°C unless otherwise specified.
Symbol
VFB-OPEN
VFB-N
Parameter
Output High Voltage
Condition
FB Pin Open
Min.
5.5
Typ.
Max.
Unit
V
Green-Mode Entry FB Voltage
Green-Mode Ending FB Voltage
Zero Duty Cycle FB Voltage
2.3
2.5
2.0
1.6
5.4
4.6
56
2.7
2.1
V
VFB-G
1.9
V
VFB-ZDC
V
FSBH0F70A
FSBH0x70/A
5.2
4.4
50
5.6
4.8
59
V
FB Open-Loop
Trigger Level
VFB-OLP
V
tD-OLP
FB Open-Loop Protection Delay
ms
Current-Sense Section(14)
FSBH0F70A
FSBH0170/A
FSBH0270/A
FSBH0370
VIN Open
0.63
0.70
0.90
1.10
4.5
0.73
0.80
1.00
1.20
5.0
0.83
0.90
1.10
1.30
5.5
VIN = 1.2V / VIN Open
VIN = 1.2V / VIN Open
VIN = 1.2V
ILIM
Peak Current Limit
A
tSS
Constant Power Limit (FSBH0170, FSBH0270, FSBH0370)
Period During Soft-Start Time(10)
ms
VLMT1
VLMT2
Threshold Voltage 1 for Current Limit
Threshold Voltage 2 for Current Limit
V
IN = 1.2V
0.73
0.56
0.80
0.63
0.87
0.70
V
V
VIN = 3.6V
Current Limit (FSBH0F70A, FSBH0170A, FSBH0270A)
FSBH0F70A
0.97
0.77
1.00
0.80
1.03
0.83
V
V
VLMT
Threshold Voltage for Current Limit
FSBH0170A/0270A
Over-Temperature Protection Section (OTP)
TOTP
Protection Junction Temperature(10, 12)
Restart Junction Temperature(10, 13)
+135
+142
+150
°C
°C
TRESTART
TOTP-25
Notes:
10. These parameters, although guaranteed, are not 100% tested in production.
11. Pulse test: pulse width ≤ 300ìs, duty ≤ 2%.
12. When activated, the output is disabled and the latch is turned off.
13. The threshold temperature for enabling the output again and resetting the latch after over-temperature
protection has been activated.
14. These parameters, although guaranteed, are tested in wafer process.
PWM Frequency
fOSC
fOSC-G
V
FB-ZDC VFB-G
VFB-N
VFB
Figure 5. VFB vs. PWM Frequency
© 2009 Fairchild Semiconductor Corporation
FSBH0270 • Rev. 2, Feb-2020
www.fairchildsemi.com
8
Typical Characteristics (Continued)
14
12
10
8
3.02
3.00
2.98
2.96
2.94
2.92
2.90
2.88
2.86
6
4
2
0
-40
-25 -10
5
20
35
50
65
80
95
95
95
110 125
110 125
110 125
-40 -25 -10
5
20
35
50
65
80
95 110 125
Temperature(°C)
Temperature(°C)
Figure 6. IDD-ST vs. Temperature
Figure 7. IDD-OP vs. Temperature
12.4
8.3
12.2
12.0
11.8
11.6
11.4
11.2
8.2
8.1
8.0
7.9
7.8
7.7
-40 -25 -10
5
20
35
50
65
80
-40
-25
-10
5
20
35
50
65
80
95
110 125
Temperature(°C)
Temperature(°C)
Figure 8. VDD-ON vs. Temperature
Figure 9. VDD-OFF vs. Temperature
6.6
6.4
6.2
6.0
5.8
5.6
5.4
5.2
5.0
28.42
28.41
28.40
28.39
28.38
28.37
28.36
28.35
-40
-25 -10
5
20
35
50
65
80
-40 -25 -10
5
20
35
50
65
80
95
110 125
Temperature(°C)
Temperature(°C)
Figure 10. VTH-OLP vs. Temperature
Figure 11. VDD-OVP vs. Temperature
4.0
3.5
3.0
2.5
2.0
1.5
1.0
7
6
5
4
3
2
1
0
-40 -25
-10
5
20
35
50
65
80
95
110 125
-40
-25
-10
5
20
35
50
65
80
95
110 125
Temperature(°C)
Temperature(°C)
Figure 12. IHV vs. Temperature
Figure 13. IHV-LC vs. Temperature
© 2009 Fairchild Semiconductor Corporation
FSBH0270 • Rev. 2, Feb-2020
www.fairchildsemi.com
9
Typical Characteristics (Continued)
101.5
101.0
100.5
100.0
99.5
19.2
19.1
19.0
18.9
18.8
18.7
18.6
99.0
98.5
98.0
97.5
-40 -25 -10
5
20
35
50
65
80
95
110 125
-40
-25 -10
5
20
35
50
65
80
95
110 125
Temperature(°C)
Temperature(°C)
Figure 14. fOSC vs. Temperature
Figure 15. fOSC-G vs. Temperature
0.64
0.63
0.62
0.61
0.60
0.59
0.58
1.17
1.16
1.15
1.14
1.13
1.12
1.11
-40
-25 -10
5
20
35
50
65
80
95
110 125
110 125
110 125
-40
-25 -10
5
20
35
50
65
80
95
110 125
110 125
110 125
Temperature(°C)
Temperature(°C)
Figure 16. VIN-OFF vs. Temperature
Figure 17. VIN-ON vs. Temperature
4.63
4.62
4.61
4.60
4.59
4.58
4.57
0.34
0.33
0.32
0.31
0.30
0.29
0.28
-40
-25 -10
5
20
35
50
65
80
95
-40
-25 -10
5
20
35
50
65
80
95
Temperature(°C)
Temperature(°C)
Figure 18. VIN-H vs. Temperature
Figure 19. VIN-L vs. Temperature
4.75
4.70
4.65
4.60
4.55
4.50
4.45
4.40
4.35
2.60
2.55
2.50
2.45
2.40
2.35
2.30
-40
-25 -10
5
20
35
50
65
80
95
-40 -25
-10
5
20
35
50
65
80
95
Temperature(°C)
Temperature(°C)
Figure 20. VFB-OLP vs. Temperature
Figure 21. VFB-N vs. Temperature
© 2009 Fairchild Semiconductor Corporation
FSBH0270 • Rev. 2, Feb-2020
www.fairchildsemi.com
10
Typical Characteristics (Continued)
2.20
2.15
2.10
2.05
2.00
1.95
1.90
1.85
1.80
1.800
1.700
1.600
1.500
1.400
1.300
1.200
-40
-25 -10
5
20
35
50
65
80
95
110 125
-40 -25 -10
5
20
35
50
65
80
95
110 125
Temperature(°C)
Temperature(°C)
Figure 22. VFB-G vs. Temperature
Figure 23. VFB-ZDC vs. Temperature
2.56
2.54
2.52
2.50
2.48
2.46
2.44
2.42
55.0
54.5
54.0
53.5
53.0
52.5
52.0
51.5
-40
-25 -10
5
20
35
50
65
80
95
110 125
-40
-25 -10
5
20
35
50
65
80
95
110 125
Temperature(°C)
Temperature(°C)
Figure 24. IDD-ZDC vs. Temperature
Figure 25. tD-OLP vs. Temperature
© 2009 Fairchild Semiconductor Corporation
FSBH0270 • Rev. 2, Feb-2020
www.fairchildsemi.com
11
Functional Description
Startup Operation
Brown-In/Out Function
The HV pin is connected to bulk voltage through an
external resistor, RHV, as shown in Figure 26. When AC
voltage is applied to power system, an internal HV
startup circuit provides a high current (around 3.5mA) to
charge an external VDD capacitor until VDD voltage
exceeds the turn-on threshold voltage (VDD-ON). For
better power consumption, the HV startup circuit shuts
down during normal operation. The external VDD
capacitor and auxiliary winding maintain the VDD voltage
and provide operating current to controller.
FSBH0x70 has a built-in internal brown-in/out protection
comparator monitoring voltage of VIN pin. Figure 28
shows a resistive divider with low-pass filtering for line-
voltage detection on the VIN pin.
Figure 28. Brown-In/Out Function on VIN Pin
Once the VIN pin voltage is lower than 0.6V and lasts
for 500ms, the PWM gate is disabled to protect the
system from over current. FSBH0x70 starts up as VIN
increases above 1.1V. Because the divider resistors of
the VIN pin are connected behind the bridge, the ratio
calculation for brownout in PFC and non-PFC system
are different, as shown in Figure 29. The formulas are
provided in the following equations:
Figure 26. Startup Circuit
Slope Compensation
The FSBH-series is designed for flyback power
converters. The peak-current-mode control is used to
optimize system performance. Slope compensation is
added to reduce current loop gain and improve power
system stability. The FSBH-series has
synchronized, positive slope for each switching cycle.
Brownout with PFC:
RC
2
⋅ 2VAC _OUT
⋅
= 0.6
(1)
(2)
(3)
RA + RB + RC
π
a built-in,
Brownout with non-PFC:
RC
Soft-Start
⋅ 2VAC _OUT = 0.6
RA + RB + RC
The FSBH-series has an internal soft-start circuit that
reduces the SenseFET switching current during power
system startup. The characteristic curve of soft-start
time versus VLMT level is shown in Figure 27. The VLMT
level slopes up like a six-step staircase. In doing so,
power system can smoothly build up the rated output
voltage and effectively reduce voltage stress on the
PWM switch and output diode.
Brown-in level is determined by:
1.1 RA + RB + RC
VAC _IN
=
⋅
RC
2
Figure 27. Soft-Start Function
Figure 29. VIN Level According to PFC Operation
© 2009 Fairchild Semiconductor Corporation
FSBH0270 • Rev. 2, Feb-2020
www.fairchildsemi.com
12
Brown-In Function of FSBH0x70A
H/L Line Over-Power Compensation
The VIN pin functions are disabled from FSBH0x70A,
but FSBH0x70A has brown-in protection in the VDD pin.
There is a discharge current internal from VDD to ground
during startup. The HV source current must be larger
than IDD-ST to charge the capacitor of VDD. Therefore, the
brown-in level can be determined by RHV according to
the equation:
To limit the output power of the converter constantly,
high/low line over-power compensation is included.
Sensing the converter input voltage through the VIN pin,
the high/low line compensation function generates a
relative peak-current-limit threshold voltage for constant
power control, as shown in Figure 32.
2VAC −12
IDD−ST
RHV
=
(4)
Green-Mode Operation
The FSBH-series uses feedback voltage (VFB) as an
indicator of the output load and modulates the PWM
frequency, as shown in Figure 30, such that the
switching frequency decreases as load decreases. In
heavy load conditions, the switching frequency is
100kHz. Once VFB decreases below VFB-N (2.5V), the
PWM frequency starts to linearly decrease from 100kHz
to 18kHz for reducing switching losses. As VFB
decreases below VFB-G (2.0V), the switching frequency is
fixed at 18kHz and FSBH-series enters “deep” green
mode to reduce the standby power consumption.
Figure 32. Constant Power Control
Protections
The FSBH-series provides full protection functions to
prevent the power supply and the load from being
damaged. The protection features include:
Latch/Auto-Recovery Function
Besides the brownout protection and high/low line over-
power compensation, the FSBH0170/0270/0370 has
additional protections via the VIN pin, such as pull-
HIGH latch and pull-LOW auto-recovery that depends
on the application. As shown in Figure 33, VIN level is
higher than 4.7V, FSBH-series is latched until the VDD is
discharged. FSBH-series is auto-recovery when the VIN
level is lower than 0.3V.
Figure 30. PWM Frequency
As VFB decreases below VFB-ZDC (1.6V), FSBH-series
enters into burst-mode operation. When VFB drops
below VFB-ZDC, FSBH-series stops switching and the
output voltage starts to drop, which causes the
feedback voltage to rise. Once VFB rises above VFB-ZDC
,
switching resumes. Burst mode alternately enables and
disables switching, thereby reducing switching loss to
improve power saving, as shown in Figure 31.
VO
Figure 33. VIN Pin Function
Open-Loop / Overload Protection (OLP)
VFB
When the upper branch of the voltage divider for the
shunt regulator (KA431 shown) is broken, as shown in
Figure 34, or over current or output short occurs, there
is no current flowing through the opto-coupler transistor,
which pulls the feedback voltage up to 6V.
VFB.ZDC
(1.6V)
IDrain
When feedback voltage is above 4.6V for longer than
56ms, OLP is triggered. This protection is also triggered
when the SMPS output drops below the nominal value
longer than 56ms due to the overload condition.
Switching
Disabled
Switching
Disabled
Figure 31. Burst-Mode Operation
© 2009 Fairchild Semiconductor Corporation
FSBH0270 • Rev. 2, Feb-2020
www.fairchildsemi.com
13
6V
VDD Over-Voltage Protection (OVP)
VDD over-voltage protection prevents IC damage caused
by over voltage on the VDD pin. The OVP is triggered
when VDD voltage reaches 28V. Debounce time (typically
130µs) prevents false trigger by switching noise.
VFB
Vo
PWM
3R
R
Over-Temperature Protection (OTP)
The SenseFET and the control IC are integrated,
making it easier to detect the temperature of the
KA431
SenseFET.
When
the
temperature
exceeds
approximately 142°C, thermal shutdown is activated.
56ms
OLP
Feedback Open
Loop
4.6V
Figure 34. OLP Operation
© 2009 Fairchild Semiconductor Corporation
FSBH0270 • Rev. 2, Feb-2020
www.fairchildsemi.com
14
Physical Dimensions
9.83
9.00
6.67
6.096
8.255
7.61
3.683
3.20
7.62
5.08 MAX
0.33 MIN
3.60
3.00
(0.56)
2.54
0.356
0.20
0.56
0.355
9.957
7.87
1.65
1.27
7.62
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BA
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSIONS AND TOLERANC
ASME Y14.5M-1994
ES PER
E) DRAWING FILENAME AND REVSION: MKT-N08FREV2.
Figure 35. 8-Pin Dual In-Line Package (DIP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
© 2009 Fairchild Semiconductor Corporation
FSBH0270 • Rev. 2, Feb-2020
www.fairchildsemi.com
15
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