FSEZ1317MY [ONSEMI]
PSR 反激 PWM 控制器，集成了 MOSFET，用于 LED 照明;
| 型号： | FSEZ1317MY |
| 厂家： | 
ONSEMI |
| 描述： | PSR 反激 PWM 控制器，集成了 MOSFET，用于 LED 照明 控制器 |
| 文件： | 总19页 (文件大小：1347K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON
Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
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FSEZ1317
Primary-Side-Regulation PWM with POWER MOSFET
Integrated
Features
Description
This third-generation Primary-Side-Regulation (PSR)
and highly integrated PWM controller provides several
features to enhance the performance of low-power
.
.
.
.
Low Standby Power Under 30mW
High-Voltage Startup
flyback
converters.
The
proprietary
topology,
Fewest External Component Counts
TRUECURRENT™, of FSEZ1317 enables precise CC
regulation and simplified circuit design for battery-
charger applications. A low-cost, smaller, and lighter
charger results, as compared to a conventional design
or a linear transformer.
Constant-Voltage (CV) and Constant-Current (CC)
Control without Secondary-Feedback Circuitry
.
.
Green-Mode: Linearly Decreasing PWM Frequency
Fixed PWM Frequency at 50kHz with Frequency
Hopping to Solve EMI Problem
To minimize standby power consumption, the
proprietary green mode provides off-time modulation to
linearly decrease PWM frequency under light-load
conditions. Green mode assists the power supply in
meeting power conservation requirements.
.
.
.
.
.
.
.
Cable Compensation in CV Mode
Peak-Current-Mode Control in CV Mode
Cycle-by-Cycle Current Limiting
By using the FSEZ1317, a charger can be implemented
with few external components and minimized cost. A
typical output CV/CC characteristic envelope is shown
in Figure 1.
VDD Over-Voltage Protection with Auto Restart
VDD Under-Voltage Lockout (UVLO)
Gate Output Maximum Voltage Clamped at 15V
Fixed Over-Temperature Protection with
Auto Restart
.
Available in the 7-Lead SOP and DIP Packages
Applications
.
Battery chargers for cellular phones, cordless
phones, PDA, digital cameras, power tools, etc.
.
Replaces linear transformers and RCC SMPS
Figure 1. Typical Output V-I Characteristic
Ordering Information
Operating
Temperature Range
Packing
Part Number
Package
Method
FSEZ1317MY
FSEZ1317NY
-40°C to +105°C
7-Lead, Small Outline Package (SOP-7)
7-Lead, Dual Inline Package (DIP-7)
Tape & Reel
Tube
-40°C to +105°C
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSEZ1317 • Rev. 2, Feb-2020
Application Diagram
Csn2
Rsn
L1
T1
DF
Rsn2
Csn
DC
Output
D1
D4
Rd
CO1 CO2
RF
Rsn1
Dsn
AC
Input
C1
C2
DFa
R1
R2
CVDD
D2
D3
CVS
VS
2
7
VDD
HV
5
8
1
4
DRAIN
CS
COMR
3
GND
RSENSE
CCR
Figure 2. Typical Application
Internal Block Diagram
Figure 3. Functional Block Diagram
© 2010 Fairchild Semiconductor Corporation
FSEZ1317 • Rev. 2, Feb-2020
www.fairchildsemi.com
2
Marking Information
F: Fairchild Logo
Z: Plant Code
X: 1-Digit Year Code
Y: 1-Digit Week Code
TT: 2-Digit Die Run Code
T: Package Type (M=SOP, N=DIP)
P: Y=Green Package
M: Manufacture Flow Code
Figure 4. Top Mark
Pin Configuration
Figure 5. Pin Configuration
Pin Definitions
Pin #
Name Description
Current Sense. This pin connects a current-sense resistor, to detect the MOSFET current for
peak-current-mode control in CV mode, and provides the output-current regulation in CC mode.
1
CS
Power Supply. IC operating current and MOSFET driving current are supplied using this pin.
This pin is connected to an external VDD capacitor of typically 10µF. The threshold voltages for
startup and turn-off are 16V and 5V, respectively. The operating current is lower than 5mA.
2
VDD
3
4
GND
Ground
Cable Compensation. This pin connects a 1µF capacitor between the COMR and GND pins
for compensation voltage drop due to output cable loss in CV mode.
COMR
Voltage Sense. This pin detects the output voltage information and discharge time based on
voltage of auxiliary winding.
5
VS
7
8
HV
High Voltage. This pin connects to bulk capacitor for high-voltage startup.
DRAIN
Driver Output. Power MOSFET drain. This pin is the high-voltage power MOSFET drain.
© 2010 Fairchild Semiconductor Corporation
FSEZ1317 • Rev. 2, Feb-2020
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Units
VHV
VVDD
VVS
HV Pin Input Voltage
DC Supply Voltage(1,2)
VS Pin Input Voltage
CS Pin Input Voltage
500
30
V
V
-0.3
-0.3
-0.3
-0.3
7.0
7.0
7.0
7.0
700
1
V
VCS
V
VCOMV
VCOMI
VDS
Voltage Error Amplifier Output Voltage
Current Error Amplifier Output Voltage
Drain-Source Voltage
V
V
V
TA=25°C
Continuous Drain Current
TA=100°C
A
ID
0.6
4
A
IDM
EAS
IAR
Pulsed Drain Current
A
Single Pulse Avalanche Energy
Avalanche Current
50
mJ
A
1
Power Dissipation (TA＜50°C)
PD
660
150
95
mW
°C/W
°C/W
°C/W
SOP
DIP
θJA
Thermal Resistance (Junction-to-Air)
Thermal Resistance (Junction-to-Case)
39
SOP
ΨJT
25
DIP
°C/W
°C
TJ
TSTG
TL
Operating Junction Temperature
Storage Temperature Range
-40
-55
+150
+150
+260
°C
Lead Temperature (Reflow, 3 Cycles)
°C
Human Body Model,
JEDEC-JESD22_A114
(All Pins Except HV Pin)
5000
2000
Electrostatic Discharge
Capability
ESD
V
Charged Device Model,
JEDEC-JESD22_C101
(All Pins Except HV Pin)
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
2. All voltage values, except differential voltages, are given with respect to the GND pin.
3. ESD ratings including HV pin: HBM=1000V, CDM=1000V.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Max.
Units
TA
Operating Ambient Temperature
-40
+105
°C
© 2010 Fairchild Semiconductor Corporation
FSEZ1317 • Rev. 2, Feb-2020
www.fairchildsemi.com
4
Electrical Characteristics
Unless otherwise specified, VDD=15V and TA=25℃.
Symbol
VDD Section
VOP
Parameter
Conditions Min. Typ. Max. Units
Continuously Operating Voltage
Turn-On Threshold Voltage
Turn-Off Threshold Voltage
Operating Current
23
17
V
V
VDD-ON
15
16
5.0
2.5
VDD-OFF
IDD-OP
IDD-GREEN
VDD-OVP
4.5
5.5
5.0
V
mA
Green-Mode Operating Supply Current
VDD Over-Voltage-Protection Level (OVP)
0.95
24
1.20
25
mA
V
23
1.5
50
VDD-OVP-HYS Hysteresis Voltage for VDD OVP
2.0
200
2.5
300
V
tD-VDDOVP
VDD Over-Voltage-Protection Debounce Time
µs
HV Startup Current Source Section
VHV-MIN
IHV
Minimum Startup Voltage on HV Pin
50
V
Supply Current Drawn from HV Pin
VDC=100V
HV=500V,
1.5
3.0
mA
IHV-LC
Leakage Current after Startup
V
DD= VDD-
0.96
3.00
µA
OFF+1V
Oscillator Section
Center Frequency
47
50
±2.0
370
13
53
fOSC
Frequency
kHz
Frequency Hopping Range
±1.5
±2.5
fOSC-N-MIN
Minimum Frequency at No-Load
Hz
kHz
%
fOSC-CM-MIN Minimum Frequency at CCM
fDV
Frequency Variation vs. VDD Deviation
VDD=10~25V,
1
2
TA=-40°C to
105°C
fDT
Frequency Variation vs. Temperature Deviation
15
%
Voltage-Sense Section
Itc
IC Bias Current
10
µA
V
VBIAS-COMV Adaptive Bias Voltage Dominated by VCOMV
RVS=20kΩ
1.4
Current-Sense Section
tPD
tMIN-N
VTH
Propagation Delay to GATE Output
Minimum On Time at No-Load
90
850
0.8
200
ns
ns
V
700
1050
Threshold Voltage for Current Limit
Voltage-Error-Amplifier Section
VVR
VN
Reference Voltage
2.475 2.500 2.525
V
V
V
Green-Mode Starting Voltage on EA_V
Green-Mode Ending Voltage on EA_V
fOSC-2kHz
fOSC=1kHz
2.5
0.4
VG
Current-Error-Amplifier Section
VIR Reference Voltage
Cable Compensation Section
2.475 2.500 2.525
V
VCOMR
COMR Pin for Cable Compensation
0.75
V
Continued on the following page…
© 2010 Fairchild Semiconductor Corporation
FSEZ1317 • Rev. 2, Feb-2020
www.fairchildsemi.com
5
Electrical Characteristics (Continued)
Unless otherwise specified, VDD=15V and TA=25℃.
Symbol
Parameter
Conditions Min. Typ. Max. Units
Internal MOSFET Section(4)
DCYMAX
Maximum Duty Cycle
70
75
80
%
V
ID=250μA,
GS=0V
BVDSS
Drain-Source Breakdown Voltage
700
V
ID=250μA,
Referenced to
TA=25°C
∆BVDSS/∆TJ Breakdown Voltage Temperature Coefficient
0.53
13
V/°C
ID=0.5A,
RDS(ON)
Static Drain-Source On-Resistance
16
1
Ω
A
VGS=10V
Maximum Continuous Drain-Source Diode Forward
Current
IS
VDS=700V,
TA=25°C
10
100
µA
µA
IDSS
Drain-Source Leakage Current
VDS=560V,
TA=100°C
VDS=350V,
ID=1A,
tD-ON
Turn-On Delay Time
Turn-Off Delay Time
10
20
30
50
ns
ns
RG=25Ω(5)
tD-OFF
VGS=0V,
CISS
Input Capacitance
V
DS=25V,
175
23
200
25
pF
pF
fS=1MHz
COSS
Output Capacitance
Over-Temperature-Protection Section
TOTP
Threshold Temperature for OTP(6)
Notes:
+130 +140 +150
°C
4. These parameters, although guaranteed, are not 100% tested in production.
5. Pulse test: pulsewidth ≦ 300µs, duty cycle ≦ 2%.
6. When the Over-temperature protection is activated, the power system enter auto restart mode and output is
disabled.
© 2010 Fairchild Semiconductor Corporation
FSEZ1317 • Rev. 2, Feb-2020
www.fairchildsemi.com
6
Typical Performance Characteristics
17
16.6
16.2
15.8
15.4
15
5.5
5.3
5.1
4.9
4.7
4.5
-40
-30
-15
0
25
50
75
85
100
125
125
125
-40
-30
-15
0
25
50
75
85
100
125
Temperature (ºC)
Temperature (ºC)
Figure 6. Turn-On Threshold Voltage (VDD-ON
)
Figure 7. Turn-Off Threshold Voltage (VDD-OFF
)
vs. Temperature
vs. Temperature
5
4.2
3.4
2.6
1.8
1
54
52
50
48
46
44
-40
-30
-15
0
25
50
75
85
100
-40
-30
-15
0
25
50
75
85
100
125
Temperature (ºC)
Temperature (ºC)
Figure 8. Operating Current (IDD-OP
vs. Temperature
)
Figure 9. Center Frequency (fOSC) vs. Temperature
2.525
2.515
2.505
2.495
2.485
2.475
1.2
1.12
1.04
0.96
0.88
0.8
-40
-30
-15
0
25
50
75
85
100
-40
-30
-15
0
25
50
75
85
100
125
Temperature (ºC)
Temperature (ºC)
Figure 10. Reference Voltage (VVR) vs. Temperature
Figure 11. Green Mode Operating Supply Current
(IDD-GREEN) vs. Temperature
© 2010 Fairchild Semiconductor Corporation
FSEZ1317 • Rev. 2, Feb-2020
www.fairchildsemi.com
7
Typical Performance Characteristics (Continued)
450
15
420
390
360
330
300
14.2
13.4
12.6
11.8
11
-40
-30
-15
0
25
50
75
85
100
125
-40
-30
-15
0
25
50
75
85
100
125
Temperature (ºC)
Temperature (ºC)
Figure 12. Minimum Frequency at No Load
(fOSC-N-MIN) vs. Temperature
Figure 13. Minimum Frequency at CCM (fOSC-CM-MIN
)
vs. Temperature
3
1050
980
910
840
770
700
2.4
1.8
1.2
0.6
0
-40
-30
-15
0
25
50
75
85
100
125
-40
-30
-15
0
25
50
75
85
100
125
Temperature (ºC)
Temperature (ºC)
Figure 14. Supply Current Drawn from HV Pin (IHV
vs. Temperature
)
Figure 15. Minimum On Time at No Load (tMIN-N
)
vs. Temperature
2.55
2.52
2.49
2.46
2.43
2.4
0.65
0.56
0.47
0.38
0.29
0.2
-40
-30
-15
0
25
50
75
85
100
125
-40
-30
-15
0
25
50
75
85
100
125
Temperature (ºC)
Temperature (ºC)
Figure 16. Green Mode Starting Voltage on EA_V
(VN) vs. Temperature
Figure 17. Green Mode Ending Voltage on EA_V (VG)
vs. Temperature
© 2010 Fairchild Semiconductor Corporation
FSEZ1317 • Rev. 2, Feb-2020
www.fairchildsemi.com
8
Typical Performance Characteristics (Continued)
1.5
11
10.5
1.42
1.34
1.26
1.18
1.1
10
9.5
9
8.5
8
-40
-30
-15
0
25
50
75
85
100
125
-40
-30
-15
0
25
50
75
85
100
125
Temperature (ºC)
Temperature (ºC)
Figure 18. IC Bias Current (Itc) vs. Temperature
Figure 19. Adaptive Bias Voltage Dominated by VCOMV
(VBIAS-COMV) vs. Temperature
0.82
0.815
0.81
3
2.5
2
0.805
0.8
1.5
1
0.795
0.79
0.5
0
-40
-30
-15
0
25
50
75
85
100
125
-40
-30
-15
0
25
50
75
85
100
125
Temperature (ºC)
Temperature (ºC)
Figure 20. Threshold Voltage for Current Limit (VTH
)
Figure 21. Leakage Current after Startup (IHV-LC
)
vs. Temperature
vs. Temperature
80
78
76
74
72
70
0.82
0.8
0.78
0.76
0.74
0.72
0.7
-40
-30
-15
0
25
50
75
85
100
125
-40
-30
-15
0
25
50
75
85
100
125
Temperature (ºC)
Temperature (ºC)
Figure 22. Variation Test Voltage on COMR Pin for
Cable Compensation (VCOMR) vs. Temperature
Figure 23. Maximum Duty Cycle (DCYMAX
vs. Temperature
)
© 2010 Fairchild Semiconductor Corporation
FSEZ1317 • Rev. 2, Feb-2020
www.fairchildsemi.com
9
Functional Description
Figure 24 shows the basic circuit diagram of primary-
side regulated flyback converter, with typical waveforms
shown in Figure 25. Generally, discontinuous
conduction mode (DCM) operation is preferred for
primary-side regulation because it allows better output
regulation. The operation principles of DCM flyback
converter are as follows:
constant current regulation mode, VCOMI determines the
duty cycle while VCOMV is saturated to HIGH.
ID
IO
Np:Ns
D
+
+ VF
-
+
VDL
L
O
A
D
Lm
During the MOSFET on time (tON), input voltage (VDL) is
applied across the primary-side inductor (Lm). Then
MOSFET current (Ids) increases linearly from zero to the
peak value (Ipk). During this time, the energy is drawn
from the input and stored in the inductor.
VO
-
V
AC
-
Ids
When the MOSFET is turned off, the energy stored in
the inductor forces the rectifier diode (D) to be turned
on. While the diode is conducting, the output voltage
(Vo), together with diode forward-voltage drop (VF), is
applied across the secondary-side inductor (LmNs2/
EA_I
VCOMI
I
CS
O
Estimator
RCS
Ref
t DIS
Detector
PWM
Control
V
2
S
Np ) and the diode current (ID) decreases linearly from
NA
V
DD
VCOMV
the peak value (IpkNp/Ns) to zero. At the end of inductor
current discharge time (tDIS), all the energy stored in the
inductor has been delivered to the output.
V
O
Estimator
RS1
RS2
+
Vw
-
EA_V
Ref
Primary-Side Regulation
Controller
When the diode current reaches zero, the transformer
auxiliary winding voltage (Vw) begins to oscillate by the
resonance between the primary-side inductor (Lm) and
the effective capacitor loaded across the MOSFET.
Figure 24. Simplified PSR Flyback Converter Circuit
During the inductor current discharge time, the sum of
output voltage and diode forward-voltage drop is
reflected to the auxiliary winding side as (Vo+VF)
Na/Ns. Since the diode forward-voltage drop decreases
as current decreases, the auxiliary winding voltage
reflects the output voltage best at the end of diode
conduction time where the diode current diminishes to
zero. Thus, by sampling the winding voltage at the end
of the diode conduction time, the output voltage
information can be obtained. The internal error amplifier
for output voltage regulation (EA_V) compares the
sampled voltage with internal precise reference to
generate error voltage (VCOMV), which determines the
duty cycle of the MOSFET in CV mode.
Ipk
NP
Ipk
NS
ID.avg Io
NA
NS
Meanwhile, the output current can be estimated using
the peak drain current and inductor current discharge
time because output current is same as the average of
the diode current in steady state.
VF
NA
NS
VO
The output current estimator picks up the peak value of
the drain current with a peak detection circuit and
calculates the output current using the inductor
discharge time (tDIS) and switching period (ts). This
output information is compared with internal precise
reference to generate error voltage (VCOMI), which
determines the duty cycle of the MOSFET in CC mode.
With
Fairchild’s
innovative
technique
Figure 25. Key Waveforms of DCM Flyback
Converter
TRUECURRENT™, constant current (CC) output can
be precisely controlled.
Among the two error voltages, VCOMV and VCOMI, the
smaller one determines the duty cycle. Therefore, during
constant voltage regulation mode, VCOMV determines the
duty cycle while VCOMI is saturated to HIGH. During
© 2010 Fairchild Semiconductor Corporation
FSEZ1317 • Rev. 2, Feb-2020
www.fairchildsemi.com
10
Cable Voltage Drop Compensation
In cellular phone charger applications, the battery is
located at the end of cable, which typically causes
several percentage of voltage drop on the battery
voltage. FSEZ1317 has a built-in cable voltage drop
compensation that provides a constant output voltage at
the end of the cable over the entire load range in CV
mode. As load increases, the voltage drop across the
cable is compensated by increasing the reference
voltage of the voltage regulation error amplifier.
Operating Current
The FSEZ1317 operating current is as small as 2.5mA,
which results in higher efficiency and reduces the VDD
hold-up capacitance requirement. Once FSEZ1317
enters “deep” green mode, the operating current is
reduced to 0.95mA, assisting the power supply in
meeting power conservation requirements.
Green-Mode Operation
The FSEZ1317 uses voltage regulation error amplifier
output (VCOMV) as an indicator of the output load and
modulates the PWM frequency as shown in Figure 26.
The switching frequency decreases as the load
decreases. In heavy load conditions, the switching
frequency is fixed at 50kHz. Once VCOMV decreases
below 2.5V, the PWM frequency linearly decreases from
50kHz. When FSEZ1317 enters deep green mode, the
PWM frequency is reduced to a minimum frequency of
370Hz, thus gaining power saving to meet international
power conservation requirements.
Figure 27. Frequency Hopping
High-Voltage Startup
Figure 28 shows the HV-startup circuit for FSEZ1317
applications. The HV pin is connected to the line input or
bulk capacitor through
a resistor, RSTART (100kΩ
recommended). During startup status, the internal
startup circuit is enabled. Meanwhile, line input supplies
the current, ISTARTUP, to charge the hold-up capacitor,
CDD, through RSTART. When the VDD voltage reaches
VDD-ON, the internal startup circuit is disabled, blocking
ISTARTUP from flowing into the HV pin. Once the IC turns
on, CDD is the only energy source to supply the IC
consumption current before the PWM starts to switch.
Thus, CDD must be large enough to prevent VDD from
dropping down to VDD-OFF before the power can be
delivered from the auxiliary winding.
VDL
+
Np
RSTART
CDL
-
I
startup
Figure 26. Switching Frequency in Green Mode
AC Line
Frequency Hopping
CDD
NA
EMI reduction is accomplished by frequency hopping,
which spreads the energy over a wider frequency range
than the bandwidth measured by the EMI test
equipment. FSEZ1317 has an internal frequency
hopping circuit that changes the switching frequency
between 47kHz and 53kHz over the period shown in
Figure 27.
FSEZ1317
1
2
3
4
8
7
CS
Drain
HV
VDD
GND
COMR
RCS
RS1
5
VS
Cvs
RS2
Figure 28. HV Startup Circuit
© 2010 Fairchild Semiconductor Corporation
FSEZ1317 • Rev. 2, Feb-2020
www.fairchildsemi.com
11
Over-Temperature Protection (OTP)
The built-in temperature-sensing circuit shuts down
PWM output if the junction temperature exceeds 140°C.
Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally at
16V and 5V, respectively. During startup, the hold-up
capacitor must be charged to 16V through the startup
resistor to enable the FSEZ1317. The hold-up capacitor
continues to supply VDD until power can be delivered
from the auxiliary winding of the main transformer. VDD
is not allowed to drop below 5V during this startup
process. This UVLO hysteresis window ensures that
hold-up capacitor properly supplies VDD during startup.
Pulse-by-pulse Current Limit
When the sensing voltage across the current-sense
resistor exceeds the internal threshold of 0.8V, the
MOSFET is turned off for the remainder of switching
cycle. In normal operation, the pulse-by-pulse current
limit is not triggered since the peak current is limited by
the control loop.
Leading-Edge Blanking (LEB)
Protections
Each time the power MOSFET switches on, a turn-on
spike occurs at the sense resistor. To avoid premature
termination of the switching pulse, a leading-edge
blanking time is built in. During this blanking period,
the current-limit comparator is disabled and cannot
switch off the gate driver. As a result conventional RC
filtering can be omitted.
The FSEZ1317 has several self-protection functions,
such as Over-Voltage Protection (OVP), Over-
Temperature Protection (OTP), and pulse-by-pulse
current limit. All the protections are implemented as
auto-restart mode. Once the abnormal condition occurs,
the switching is terminated and the MOSFET remains
off, causing VDD to drop. When VDD drops to the VDD
turn-off voltage of 5V, internal startup circuit is enabled
again and the supply current drawn from the HV pin
charges the hold-up capacitor. When VDD reaches the
turn-on voltage of 16V, normal operation resumes. In
this manner, the auto-restart alternately enables and
disables the switching of the MOSFET until the
abnormal condition is eliminated (see Figure 29).
Gate Output
The FSEZ1317 output stage is a fast totem-pole gate
driver. Cross conduction has been avoided to minimize
heat dissipation, increase efficiency, and enhance
reliability. The output driver is clamped by an internal
15V Zener diode to protect the power MOSFET
transistors against undesired over-voltage gate signals.
Error Occurs
Power
VDS
Built-In Slope Compensation
Error Removed
On
The sensed voltage across the current-sense resistor is
used for current mode control and pulse-by-pulse
current limiting. Built-in slope compensation improves
stability and prevents sub-harmonic oscillations due to
peak-current mode control. The FSEZ1317 has a
synchronized, positive-slope ramp built-in at each
switching cycle.
VDD
16V
Noise Immunity
Noise from the current sense or the control signal can
cause significant pulsewidth jitter, particularly in
5V
continuous-conduction
mode.
While
slope
compensation helps alleviate these problems, further
precautions should still be taken. Good placement and
layout practices should be followed. Avoiding long PCB
traces and component leads, locating compensation
and filter components near the FSEZ1317, and
increasing the power MOS gate resistance are advised.
Operating Current
2.5mA
Normal
Operation
Abnormal
Situation
Normal
Operation
Figure 29. Auto-Restart Operation
VDD Over-Voltage Protection (OVP)
DD over-voltage protection prevents damage from over-
V
voltage conditions. If the VDD voltage exceeds 24V at
open-loop feedback condition, OVP is triggered and the
PWM switching is disabled. The OVP has a debounce
time (typically 200µs) to prevent false triggering due to
switching noises.
© 2010 Fairchild Semiconductor Corporation
FSEZ1317 • Rev. 2, Feb-2020
www.fairchildsemi.com
12
Typical Application Circuit (Primary-Side Regulated Flyback Charger)
Application
Fairchild Devices
Input Voltage Range
Output
Output DC cable
Cell Phone Charger
FSEZ1317 (SOP-7)
90~265VAC
5V/0.7A (3.5W)
AWG26, 1.8 Meter
Features
High efficiency (>65.5% at full load) meeting EPS 2.0 regulation with enough margin
Low standby (Pin<30mW at no-load condition)
Figure 30. Measured Efficiency
Figure 31. Standby Power
Figure 32. Schematic of Typical Application Circuit
© 2010 Fairchild Semiconductor Corporation
FSEZ1317 • Rev. 2, Feb-2020
www.fairchildsemi.com
13
Typical Application Circuit (Continued)
Transformer Specification
.
.
Core: EE16
Bobbin: EE16
9
7
Secondary
Winding
1st Shield
1
1
Primary
Winding
3
5
4
Auxiliary
Winding
BOBBIN
Figure 33. Transformer Specification
Notes:
7. When W4R’s winding is reversed winding, it must wind one layer.
8. When W2 is winding, it must wind three layers and put one layer of tape after winding the first layer.
Terminal
Insulation
Barrier Tape
No.
Wire
ts
S
F
ts
2
1
0
2
3
3
3
Primary Seconds
W1
4
5
2UEW 0.23*2
15
41
39
37
1.2
9
W2
3
1
2UEW 0.17*1
W3
W4
1
7
-
COPPER SHIELD
TEX-E 0.55*1
9
CORE ROUNDING TAPE
Pin
1－3
1－3
Specification
2.25mH ± 7%
80H ± 5%
Remark
Primary-Side Inductance
100kHz, 1V
Primary-Side Effective Leakage
Short One of the Secondary Windings
© 2010 Fairchild Semiconductor Corporation
FSEZ1317 • Rev. 2, Feb-2020
www.fairchildsemi.com
14
Physical Dimensions
Figure 34. 7-Lead, Small Outline Package (SOP-7)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2010 Fairchild Semiconductor Corporation
FSEZ1317 • Rev. 2, Feb-2020
www.fairchildsemi.com
15
Physical Dimensions
9.40
9.00
7
5
6.60
6.20
1
4
(0.56)
3.60
3.20
7.62
5.08 MAX
0.33
3.60
3.00
0.35
0.20
2.54
0.56
0.36
9.91
7.62
1.62
1.42
7.62
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE COMPLIES TO JEDEC
MS-001, VARIATION BA, EXCEPT FOR
TERMINAL COUNT (7 RATHER THAN 8)
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSIONS AND TOLERANCES PER
ASME Y14.5M-1994
E) DRAWING FILENAME AND REVISION: MKT-NA07BREV2
Figure 35. 7-Lead, Dual-inline Package (DIP-7)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
© 2010 Fairchild Semiconductor Corporation
FSEZ1317 • Rev. 2, Feb-2020
www.fairchildsemi.com
16
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