FSHDMI08MTDX [ONSEMI]
宽带宽差分信号 HDMI 开关;
| 型号： | FSHDMI08MTDX |
| 厂家： | 
ONSEMI |
| 描述： | 宽带宽差分信号 HDMI 开关 开关 光电二极管 商用集成电路 |
| 文件： | 总13页 (文件大小：822K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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August 2009
FSHDMI08 — 低电压, 宽带及带有 DDC 和 CEC 多路传输
器的 HDMI 开关
特性
总述
FSHDMI08是一种宽带开关，用于发送HDMI连接信号，
时钟信号及有关的DDC和CEC控制信号，对于UXGA方
案，本开关的每一个通道均可支持高达1.65Gbps的数据
传输速率。可以应用于包括液晶电视、DVD、机顶盒、笔
记本电脑及带多路数字视频接口的其它设计中。通过
FSHDMI04开关，可实现以低非邻道串扰及优质的断开隔
离（Off-Isolation）性能传输HDMI信号。本性能对于减少
视频应用中有效视频源之间的重影现象非常关键。本开关
宽的带宽使得高速差分信号以最小的附加斜度和相位抖动
通过开关。管脚输出支持HDMI标准A类连接器在PCB上
的设计。
1.65MHz 非相邻通道间的串扰
低信号失真: 在1.65Gbps下只有-1.5dB 的衰减
各通道间地绝缘
快速启动和关闭 (< 6ns)
1.65Gbps 通道传输速率
8kV的 ESD 保护
低 Skew: 差分对间延迟差 <90ps,
差分对内延迟差< 150ps
低功耗 (最大值为1µA )
重要提示:
应用
欲知其它详情，请 analogswitch@fairchildsemi.com.
XGA 和720p DVI 及 HDMI 视频源的选择
订购信息
Package
Description
Eco
Status
订购编号
封装说明
56-引脚，超薄小封装 (TSSOP), JEDEC MO-153, 6.1mm 宽
FSHDMI08MTDX
RoHS
Tape and Reel
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
Primary HDMI
Source
TMDS Channels
Secondary HDMI
Source
Primary Source
DDC &
CEC
Secondary Source
DDC &
Control Channels
CEC
图 1.
单一连接 HDMI 应用
© 2006 Fairchild Semiconductor Corporation
FSHDMI08 Rev. 1.0.4
www.fairchildsemi.com
功能图
1D2+
1D2-
D2+
D2-
1D1+
1D1-
1D0+
D1+
D1-
D0+
1D0-
D0-
1CLK+
1CLK-
CLK+
CLK-
2D2+
2D2-
2D1+
2D1-
2D0+
2D0-
2CLK+
2CLK-
VCC3
/OEDDC
SDDC
VDDC
/OETMDS
STMDS
Control
SCL1
SDA1
CEC1
HPD1
SCL
SDA
CEC
HPD
SCL2
SDA2
DGND
GND
CEC2
HPD2
图 2.
功能图
管脚描述
管脚 #
名称
1Dn+, 1Dn-, 2Dn+, 2Dn-, Dn+, Dn-
描述
TMDS 数据通道
1-4,6,7,11-14,16,17,
47,48,50,51,53,54
8,9,18,19,44,45
24,28,33
22,26,35
23,27,34
21,25,36
29
1CLK+, 1CLK-, 2CLK+, 2CLK-, CLK+, CLK-
TMDS 时钟通道
热插入侦测
HPD1, HPD2, HPD
SCL1, SCL2, SCL
SDA1, SDA2, SDA
CEC1, CEC2, CEC
VDDC
显示时钟通道 (DDC)
显示数据通道 (DDC)
消费电子控制 (CEC)
DDC 供电
20,39,40,55,56
30
VCC3
TMDS 供电
DGND
DDC/CEC 接地
大地
5,10,15,38,43,46,49,52
32,42
GND
STMDS, SDDC
/OETMDS, /OEDDC
选择管脚 (TMDS, DDC)
输出使能 (TMDS, DDC)
31,41
© 2006 Fairchild Semiconductor Corporation
FSHDMI08 Rev. 1.0.4
www.fairchildsemi.com
2
管脚分配
1D2+
1D2-
1
2
56
55
54
53
52
51
50
49
48
47
46
45
VCC3
VCC3
D2+
1D1+
1D1-
3
4
D2-
GND
5
GND
D1+
1D0+
1D0-
6
7
D1-
1CLK+
1CLK-
GND
8
GND
D0+
9
10
D0-
2D2+ 11
12
2D1+ 13
14
GND
CLK+
CLK-
GND
STMDS
/OETMDS
VCC3
VCC3
GND
DGND
CEC
SCL
2D2-
44
43
2D1-
GND 15
42
41
40
39
38
37
16
2D0+
2D0- 17
2CLK+ 18
2CLK- 19
VCC3
CEC1 21
22
20
36
35
34
33
32
31
30
29
SCL1
SDA1 23
24
SDA
HPD1
HPD
SDDC
/OEDDC
DGND
VDDC
CEC2 25
SCL2 26
SDA2 27
28
HPD2
图 3.
管脚
分配图
STMDS,SDDC
/OETMDS, / OEDDC
功能
Don’t’ Care
Logic Level HIGH
Logic Level LOW
所有端口断开 (Hi-Z)
1Dn+/1Dn-=Dn+/Dn-; 1CLK+/ 1CLK-=CLK+/CLK-; HPD1=HPD;
SCL1=SCL; SDA1=SDA; CEC1=CEC
Logic Level LOW
2Dn+/2Dn-=Dn+/Dn-; 2CLK+/ 2CLK-=CLK+/CLK-; HPD2=HPD;
SCL2=SCL; SDA2=SDA; CEC2=CEC
Logic Level HIGH
Logic Level LOW
© 2006 Fairchild Semiconductor Corporation
FSHDMI08 Rev. 1.0.4
www.fairchildsemi.com
3
绝对最大值
超出绝对最大额定值会破坏设备 ,设备会不工作或者说不建议设备在和超过建议的工作条件下被操作。
另外, 过长的暴露在超过建议工作条件下会影响设备的可靠性。这种绝对最大额定值仅仅是极端额定值。
表达符号
VCC3
参数
最小值
最大值
单位
供电电源 – TMDS 通道
供电电源 – 5V DDC
-0.5
-0.5
4.6
6.0
V
V
VDDC
1Dn+, 1Dn-, 2Dn+, 2Dn-, Dn+, Dn-,
1CLK+, 1CLK-, 2CLK+, 2CLK-, CLK+,
CLK-
(1)
VSWTMDS
开关输出/输入电压
开关输入/输出电压
-0.5
-0.5
VCC3 + 0.3
VDDC + 0.3
V
V
(1)
HPD1, HPD2, HPD, SCL1, SCL2, SCL,
SDA1, SDA2, SDA, CEC1, CEC2, CEC
VSWDDC
(1)
(1)
VCNTRLT
VCNTRLD
IIK
控制输入电压
STMDS, /OETMDS
SDDC, /OEDDC
-0.5
-0.5
4.6
6.0
V
V
控制输入电压
输入钳位二极管电流
开关输入/出电流 (续)
储存温度范围
-50
mA
mA
°C
°C
°C
ISW
128
+150
+150
TSTG
TJ
-65
最高结点温度
TL
导线温度(焊接, 10秒)
+260
8.0
I/O接地
kV
kV
人体电流模式 (JEDEC: JESD22-A114)
人体电流模式 (JEDEC: JESD22-C101)
ESD
2.5
2.0
所有管脚
注解
1. 如输入及输出二极管电流额定值均达到时则可能会超出输入及输出负额定值。
推荐工作条件
推荐工作条件表中定义的是实际元件工作的条件。推荐工作条件指定用于保证实现数据表规范的最佳性
能， Fairchild 建议不得超出以上值或设计至最大绝对额定值.
表达符号
参数
最小值
最大值
单位
VCC3
VDDC
TMDS 供电电压 – 3V
DDC 供电电压
3.0
4.3
5.5
V
V
3.0
VCNTRLT
VCNTRLD
VSWTMDS
VSWDDC
TA
控制输入电压 – STMDS, /OETMDS
控制输入电压 – SDDC, /OEDDC
开关输入/出电压对于 HDM I路径
开关输入/出电压对于 DDC 路径
工作温度
0
VCC3
VDDC
VCC3
VDDC
85
V
0
VCC3 – 0.6
0
V
V
V
-40
ºC
ºC/W
热阻 (大气)
80
θJA
© 2006 Fairchild Semiconductor Corporation
FSHDMI08 Rev. 1.0.4
www.fairchildsemi.com
4
DC电气特性
如无其它规定，均为在 25°C 下 VCC3=3.3V, VDDC=5.0V 的典型值.
TA=- 40°C 至 +85°C
表达符号
参数
VCC3 / VDDC (V)
条件
单位
最小
典型
最大
VCC3=3.0
DDC=5.0
VCC3=3.0 至 3.6
DDC=3.0 至 5.5
VIK
VIH
钳位二极管电压
IIN=-18mA
-1.2
V
V
控制输入电压高平
2
V
VCC3=3.0 至 3.6
VIL
控制输入电压低平
0.8
1
V
VDDC=3.0 至 5.5
0 ≤ VSWTMDS ≤ VCC3
图 5
断开状态漏电流
TMDS 通道
V
V
CC3=3.6
DDC=5.5
IOZTMDS
-1
-5
µA
0 ≤ VSWDDC ≤ VDDC
图 5
断开状态漏电流
DDC/CEC 通道
V
V
CC3=3.6
DDC=5.5
IOZDDC
5
µA
控制输入漏电流
(STMDS, /OETMDS
V
V
CC3=3.6
DDC=5.5
IINTMDS
IINDDC
ICC3
VSWDDC=0 to VCC3
-1
-1
1
1
2
2
µA
µA
µA
µA
)
控制输入漏电流
V
V
CC3=3.6
DDC=5.5
VSWDDC=0 to VDDC
(SDDC, /OEDDC
)
V
V
CC3=3.6
DDC=5.5
VSWTMDS=VCC3 – 0.6
or VCC3, IOUT=0
静态供电电流 - TMDS
静态供电电流 - DDC
V
V
CC3=3.6
DDC=5.5
VSWDDC=0 或 VDDC
,
IDDC
I
OUT=0
一端输入3.0V;
其它输入在 VCC3-0.6
或 VCC3
VCC3=3.6
∆ICCT3
I
I
CC3的增值
DDC的增值
100
15
µA
µA
VCC5=5.5
一端输入3.0V;
其它输入在 VDDC
V
V
CC3=3.6
CC5=5.5
∆ICCTD
© 2006 Fairchild Semiconductor Corporation
FSHDMI08 Rev. 1.0.4
www.fairchildsemi.com
5
AC电气特性
如无其它规定，均为在 25°C 下 VCC3=3.3V, VDDC=5.0V 的典型值.
TA=- 40ºC 至 +85ºC
表达符号
参数
VCC3 / VDDC (V)
条件
单位
最小
典型
最大
TMDS通道
VSWTMDS=VCC3 -0.5,
打开时间
S, /OE 到输出
V
CC3=3.0 至 3.6
RPU=50Ω, CL=5pf
tONTMDS
tOFFTMDS
tBBM-TMDS
4
2
6
4
VDDC=5.0
图 6, 图 7
ns
VSWTMDS=VCC3 -0.5,
关闭时间
S 到输出
V
CC3=3.0 至 3.6
RPU=50Ω, CL=5pf
VDDC=5.0
图 6,图 7
VSWTMDS=VCC3 -0.5,
VCC3=3.0 至 3.6
DDC=5.0
先断后通时间(2)
开关传输延迟(2)
1
ns
ps
RPU=50Ω, CL=5pf
V
图 15
RPU=50Ω, CL=5pf
图 14
VCC3=3.0 至 3.6
DDC=5.0
tpd (tpLH, pHL
t
)
4000
90
V
f=165MHz clock with 50%
duty cycle, RPU=50Ω,
CL=5pf
VCC3=3.0 至 3.6
DDC=5.0
tjitter
总抖动 (DJ+RJ)
ps
V
图 14
f=165MHz clock with 50%
duty cycle, RPU=50Ω,
CL=5pf
VCC3=3.0 至 3.6
tratio
tSK1
tSK2
占空比
40
50
55
90
60
%
ps
ps
VDDC =5.0
图 14
差分对间延迟差
(TMDS Cn+ 至
Cn-)
f=1.65Gbps, 223-1 PRBS,
VCC3=3.0 至 3.6
100
160
RPU=50Ω, CL=5p图 14
VDDC=5.0
f=1.65Gbps, 223-1 PRBS,
差分对内延迟差
(任意两个TMDS
开关通道之间)
RPU=50Ω,
VCC3=3.0 至 3.6
CL=5pf
图 14
VDDC=5.0
RT=50Ω, f=370MHz
图 10
VCC3=3.0 至 3.6
DDC=5.0
-30
-25
-25
-20
V
隔离度
(TMDS通道)
OIRRTMDS
dB
RT=50Ω, f=825MHz
图 10
VCC3=3.0 至 3.6
DDC=5.0
V
RT=50Ω, f=370MHz
图 11
VCC3=3.0 至 3.6
VDDC=5.0
非相邻通道串扰
(TMDS通道)
XtalkTMDS
dB
RT=50Ω, f=825MHz
图 11
VCC3=3.0 至 3.6
VDDC=5.0
VCC3=3.3
fmax
最大数据波特(2)
1.65
Gbps
VDDC=5.0
控制通道 – DDC / CEC
打开时间; SDDC
/OEDDC到输出
,
V
V
CC3=3.3
DDC=3.0 至 5.5 CL=5pf
VSWDDC=2V, RDDC=1kΩ,
tONDDC
28
24
ns
ns
关闭时间; SDDC
/OEDDC 到输出
,
V
V
CC3=3.3
DDC=3.0 至 5.5 CL=5pf
VSWDDC=2V, RL=1kΩ,
tOFFDDC
注:
2. 以上参数由特性和设计保证.
© 2006 Fairchild Semiconductor Corporation
FSHDMI08 Rev. 1.0.4
www.fairchildsemi.com
6
测试图
VON
Dm,CLKm
CEC,HPD,
SCL, SDA
,
nDm,nCLKm,
CECn,HPDn,
SCLn, SDAn
IOZ
NC
Dm ,CLKm
CEC,HPD,
SCL,SDA
,
A
V
SW
Select
V
SW
GND
=
0 or Vcc3
ION
GND
VCNTRLT
VCNTRLD = 0 or VDDC
Select
GND
V
V
CNTRLT = 0 or Vcc3
Each switch port is tested separately.
CNTRLD = 0 or VDDC
R
ON = V ON / I ON
图 4.
导通电阻
图 5.
断开漏电流
Vcc3
10mA
RPU
Generator
V
VOUT
SWTMDS
CL
GND
VCNTRLT
RPU and CL are functions of the application environment
(see AC/DC tables for values of CL and RPU).
CL includes test fixture and stray capacitance.
GND
图 6.
TMDS测试电路负载
nDm ,nCLKm
,
VDDC
CECn,HPDn,
SCLn,SDAn
RDDC
VSWDDC
VOUT
CL
GND
VCNTRLD
RPU and CL are functions of the application environment
(see AC/DC tables for values of CL and RDDC).
CL includes test fixture and stray capacitance.
GND
图 7.
DDC 测试电路负载
© 2006 Fairchild Semiconductor Corporation
FSHDMI08 Rev. 1.0.4
www.fairchildsemi.com
7
测试图
tRISE= 2.5ns
tFALL = 2.5ns
tRISE= 2.5ns
tFALL = 2.5ns
VDDC
V
CC3
90%
90%
90%
VCC3/2
90%
CC3 /2
Input - VCNTRLD
10%
Input- VCNTRLT
10%
VDDC /2
VDDC /2
V
10%
10%
GND
GND
VCC3
Output- VOUT
VOH
Output - VOUT
VOL
VDDC /2
10%
VOL + 0.3
10%
VCC3 – 0.5
tON
tON
tOFF
tOFF
图 8.
打开 / 关闭波形
图 9.
DDC打开 / 关闭波形
Network Analyzer
RS
VIN
VCNTRLT
VS
GND
RT
GND
GND
VOUT
RT
GND
Off Isolation = 20 Log (VOUT / VIN
GND
GND
)
图 10. 通道隔离度
Network Analyzer
NC
RS
VIN
VCNTRLT
VS
GND
GND
GND
RT
GND
VOUT
GND
RT
RS and RT are functions of the application
environment (see AC/DC tables for values).
GND
CROSSTALK = 20 Log (VOUT / V
)
IN
图 11. 非相邻通道间的串扰
© 2006 Fairchild Semiconductor Corporation
FSHDMI08 Rev. 1.0.4
www.fairchildsemi.com
8
测试图
VSW
VSW
Capacitance
Meter
Capacitance
Meter
VCNTRLT = 0 or VCC3
VCNTRLD = 0 or VDDC
f = 1MHz
VCNTRLT = 0 or VCC3
VCNTRLD = 0 or VDDC
VSW
f = 1MHz
图 12. 通道断开电容
图 13. 通道导通电容
tRISE = 240ps
tFALL= 240ps
+500mV
Input Differential Pair
1Dn+, 1Dn-,
80%
0V
80%
0V
Input- V
SWTMDS
2Dn+, 2Dn-,
1CLK+, 1CLK-,
2CLK+, 2CLK-,
20%
20%
-500mV
+500mV
t
t
SK1 = | t
- t
|
pHL
pLH
= |
tpLH/HL max. - tpLH/HL min.
|
SK2
Output Differential Pair
Dn+, Dn-,
Output- VOUT
0V
0V
CLK+, CLK-,
– 500mV
tpLH
tpHL
图 14. 差分对间和对内延迟差Tpd
tRISE = 2.5ns
VCC3
VCC3
10mA
90%
RPU
Input - VCNTRLT
10%
10mA
Generator
VCC3/2
GND
VOUT
CL
VCC3
GND
Output - VOUT
VOL
VCNTRLT
10%
tBBM
GND
RPU and CL are functions of the application
environment (see AC/DC tables for values).
CL includes test fixture and stray capacitance.
图 15. 先断后开
© 2006 Fairchild Semiconductor Corporation
FSHDMI08 Rev. 1.0.4
www.fairchildsemi.com
9
物理尺寸
A
56
51
34
29
B
8.10
4.05
0.2 C B
A
1
6
23
28
0.30
0.50
0.1 C
-C-
0.50
0.10
A
B
C
0.25
MTD56REV3
图 16. 56-引脚，超薄小封装 (TSSOP)
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© 2006 Fairchild Semiconductor Corporation
FSHDMI08 Rev. 1.0.4
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© 2006 Fairchild Semiconductor Corporation
FSHDMI08 Rev. 1.0.4
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