FSL206MRBN_技术文档

Green Mode Power Switch

FSL206MR

Description

The FSL206MR integrated Pulse−Width Modulator (PWM) and

®

SENSEFET is specifically designed for high−performance offline

Switched−Mode Power Supplies (SMPS) while minimizing external

components. This device integrates high−voltage power regulators

that combine an avalanche−rugged SENSEFET with a Current−Mode

PWM control block.

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The integrated PWM controller includes: a 7.8 V regulator,

eliminating the need for auxiliary bias winding; Under−Voltage

Lockout (UVLO) protection; Leading−Edge Blanking (LEB); an

optimized gate turn−on/turn−off driver; EMI attenuator; Thermal

Shutdown (TSD) protection; temperature−compensated precision

current sources for loop compensation; soft−start during startup; and

fault−protection circuitry such as Overload Protection (OLP),

Over−Voltage Protection (OVP), Abnormal Over−Current Protection

(AOCP), and Line Under−Voltage Protection (LUVP).

PDIP8 9.42x6.38, 2.54P

CASE 646CM

PDIP8 9.59x6.6, 2.54P

CASE 646CN

The internal high−voltage startup switch and the Burst−Mode

operation with very low operating current reduce the power loss in

Standby Mode. As a result, it is possible to reach a power loss of

150 mW with no bias winding and 25 mW (for FSL206MR) or

30 mW (for FSL206MRBN) with a bias winding under no−load

conditions when the input voltage is 265 Vac.

PDIP8 GW

CASE 709AJ

MARKING DIAGRAM

Features

• Internal Avalanche−Rugged SENSEFET 650 V

• Precision Fixed Operating Frequency: 67 kHz

$Y&E&Z&2&K

FSL206MR

• No−Load < 150 mW at 265 Vac without Bias Winding; <25 mW with

Bias Winding for FSL206MR, < 30 mW with Bias Winding for

FSL206MRBN

• No Need for Auxiliary Bias Winding

• Frequency Modulation for Attenuating EMI

• Line Under−Voltage Protection (LUVP)

• Pulse−by−Pulse Current Limiting

$Y

&E

&Z

&2

&K

= ON Semiconductor Logo

= Designated Space

= Assembly Plant Code

= 2−Digit Date code format

= 2−Digits Lot Run Traceability Code

FSL206MR = Specific Device Code Data

• Low Under−Voltage Lockout (UVLO)

• Ultra−Low Operating Current: 300 mA

• Built−In Soft−Start and Startup Circuit

$Y&Z&2&K

L206MRB

• Various Protections: Overload Protection (OLP), Over−Voltage

Protection (OVP), Thermal Shutdown (TSD), Abnormal

Over−Current Protection (AOCP) Auto−Restart Mode for All

Protections

$Y

&Z

= ON Semiconductor Logo

= Assembly Plant Code

&2

&K

L206MRB

= 2−Digit Date code format

= 2−Digits Lot Run Traceability Code

= Specific Device Code Data

Applications

• SMPS for STB, DVD & DVCD Players

• SMPS for Auxiliary Power

Related Resources

ORDERING INFORMATION

• https://www.onsemi.com/PowerSolutions/home.do

• https://www.onsemi.com/pub/Collateral/AN−4137.pdf.pdf

• https://www.onsemi.com/pub/Collateral/AN−4141.pdf.pdf

• https://www.onsemi.com/pub/Collateral/AN−4150.pdf.pdf

See detailed ordering and shipping information on page 2 of

this data sheet.

1

Publication Order Number:

March, 2020 − Rev. 4

FSL206MR/D

FSL206MR

ORDERING INFORMATION

Output Power Table (Note 1)

230 Vac

+ 15% (Note 2)

85 ∼265 Vac

Open Frame

(Note 3)

Open Frame

(Note 3)

Operating

Temperature

PKG

Packing Method

Top Mark

FSL206MR

L206MRB

FSL206MR

Part Number

FSL206MRN

FSL206MRBN

FSL206MRL

FSL206MRLX

Current Limit

R

DS(ON),MAX

−40 ∼ 115°C

8−DIP

Tube

0.6 A

19 W

12 W

7 W

8−LSOP

Tube

Tape & Reel

1. The junction temperature can limit the maximum output power.

2. 230 Vac or 100/115 Vac with doubler. The maximum power with CCM operation.

3. Maximum practical continuous power in an open−frame design at 50°C ambient.

APPLICATION DIAGRAM

AC

IN

AC

IN

DC

OUT

DC

OUT

V_STR

Drain

V_STR

Drain

LS

PWM

V_FB

V_CCGND

V_FB

V_CCGND

(a) With Bias Winding

(b) Without Bias Winding

Figure 1. Typical Application

INTERNAL BLOCK DIAGRAM

8

7.8V

V

Good

CC

7V/8V

“H” if V < 1.5V

LS

“L” if V > 2V

LS

V

CC

Q

V

Good

CC

Figure 2. Internal Block Diagram

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2

FSL206MR

PIN CONFIGURATION

GND

Drain

V

Drain

CC

8−DIP

V

FB

8−LSOP

V

STR

LS

Figure 3. Pin Configuration

PIN DEFINITIONS

Pin No.

Name

GND

VCC

Description

1

2

Ground. SENSEFET source terminal on the primary side and internal control ground.

Positive Supply Voltage Input. Although connected to an auxiliary transformer winding, current is supplied from pin

5 (V

) via an internal switch during startup (see Figure 2). Once V reaches the UVLO upper threshold (12 V),

CC

STR

the internal startup switch opens and device power is supplied via the auxiliary transformer winding.

3

VFB

Feedback Voltage. Non−inverting input to the PWM comparator, with a 0.11 mA current source connected internally

and a capacitor and opto−coupler typically connected externally. There is a delay while charging external capacitor

C

from 2.4 V to 5 V using an internal 2.7 mA current source. This delay prevents false triggering under transient

FB

conditions, but allows the protection mechanism to operate under true overload conditions.

4

5

LS

Line Sense Pin This pin is used to protect the device when the input voltage is lower than the rated input voltage

range. If this pin is not used, connect to ground.

VSTR

Startup. Connected to the rectified AC line voltage source. At startup, the internal switch supplies internal bias and

charges an external storage capacitor placed between the V pin and ground. Once V reaches 8 V, all internal

CC

blocks are activated. After that, the internal high−voltage regulator (HV REG) turns on and off irregularly to maintain

at 7.8 V.

V

CC

6, 7, 8

Drain Drain. Designed to connect directly to the primary lead of the transformer and capable of switching a maximum of

650 V. Minimizing the length of the trace connecting these pins to the transformer decreases leakage inductance.

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3

FSL206MR

ABSOLUTE MAXIMUM RATINGS (T = 25°C unless otherwise specified)

A

Symbol

Parameter

Min

−0.3

−

Max

Unit

V

STR

V

Pin Voltage

650

STR

V

Drain Pin Voltage

Supply Voltage

LS Pin Voltage

650

V

DS

CC

V

26

V

LS

V

FB

−

Internally Clamped Voltage (Note 4)

V

Feedback Voltage Range

−0.3

−

Internally Clamped Voltage (Note 4)

V

I

Drain Current Pulsed (Note 5)

Single−Pulsed Avalanche Energy (Note 6)

Total Power Dissipation

1.5

11

A

DM

E

AS

−

mJ

W

°C

kV

P

D

−

1.3

+150

+125

+150

4

T

J

Operating Junction Temperature

Operating Ambient Temperature

Storage Temperature

−40

−55

−

T

A

T

STG

ESD

Human Body Model, JESD22−A114

Charged Device Model, JESD22−C101

−

2

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

4. V is clamped by internal clamping diode (13 V I

< 100 mA). After Shutdown, before V reaching V

, V < V < V

.

FB

CLAMP_MAX

CC

STOP SD

FB

CC

5. Repetitive rating: pulse−width limited by maximum junction temperature.

6. L = 21 mH, starting T = 25°C

J

THERMAL IMPEDANCE (T = 25°C unless otherwise specified)

A

Symbol

Parameter

Value

Unit

°C/W

q

Junction−to−Ambient Thermal Impedance (Note 7)

93

JA

7. JEDEC recommended environment, JESD51−2 and test board, JESD51−10 with minimum land pattern for 8DIP and JESD51−3 with

minimum land pattern for 8LSOP.

ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified)

A

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

SENSEFET SECTION

BV

Drain−Source Breakdown

Voltage

V

CC

= 0 V, I = 250 mA

650

−

DSS

D

V

I

Zero Gate Voltage Drain Current

V

DS

V

DS

V

GS

= 650 V, V = 0 V

−

50

250

19

mA

W

DSS

GS

= 520 V, V = 0 V, T = 125°C (Note 8)

GS

A

R

Drain−Source On−State

Resistance (Note 9)

= 10 V, I = 0.3 A

14

DS(ON)

D

C

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

Rise Time

V

GS

V

GS

V

GS

V

DS

V

DS

= 0 V, V = 25 V, f = 1 MHz

−

162

14.9

2.7

−

pF

ns

ISS

DS

C

= 0 V, V = 25 V, f = 1 MHz

DS

OSS

RSS

C

= 0 V, V = 25 V, f = 1 MHz

DS

t

r

= 325 V, I = 0.5 A, R = 25 W

6.1

D

G

t

f

Fall Time

= 325 V, I = 0.5 A, R = 25 W

43.6

D

G

CONTROL SECTION

f

Switching Frequency

V

= 4 V, V = 10 V

61

−

67

5

73

10

−

KHz

%

OSC

FB

CC

Df

Switching Frequency Variation

Frequency Modulation (Note 8)

Maximum Duty Cycle

−25°C < T < 85°C

J

OSC

f

M

−

3

kHz

%

D

V

= 4 V, V = 10 V

66

0

72

0

78

0

MAX

FB

CC

D

Minimum Duty Ratio

= 0 V, V = 10 V

%

MIN

FB

CC

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4

FSL206MR

ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise specified) (continued)

A

Symbol

Parameter

Test Condition

= 0 V, V Sweep

Min

7

Typ

8

Max

9

Unit

V

START

UVLO Threshold Voltage

V

FB

CC

V

STOP

After Turn−on

6

7

8

V

I

Feedback Source Current

V

FB

V

FB

= 0, V = 10 V

90

10

110

15

130

20

mA

ms

FB

CC

t

Internal Soft−Start Time

= 4 V, V = 10 V

S/S

CC

BURST−MODE SECTION

V

Burst−Mode HIGH

V

= 10 V

FSL206MR

FSL206MRB

FSL206MR

FSL206MRB

FSL206MR

FSL206MRB

0.66

0.40

0.59

0.28

−

0.83

0.50

0.74

0.35

90

1.00

0.60

0.89

0.42

−

V

BURH

CC

FB

Threshold Voltage

Increase

V

Burst−Mode LOW

Threshold Voltage

V

CC

V

FB

= 10 V

Decrease

V

BURL

V

HYS

Burst−Mode Hysteresis

mV

BUR

−

150

−

PROTECTION SECTION

I

Peak Current Limit

V

= 4 V, di/dt = 300 mA/ms, V = 10 V

0.54

−

0.60

100

5.0

2.7

−

0.66

−

A

ns

V

LIM

FB

CC

t

Current Limit Delay Time (Note 8)

Shutdown Feedback Voltage

Shutdown Delay Current

CLD

V

SD

DELAY

V

= 10 V

= 4 V

4.5

2.1

250

5.5

3.3

−

CC

I

mA

ns

FB

t

Leading Edge Blanking Time

(Note 8)

LEB

V

AOCP

Abnormal Over−Current

Protection (Note 8)

−

0.7

−

V

Over−Voltage Protection

V

FB

V

FB

V

FB

= 4 V, V Increase

23.0

1.9

24.5

2.0

26.0

2.1

V

OVP

CC

V

Line−Sense Protection On to Off

Line−Sense Protection Off to On

= 3 V, V = 10 V, V Decrease

CC LS

LS_OFF

V

= 3 V, V = 10 V, V Increase

1.4

1.5

1.6

V

LS_ON

CC

LS

TSD

Thermal Shutdown Temperature

(Note 8)

125

135

150

°C

HYS

TSD Hysteresis Temperature

(Note 8)

−

60

−

°C

TSD

HIGH VOLTAGE REGULATOR SECTION

HV Regulator Voltage

TOTAL DEVICE SECTION

H

V

FB

= 0 V, V

= 40 V

7.8

V

HVR

STR

I

Operating Supply Current (Control V = 15 V, 0 V < V < V

BURL

−

0.3

0.25

−

0.5

0.45

1.3

mA

OP1

OP2

OP3

CC

FB

Part Only, without Switching)

Operating Supply Current (Control V = 8 V, 0 V < V < V

BURL

CC

FB

Part Only, without Switching)

Operating Supply Current (Note 8) V = 15 V, V

< V < V

FB SD

CC

BURL

(While Switching)

I

Startup Charging Current

Startup Current

V

CC

V

CC

V

CC

= 0 V, V > 40 V

STR

1.6

−

1.9

100

26

2.4

150

−

mA

V

CH

I

= Before V , V = 0 V

START FB

START

V

STR

Minimum V

Supply Voltage

= V = 0 V, V Increase

STR

−

STR

FB

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

8. Though guaranteed by design, it is not 100% tested in production.

9. Pulse test: pulse width = 300 ms, duty cycle = 2%.

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5

FSL206MR

TYPICAL PERFORMANCE CHARACTERISTICS

HV Regulator Voltage (V

)

Operating Frequency (f _OSC

)

HVR

1.4

1.3

1.2

1.1

1

1.4

1.3

1.2

1.1

1

0.9

0.8

0.7

0.6

0.9

0.8

0.7

0.6

‐40℃ ‐25℃

0℃ 25℃

50℃ 75℃

90℃ 110℃ 115℃

‐40℃

‐25℃

0℃

25℃

50℃

75℃

90℃

110℃

Figure 4. Operating Frequency vs. Temperature

Figure 5. HV Regulator Voltage vs. Temperature

Stop Theshold Voltage (V

)

Start Theshold Voltage (V_START

)

STOP

1.4

1.3

1.2

1.1

1

1.4

1.3

1.2

1.1

1

0.9

0.8

0.7

0.6

0.9

0.8

0.7

0.6

‐40℃

‐25℃

0℃

25℃

50℃

75℃

90℃

110℃

‐40℃

‐25℃

0℃

25℃

50℃

75℃

90℃

110℃

Figure 6. Start Threshold Voltage vs. Temperature

Figure 7. Stop Threshold Voltage vs. Temperature

Feedback Source Current (I_FB

)

Peak Current Limit (I_LIM

)

1.4

1.3

1.2

1.1

1

1.4

1.3

1.2

1.1

1

0.9

0.8

0.7

0.6

0.9

0.8

0.7

0.6

‐40℃ ‐25℃

0℃

25℃

50℃

75℃

90℃ 110℃

‐40℃

‐25℃

0℃

25℃

50℃

75℃

90℃

110℃

Figure 8. Feedback Source Current vs. Temperature

Figure 9. Peak Current Limit vs. Temperature

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6

FSL206MR

TYPICAL PERFORMANCE CHARACTERISTICS (Continued)

(These Characteristic graphs are normalized at T = 25.)

A

Startup Charging Current (I_CH

)

Operating Supply Current (Iop1)

1.4

1.3

1.2

1.1

1

1.4

1.3

1.2

1.1

1

0.9

0.8

0.7

0.6

0.9

0.8

0.7

0.6

‐40℃

‐25℃

0℃

25℃

50℃

75℃

90℃

110℃

‐40℃

‐25℃

0℃

25℃

50℃

75℃

90℃

110℃

Figure 10. Startup Charging Current vs. Temperature

Figure 11. Operating Supply Current 1

vs. Temperature

Operating Supply Current (Iop2)

Over‐Voltage Protection (V

)

OVP

1.4

1.3

1.2

1.1

1

1.4

1.3

1.2

1.1

1

0.9

0.8

0.7

0.6

0.9

0.8

0.7

0.6

‐40℃

‐25℃

0℃

25℃

50℃

75℃

90℃

110℃

‐40℃

‐25℃

0℃

25℃

50℃

75℃

90℃

110℃

Figure 12. Operating Supply Current 2

vs. Temperature

Figure 13. Over−Voltage Protection Voltage

vs. Temperature

Shutdown Delay Current (I_DELAY

)

1.4

1.3

1.2

1.1

1

0.9

0.8

0.7

0.6

‐40℃

‐25℃

0℃

25℃

50℃

75℃

90℃

110℃

Figure 14. Shutdown Delay Current vs. Temperature

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7

FSL206MR

Feedback Control

FUNCTIONAL DESCRIPTION

FSL206MR employs current−mode control, as shown in

Figure 17. An opto−coupler (such as the FOD817A) and

shunt regulator (such as the KA431) are typically used to

implement the feedback network. Comparing the feedback

Startup

At startup, an internal high−voltage current source

supplies the internal bias and charges the external capacitor

(C ) connected with the V pin, as illustrated in Figure 15.

A

CC

voltage with the voltage across the R

resistor makes it

SENSE

An internal high−voltage regulator (HV REG) located

between the V and V pins regulates the V to 7.8 V

and supplies operating current. Therefore, FSL206MR

needs no auxiliary bias winding.

possible to control the switching duty cycle. When the shunt

regulator reference pin voltage exceeds the internal

reference voltage of 2.5 V, the optocoupler LED current

STR

CC

increases, the feedback voltage V is pulled down, and the

FB

duty cycle is reduced. This typically occurs when the input

voltage is increased or the output load is decreased.

V_DC,link

V_STR

2

I_CH

V_CC

7.8V

HV/REG

UVLO

3

I_START

C_A

V_REF

Figure 15. Startup Block

Oscillator Block

Figure 17. Pulse−Width−Modulation (PWM) Circuit

The oscillator frequency is set internally and the power

switch has a random frequency fluctuation function.

Fluctuation of the switching frequency of a switched power

supply can reduce EMI by spreading the energy over a wider

frequency range than the bandwidth measured by the EMI

test equipment. The amount of EMI reduction is directly

related to the range of the frequency variation. The range of

frequency variation is fixed internally; however, its

selection is randomly chosen by the combination of external

feedback voltage and internal free−running oscillator. This

randomly chosen switching frequency effectively spreads

the EMI noise nearby switching frequency and allows the

use of a cost−effective inductor instead of an AC input line

filter to satisfy the world−wide EMI requirements.

Leading−Edge Blanking (LEB)

At the instant the internal SENSEFET is turned on, the

primary−side capacitance and secondary−side rectifier

diode reverse recovery typically cause a high−current spike

through the SENSEFET. Excessive voltage across the

R

SENSE

resistor leads to incorrect feedback operation in the

current−mode PWM control. To counter this effect, the

power switch employs a leading−edge blanking (LEB)

circuit (see the Figure 17). This circuit inhibits the PWM

comparator for a short time (t

turned on.

) after the SENSEFET is

LEB

Protection Circuits

The protective functions include Overload Protection

(OLP), Over−Voltage Protection (OVP), Under−Voltage

Lockout (UVLO), Line Under−Voltage Protection (LUVP),

Abnormal Over−Current Protection (AOCP), and thermal

shutdown power switch. Because these protection circuits

are fully integrated inside the IC without external

components, reliability is improved without increasing cost.

Once a fault condition occurs, switching is terminated and

I_DS

several

mseconds

t_SW=1/f_SW

t_SW

t

Dt

the SENSEFET remains off. This causes V to fall. When

f_SW

CC

MAX

f

_SW+1/2Df_SW

V

CC

reaches the UVLO stop voltage V

(7 V), the

STOP

protection is reset and the internal high− voltage current

source charges the V capacitor via the V pin. When

MAX

no repetition

f

_SW-1/2Df_SW

CC

STR

several

milliseconds

V

CC

reaches the UVLO start voltage V

(8 V), the FPS

START

resumes normal operation. In this manner, auto−restart can

alternately enable and disable the switching of the power

SENSEFET until the fault condition is eliminated.

t

Figure 16. Frequency Fluctuation Waveform

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8

FSL206MR

Abnormal Over−Current Protection (AOCP)

When the secondary rectifier diodes or the transformer pin

are shorted, a steep current with extremely high di/dt can

flow through the SENSEFET during the LEB time. Even

though the power switch has OLP (Overload Protection), it

is not enough to protect the FPS in that abnormal case, since

severe current stress is imposed on the SENSEFET until

OLP triggers. The power switch includes the internal AOCP

(Abnormal Over−Current Protection) circuit shown in

Figure 20. When the gate turn−on signal is applied to the

power SENSEFET, the AOCP block is enabled and monitors

the current through the sensing resistor. The voltage across

the resistor is compared with a preset AOCP level. If the

sensing resistor voltage is greater than the AOCP level, the

set signal is applied to the latch, resulting in the shutdown of

the SMPS.

Figure 18. Auto−Restart Protection Waveforms

Overload Protection (OLP)

Overload is defined as the load current exceeding a preset

level due to an unexpected event. In this situation, the

protection circuit should be activated to protect the SMPS.

However, even when the SMPS is operating normally, the

overload protection (OLP) circuit can be activated during

the load transition or startup. To avoid this undesired

operation, the OLP circuit is activated after a specified time

to determine whether it is a transient situation or a true

overload situation. The Current−Mode feedback path limits

the current in the SENSEFET when the maximum PWM

duty cycle is attained. If the output consumes more than this

Figure 20. Abnormal Over−Current Protection

Thermal Shutdown (TSD)

The SENSEFET and control IC being integrated makes it

easier to detect the temperature of the SENSEFET. When the

junction temperature exceeds ~135°C, thermal shutdown is

activated and the power switch is restarted after temperature

decreases to 60°C.

maximum power, the output voltage (V ) decreases below

O

its rating voltage. This reduces the current through the

opto−coupler LED, which also reduces the opto−coupler

transistor current, increasing the feedback voltage (V ). If

FB

V

exceeds 2.4 V, the feedback input diode is blocked and

FB

Over−Voltage Protection (OVP)

the 2.7 mA current source (I

slowly up. In this condition, V increases until it reaches

5 V, when the switching operation is terminated, as shown

in Figure 19. The shutdown delay is the time required to

charge C from 2.4 V to 5 V with 2.7 mA current source.

) starts to charge C

DELAY

FB

In the event of a malfunction in the secondary−side

feedback circuit or an open feedback loop caused by

a soldering defect, the current through the opto−coupler

transistor becomes almost zero (refer to Figure 17). Then

FB

V

FB

climbs up in a similar manner to the overload situation,

forcing the preset maximum current to be supplied to the

SMPS until the overload protection is activated. Because

excess energy is provided to the output, the output voltage

may exceed the rated voltage before the overload protection

is activated, resulting in the breakdown of the devices in the

secondary side. To prevent this situation, an over−voltage

V_FB

Overload Protection

protection (OVP) circuit is employed. In general, V is

CC

2.4V

proportional to the output voltage and the FPS uses V

instead of directly monitoring the output voltage. If V

CC

t₁₂= C_FB× (V(t )−V(t₁)) / I

CC

2

DELAY

exceeds 24.5 V, OVP circuit is activated, resulting in

termination of the switching operation. To avoid undesired

t₁

t₂

t

activation of OVP during normal operation, V should be

designed to be below 24.5 V.

CC

Figure 19. Overload Protection (OLP)

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9

FSL206MR

Line Under−Voltage Protection (LUVP)

Burst Operation

If the input voltage of the converter is lower than the

minimum operating voltage, the converter input current

increases too much, causing components failure. If the input

voltage is low, the converter should be protected. In the

FSL206MR, the LUVP circuit senses the input voltage using

the LS pin and, if this voltage is lower than 1.5 V, the LUVP

signal is generated. The comparator has 0.5 V hysteresis. If

the LUVP signal is generated, the output drive block is shut

down and the output voltage feedback loop is saturated.

To minimize power dissipation in Standby Mode, the

power switch enters Burst Mode. As the load decreases, the

feedback voltage decreases. As shown in Figure 23, the

device automatically enters Burst Mode when the feedback

voltage drops below V

. Switching continues until the

BURH

feedback voltage drops below V . At this point,

BURL

switching stops and the output voltages start to drop at a rate

dependent on the standby current load. This causes the

feedback voltage to rise. Once it passes V

, switching

BURH

resumes. The feedback voltage then falls and the process

repeats. Burst Mode alternately enables and disables

switching of the SENSEFET and reduces switching loss in

Standby Mode.

−

+

Figure 21. Line UVP Circuit

Soft−Start

The FSL206MR has an internal soft−start circuit that

slowly increases the feedback voltage, together with the

SENSEFET current, after it starts. The typical soft−start

time is 15 ms, as shown in Figure 22, where progressive

increments of the SENSEFET current are allowed during the

startup phase. The pulse width to the power switching device

is progressively increased to establish the correct working

conditions for transformers, inductors, and capacitors. The

voltage on the output capacitors is progressively increased

with the intention of smoothly establishing the required

output voltage. It also helps prevent transformer saturation

and reduce the stress on the secondary diode.

Figure 23. Burst−Mode Operation

Figure 22. Internal Soft−Start

SENSEFET is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States

and/or other countries.

www.onsemi.com

10

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

PDIP8 9.42x6.38, 2.54P

CASE 646CM

ISSUE O

DATE 31 JUL 2016

9.83

9.00

8

1

5

6.670

6.096

4

8.255

TOP VIEW

7.610

1.65

1.27

(0.56)

7.62

3.683

3.200

5.08 MAX

3.60

3.00

0.33 MIN

0.356

0.200

15

°

0.560

0.355

°

0

2.54

9.957

7.62

FRONT VIEW

7.870

SIDE VIEW

NOTES:

A. CONFORMS TO JEDEC MS−001, VARIATION BA

B. ALL DIMENSIONS ARE IN MILLIMETERS

C. DIMENSIONS ARE EXCLUSIVE OF BURRS,

MOLD FLASH, AND TIE BAR EXTRUSIONS

D. DIMENSIONS AND TOLERANCES PER ASME

Y14.5M−2009

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON13468G

PDIP8 9.42X6.38, 2.54P

PAGE 1 OF 1

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

www.onsemi.com

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

PDIP8 9.59x6.6, 2.54P

CASE 646CN

ISSUE O

DATE 31 JUL 2016

0.400 10.160

0.355

[

9.017

]

8

5

PIN 1 INDICATOR

0.280 7.112

0.240 6.096

[

]

1

4

HALF LEAD STYLE 4X

0.031 [0.786] MIN

FULL LEAD STYLE 4X

0.010 [0.252] MIN

0.325 8.263

0.300 7.628

[

]

0.195 4.965

MAX 0.210 [5.334]

0.115

2.933

[ ]

SEATING PLANE

0.150 3.811

0.115

2.922

[ ]

C

MIN 0.015 [0.381]

0.100 [2.540]

0.300 [7.618]

4X

(0.031 [0.786])

0.430 [10.922]

MAX

0.022 0.562

0.014

[ ]

0.358

4X FOR 1/2 LEAD STYLE

8X FOR FULL LEAD STYLE

0.070 1.778

0.045 1.143

0.10

C

[

]

NOTES:

A)THIS PACKAGE CONFORMS TJOEDEC MS−001 VARIATION BA WHICH DEFINES

2 VERSIONS OF THE PACKAGE TERMINAL STYLE WHICH ARE SHOWN HERE.

B) CONTROLING DIMS ARE IN INCHES

C)DIMENSIONS ARE EXCLUSIVE OF BURRSM,OLD FLASH, AND TIE BAR EXTRUSIONS.

D) DIMENSIONS AND TOLERANCES PER ASME Y14.5M−2009

98AON13470G

DOCUMENT NUMBER:

STATUS:

Electronic versions are uncontrolled except when

accessed directly from the Document Repository. Printed

versions are uncontrolled except when stamped

“CONTROLLED COPY” in red.

ON SEMICONDUCTOR STANDARD

NEW STANDARD:

Case Outline Number:

http://onsemi.com

1

October, 2002 − Rev. 0

DESCRIPTION: PDIP8 9.59X6.6, 2.54P

PAGE 1 OFX2XX

DOCUMENT NUMBER:

98AON13470G

PAGE 2 OF 2

ISSUE

REVISION

DATE

31 JUL 2016

O

RELEASED FOR PRODUCTION FROM FAIRCHILD N08M TO ON

SEMICONDUCTOR. REQ. BY I. CAMBALIZA.

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

Case Outline Number:

July, 2016 − Rev. O

646CN

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

PDIP8 GW

CASE 709AJ

ISSUE O

DATE 31 JAN 2017

98AON13756G

ON SEMICONDUCTOR STANDARD

DOCUMENT NUMBER:

STATUS:

Electronic versions are uncontrolled except when

accessed directly from the Document Repository. Printed

versions are uncontrolled except when stamped

“CONTROLLED COPY” in red.

NEW STANDARD:

Case Outline Number:

http://onsemi.com

1

October, 2002 − Rev. 0

DESCRIPTION: PDIP8 GW

PAGE 1 OFX2XX

DOCUMENT NUMBER:

98AON13756G

PAGE 2 OF 2

ISSUE

REVISION

DATE

O

RELEASED FOR PRODUCTION FROM FAIRCHILD MKT−MLSOP08A TO ON

SEMICONDUCTOR. REQ. BY D. TRUHITTE.

31 JAN 2017